Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: a7f77545d401266a6415e6e03c7738c95314f0e6
https://github.com/qemu/qemu/commit/a7f77545d401266a6415e6e03c7738c95314f0e6
Author: Stefan Hajnoczi <[email protected]>
Date: 2024-12-25 (Wed, 25 Dec 2024)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/plugin-gen.c
M accel/tcg/translate-all.c
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/exec/translator.h
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M include/hw/core/tcg-cpu-ops.h
M target/alpha/cpu.c
M target/alpha/cpu.h
M target/alpha/translate.c
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/tcg/cpu-v7m.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/translate.c
M target/avr/cpu.c
M target/avr/cpu.h
M target/avr/translate.c
M target/hexagon/cpu.c
M target/hexagon/cpu.h
M target/hexagon/fma_emu.c
M target/hexagon/fma_emu.h
M target/hexagon/op_helper.c
M target/hexagon/translate.c
M target/hppa/cpu.c
M target/hppa/cpu.h
M target/hppa/translate.c
M target/i386/tcg/helper-tcg.h
M target/i386/tcg/tcg-cpu.c
M target/i386/tcg/translate.c
M target/loongarch/cpu.c
M target/loongarch/internals.h
M target/loongarch/tcg/translate.c
M target/m68k/cpu.c
M target/m68k/cpu.h
M target/m68k/translate.c
M target/microblaze/cpu.c
M target/microblaze/cpu.h
M target/microblaze/translate.c
M target/mips/cpu.c
M target/mips/tcg/tcg-internal.h
M target/mips/tcg/translate.c
M target/openrisc/cpu.c
M target/openrisc/cpu.h
M target/openrisc/translate.c
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/translate.c
M target/riscv/cpu.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/rx/cpu.c
M target/rx/cpu.h
M target/rx/translate.c
M target/s390x/cpu.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/translate.c
M target/sh4/cpu.c
M target/sh4/cpu.h
M target/sh4/translate.c
M target/sparc/cpu.c
M target/sparc/cpu.h
M target/sparc/fop_helper.c
M target/sparc/helper.h
M target/sparc/translate.c
M target/tricore/cpu.c
M target/tricore/cpu.h
M target/tricore/translate.c
M target/xtensa/cpu.c
M target/xtensa/cpu.h
M target/xtensa/translate.c
M tcg/optimize.c
M tests/tcg/multiarch/system/memory.c
Log Message:
-----------
Merge tag 'pull-tcg-20241224' of https://gitlab.com/rth7680/qemu into staging
tcg/optimize: Remove in-flight mask data from OptContext
fpu: Add float*_muladd_scalbn
fpu: Remove float_muladd_halve_result
fpu: Add float_round_nearest_even_max
fpu: Add float_muladd_suppress_add_product_zero
target/hexagon: Use float32_muladd
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
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# gpg: Signature made Tue 24 Dec 2024 15:04:04 EST
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20241224' of https://gitlab.com/rth7680/qemu: (72 commits)
accel/tcg: Move gen_intermediate_code to TCGCPUOps.translate_core
target/hexagon: Simplify internal_mpyhh setup
target/hexagon: Use mulu64 for int128_mul_6464
target/hexagon: Remove Double
target/hexagon: Remove Float
target/hexagon: Expand GEN_XF_ROUND
target/hexagon: Remove internal_fmafx
target/hexagon: Use float32_muladd for helper_sffm[as]_lib
target/hexagon: Use float32_muladd_scalbn for helper_sffma_sc
target/hexagon: Use float32_muladd for helper_sffms
target/hexagon: Use float32_muladd for helper_sffma
target/hexagon: Use float32_mul in helper_sfmpy
softfloat: Add float_muladd_suppress_add_product_zero
softfloat: Add float_round_nearest_even_max
softfloat: Remove float_muladd_halve_result
target/sparc: Use float*_muladd_scalbn
target/arm: Use float*_muladd_scalbn
softfloat: Add float{16,32,64}_muladd_scalbn
tcg/optimize: Move fold_cmp_vec, fold_cmpsel_vec into alphabetic sort
tcg/optimize: Move fold_bitsel_vec into alphabetic sort
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
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