Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 906853e1427a1ff89c64c0ebb6faa9c68f0a5d74
https://github.com/qemu/qemu/commit/906853e1427a1ff89c64c0ebb6faa9c68f0a5d74
Author: Anastasia Belova <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M hw/misc/arm_sysctl.c
Log Message:
-----------
hw/arm_sysctl: fix extracting 31th bit of val
1 << 31 is casted to uint64_t while bitwise and with val.
So this value may become 0xffffffff80000000 but only
31th "start" bit is required.
This is not possible in practice because the MemoryRegionOps
uses the default max access size of 4 bytes and so none
of the upper bytes of val will be set, but the bitfield
extract API is clearer anyway.
Use the bitfield extract() API instead.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Anastasia Belova <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: add clarification to commit message]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 593b910ebedb9f8969aba22ca35970f710722ba7
https://github.com/qemu/qemu/commit/593b910ebedb9f8969aba22ca35970f710722ba7
Author: Tigran Sogomonian <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M hw/misc/npcm7xx_mft.c
Log Message:
-----------
hw/misc: cast rpm to uint64_t
The value of an arithmetic expression
'rpm * NPCM7XX_MFT_PULSE_PER_REVOLUTION' is a subject
to overflow because its operands are not cast to
a larger data type before performing arithmetic. Thus, need
to cast rpm to uint64_t.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Tigran Sogomonian <[email protected]>
Reviewed-by: Patrick Leis <[email protected]>
Reviewed-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 16e8c947bd6f741d328bb1521f62f69dccaa3fe1
https://github.com/qemu/qemu/commit/16e8c947bd6f741d328bb1521f62f69dccaa3fe1
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M tests/qtest/boot-serial-test.c
Log Message:
-----------
tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests
Re-indent ASM comments adding the 'loop:' label.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: afd757e46166afe86a6df4407b64203e53ea44f4
https://github.com/qemu/qemu/commit/afd757e46166afe86a6df4407b64203e53ea44f4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M tests/qtest/boot-serial-test.c
Log Message:
-----------
tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests
Since registers are not modified, we don't need
to refill their values. Directly jump to the previous
store instruction to keep filling the TXDAT register.
The equivalent C code remains:
while (true) {
*UART_DATA = 'T';
}
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 80b8b01f89387181378aa251e7a5454470ec5045
https://github.com/qemu/qemu/commit/80b8b01f89387181378aa251e7a5454470ec5045
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M tests/qtest/boot-serial-test.c
Log Message:
-----------
tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test
In the next commit we are going to use a different value
for the $w1 register, maintaining the same $x2 value. In
order to keep the next commit trivial to review, set $x2
before $w1.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1bb7f615a517ba85ebdbbd30d8de2120b4598d12
https://github.com/qemu/qemu/commit/1bb7f615a517ba85ebdbbd30d8de2120b4598d12
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M tests/qtest/boot-serial-test.c
Log Message:
-----------
tests/qtest/boot-serial-test: Initialize PL011 Control register
The tests using the PL011 UART of the virt and raspi machines
weren't properly enabling the UART and its transmitter previous
to sending characters. Follow the PL011 manual initialization
recommendation by setting the proper bits of the control register.
Update the ASM code prefixing:
*UART_CTRL = UART_ENABLE | TX_ENABLE;
to:
while (true) {
*UART_DATA = 'T';
}
Note, since commit 51b61dd4d56 ("hw/char/pl011: Warn when using
disabled transmitter") incomplete PL011 initialization can be
logged using the '-d guest_errors' command line option.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 538b764d3417b9295cf7f8b617eb7bc90cbc4ad6
https://github.com/qemu/qemu/commit/538b764d3417b9295cf7f8b617eb7bc90cbc4ad6
Author: Peter Maydell <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M target/arm/helper.c
R target/arm/op_addsub.h
A target/arm/tcg/arith_helper.c
M target/arm/tcg/meson.build
A target/arm/tcg/op_addsub.c.inc
Log Message:
-----------
target/arm: Move minor arithmetic helpers out of helper.c
helper.c includes some small TCG helper functions used for mostly
arithmetic instructions. These are TCG only and there's no need for
them to be in the large and unwieldy helper.c. Move them out to
their own source file in the tcg/ subdirectory, together with the
op_addsub.h multiply-included template header that they use.
Since we are moving op_addsub.h, we take the opportunity to
give it a name which matches our convention for files which
are not true header files but which are #included from other
C files: op_addsub.c.inc.
(Ironically, this means that helper.c no longer contains
any TCG helper function definitions at all.)
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Alex Bennée <[email protected]>
Commit: 86a00f2046f5f5b613bdf18d6c972b495a907c37
https://github.com/qemu/qemu/commit/86a00f2046f5f5b613bdf18d6c972b495a907c37
Author: Pierrick Bouvier <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M docs/system/arm/cpu-features.rst
M target/arm/arm-qmp-cmds.c
M target/arm/cpu.h
M target/arm/cpu64.c
M tests/qtest/arm-cpu-features.c
Log Message:
-----------
target/arm: add new property to select pauth-qarma5
Before changing default pauth algorithm, we need to make sure current
default one (QARMA5) can still be selected.
$ qemu-system-aarch64 -cpu max,pauth-qarma5=on ...
Signed-off-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 39d70016d9abe15967f7051741dd5621c659b1f4
https://github.com/qemu/qemu/commit/39d70016d9abe15967f7051741dd5621c659b1f4
Author: Peter Maydell <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M tests/tcg/aarch64/Makefile.softmmu-target
Log Message:
-----------
tests/tcg/aarch64: force qarma5 for pauth-3 test
The pauth-3 test explicitly tests that a computation of the
pointer-authentication produces the expected result. This means that
it must be run with the QARMA5 algorithm.
Explicitly set the pauth algorithm when running this test, so that it
doesn't break when we change the default algorithm the 'max' CPU
uses.
Signed-off-by: Peter Maydell <[email protected]>
Commit: 132f8ec799cea261ad6b60ac8ae86f17cc98b9a1
https://github.com/qemu/qemu/commit/132f8ec799cea261ad6b60ac8ae86f17cc98b9a1
Author: Pierrick Bouvier <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M docs/system/arm/cpu-features.rst
M docs/system/introduction.rst
M hw/core/machine.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
Log Message:
-----------
target/arm: change default pauth algorithm to impdef
Pointer authentication on aarch64 is pretty expensive (up to 50% of
execution time) when running a virtual machine with tcg and -cpu max
(which enables pauth=on).
The advice is always: use pauth-impdef=on.
Our documentation even mentions it "by default" in
docs/system/introduction.rst.
Thus, we change the default to use impdef by default. This does not
affect kvm or hvf acceleration, since pauth algorithm used is the one
from host cpu.
This change is retro compatible, in terms of cli, with previous
versions, as the semantic of using -cpu max,pauth-impdef=on, and -cpu
max,pauth-qarma3=on is preserved.
The new option introduced in previous patch and matching old default is
-cpu max,pauth-qarma5=on.
It is retro compatible with migration as well, by defining a backcompat
property, that will use qarma5 by default for virt machine <= 9.2.
Tested by saving and restoring a vm from qemu 9.2.0 into qemu-master
(10.0) for cpus neoverse-n2 and max.
Signed-off-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 435d260e7ec5ff9c79e3e62f1d66ec82d2d691ae
https://github.com/qemu/qemu/commit/435d260e7ec5ff9c79e3e62f1d66ec82d2d691ae
Author: Pierrick Bouvier <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M docs/system/arm/virt.rst
Log Message:
-----------
docs/system/arm/virt: mention specific migration information
Signed-off-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
[PMM: Removed a paragraph about using non-versioned models.]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e8aa7fdcddfc8589bdc7c973a052e76e8f999455
https://github.com/qemu/qemu/commit/e8aa7fdcddfc8589bdc7c973a052e76e8f999455
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-01-13 (Mon, 13 Jan 2025)
Changed paths:
M docs/system/arm/cpu-features.rst
M docs/system/arm/virt.rst
M docs/system/introduction.rst
M hw/core/machine.c
M hw/misc/arm_sysctl.c
M hw/misc/npcm7xx_mft.c
M target/arm/arm-qmp-cmds.c
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/cpu64.c
M target/arm/helper.c
R target/arm/op_addsub.h
A target/arm/tcg/arith_helper.c
M target/arm/tcg/meson.build
A target/arm/tcg/op_addsub.c.inc
M tests/qtest/arm-cpu-features.c
M tests/qtest/boot-serial-test.c
M tests/tcg/aarch64/Makefile.softmmu-target
Log Message:
-----------
Merge tag 'pull-target-arm-20250113' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm_sysctl: fix extracting 31th bit of val
* hw/misc: cast rpm to uint64_t
* tests/qtest/boot-serial-test: Improve ASM
* target/arm: Move minor arithmetic helpers out of helper.c
* target/arm: change default pauth algorithm to impdef
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# gpg: Signature made Mon 13 Jan 2025 08:53:41 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250113' of
https://git.linaro.org/people/pmaydell/qemu-arm:
docs/system/arm/virt: mention specific migration information
target/arm: change default pauth algorithm to impdef
tests/tcg/aarch64: force qarma5 for pauth-3 test
target/arm: add new property to select pauth-qarma5
target/arm: Move minor arithmetic helpers out of helper.c
tests/qtest/boot-serial-test: Initialize PL011 Control register
tests/qtest/boot-serial-test: Reorder pair of instructions in PL011 test
tests/qtest/boot-serial-test: Reduce for() loop in PL011 tests
tests/qtest/boot-serial-test: Improve ASM comments of PL011 tests
hw/misc: cast rpm to uint64_t
hw/arm_sysctl: fix extracting 31th bit of val
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/dc26a2cd9cb6...e8aa7fdcddfc
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