Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ffd23ae2a6374c9754f33f992874722735cc7f7c
https://github.com/qemu/qemu/commit/ffd23ae2a6374c9754f33f992874722735cc7f7c
Author: Craig Blackmore <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: fix typo in vext continuous ldst function names
Replace `continus` with `continuous`.
Signed-off-by: Craig Blackmore <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d4ce7ef4b3b867e4d369f6024cf5f217f7bc2202
https://github.com/qemu/qemu/commit/d4ce7ef4b3b867e4d369f6024cf5f217f7bc2202
Author: Craig Blackmore <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: rvv: speed up small unit-stride loads and stores
Calling `vext_continuous_ldst_tlb` for load/stores up to 6 bytes
significantly improves performance.
Co-authored-by: Helene CHELIN <[email protected]>
Co-authored-by: Paolo Savini <[email protected]>
Co-authored-by: Craig Blackmore <[email protected]>
Signed-off-by: Helene CHELIN <[email protected]>
Signed-off-by: Paolo Savini <[email protected]>
Signed-off-by: Craig Blackmore <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e9952b3631b97f35d06052e0f3ec7ce812c9b539
https://github.com/qemu/qemu/commit/e9952b3631b97f35d06052e0f3ec7ce812c9b539
Author: Yanfeng Liu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/gdbstub.c
Log Message:
-----------
riscv/gdbstub: add V bit to priv reg
This adds virtualization mode (V bit) as bit(2) of register `priv`
per RiscV debug spec v1.0.0-rc4. Checked with gdb-multiarch v12.1.
Note that GDB may display `INVALID` tag for `priv` reg when V bit
is set, this doesn't affect actual access to the bit though.
Signed-off-by: Yanfeng Liu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3739732e755d84859fc2278ae3fff7d3869507b5
https://github.com/qemu/qemu/commit/3739732e755d84859fc2278ae3fff7d3869507b5
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shcounterenw
shcounterenw is defined in RVA22 as:
"For any hpmcounter that is not read-only zero, the corresponding bit in
hcounteren must be writable."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 8d6855ac7ef797f433c5b75f33e3be8f306eaa37
https://github.com/qemu/qemu/commit/8d6855ac7ef797f433c5b75f33e3be8f306eaa37
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shvstvala
shvstvala is defined in RVA22 as:
"vstval must be written in all cases described above for stval."
By "cases describe above" the doc refer to the description of sstvala:
"stval must be written with the faulting virtual address for load,
store, and instruction page-fault, access-fault, and misaligned
exceptions, and for breakpoint exceptions other than those caused by
execution of the EBREAK or C.EBREAK instructions. For
virtual-instruction and illegal-instruction exceptions, stval must be
written with the faulting instruction."
We already have sstvala, and our vstval follows the same rules as stval,
so we can claim to support shvstvala too.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e306fff7f83285a385c29927833b1633e51d431b
https://github.com/qemu/qemu/commit/e306fff7f83285a385c29927833b1633e51d431b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shtvala
shtvala is described in RVA22 as:
"htval must be written with the faulting guest physical address
in all circumstances permitted by the ISA."
This is the case since commit 3067553993, so claim support for shtvala.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 73afe5c2f930b0ca86f7e8a43d501aa1908924ed
https://github.com/qemu/qemu/commit/73afe5c2f930b0ca86f7e8a43d501aa1908924ed
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shvstvecd
shvstvecd is defined in RVA22 as:
"vstvec.MODE must be capable of holding the value 0 (Direct).
When vstvec.MODE=Direct, vstvec.BASE must be capable of holding any
valid four-byte-aligned address."
This is always true for TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c379e6f627c191a07ad3771a5974cefc2b12d1d1
https://github.com/qemu/qemu/commit/c379e6f627c191a07ad3771a5974cefc2b12d1d1
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shvsatpa
shvsatpa is defined in RVA22 as:
"All translation modes supported in satp must be supported in vsatp."
This is always true in TCG so let's claim support for it.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2fedb6b1835cc83a168a920dd39dbd3cd834c254
https://github.com/qemu/qemu/commit/2fedb6b1835cc83a168a920dd39dbd3cd834c254
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
target/riscv: add shgatpa
shgatpa is defined in RVA22 as:
"For each supported virtual memory scheme SvNN supported in satp, the
corresponding hgatp SvNNx4 mode must be supported. The hgatp mode Bare
must also be supported."
Claim support for shgatpa since this is always true for TCG.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f4df21e07f126eab24adf505cb33db0c94968cab
https://github.com/qemu/qemu/commit/f4df21e07f126eab24adf505cb33db0c94968cab
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv/tcg: add sha
'sha' is the augmented hypervisor extension, defined in RVA22 as a set of
the following extensions:
- RVH
- Ssstateen
- Shcounterenw (always present)
- Shvstvala (always present)
- Shtvala (always present)
- Shvstvecd (always present)
- Shvsatpa (always present)
- Shgatpa (always present)
We can claim support for 'sha' by checking if we have RVH and ssstateen.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e2dca2dc5abfba504d4ac9222673a9edbc1c1266
https://github.com/qemu/qemu/commit/e2dca2dc5abfba504d4ac9222673a9edbc1c1266
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/op_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: use RISCVException enum in exception helpers
Do a cosmetic change in riscv_raise_exception() to change 'exception'
type from uint32_t to RISCVException, making it a bit clear that the
arg is directly correlated to the RISCVException enum.
As a side effect, change 'excp' type from int to RISCVException in
generate_exception() to guarantee that all callers of
riscv_raise_exception() will use the enum.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 8f1a1289429b3bcb9709c0cfef2006d759e2936b
https://github.com/qemu/qemu/commit/8f1a1289429b3bcb9709c0cfef2006d759e2936b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/op_helper.c
M target/riscv/trace-events
Log Message:
-----------
target/riscv: add trace in riscv_raise_exception()
When using system mode we can get the CPU traps being taken via the
'riscv_trap' trace or the "-d int" qemu log. User mode does not a way of
logging/showing exceptions to users.
Add a trace in riscv_raise_exception() to allow qemu-riscv(32/64) users
to check all exceptions being thrown. This is particularly useful to
help identifying insns that are throwing SIGILLs.
As it is today we need to debug their binaries to identify where the
illegal insns are:
$ ~/work/qemu/build/qemu-riscv64 -cpu rv64 ./foo.out
Illegal instruction (core dumped)
After this change users can capture the trace and use EPC to pinpoint
the insn:
$ ~/work/qemu/build/qemu-riscv64 -cpu rv64 -trace riscv_exception ./foo.out
riscv_exception 8 (user_ecall) on epc 0x17cd2
riscv_exception 8 (user_ecall) on epc 0x17cda
riscv_exception 8 (user_ecall) on epc 0x17622
(...)
riscv_exception 2 (illegal_instruction) on epc 0x1053a
Illegal instruction (core dumped)
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 37089cb8ad3e0ffd552a68101e42697eb9dcd48a
https://github.com/qemu/qemu/commit/37089cb8ad3e0ffd552a68101e42697eb9dcd48a
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Remove obsolete pointer masking extension code.
Zjpm extension is finally ratified. And it's much simplier compared to the
experimental one.
The newer version doesn't allow to specify custom mask or base for pointer
masking.
Instead it allows only certain options for masking top bits.
Signed-off-by: Alexey Baturo <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 33ca99a111b4cb6af7f6f907ad685b04ff05892a
https://github.com/qemu/qemu/commit/33ca99a111b4cb6af7f6f907ad685b04ff05892a
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/csr.c
M target/riscv/pmp.c
M target/riscv/pmp.h
Log Message:
-----------
target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of
Zjpm v1.0
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3d1c5c08855de3a17fa91777260f4d1867f39bdf
https://github.com/qemu/qemu/commit/3d1c5c08855de3a17fa91777260f4d1867f39bdf
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Add helper functions to calculate current number of masked bits
for pointer masking
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6ec718e352c9694e2caed5977c847a5e9bbbe11e
https://github.com/qemu/qemu/commit/6ec718e352c9694e2caed5977c847a5e9bbbe11e
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add pointer masking tb flags
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4d501a7a7fb4a9a4ac17d031225bafe7f4f75583
https://github.com/qemu/qemu/commit/4d501a7a7fb4a9a4ac17d031225bafe7f4f75583
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Update address modify functions to take into account pointer
masking
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4d1600934a6c0fb617ffd4852fd54dfdd3eda35b
https://github.com/qemu/qemu/commit/4d1600934a6c0fb617ffd4852fd54dfdd3eda35b
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/internals.h
M target/riscv/op_helper.c
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Apply pointer masking for virtualized memory accesses
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e00e2749ce6194e2757a850e13dc4c337bf3e3d0
https://github.com/qemu/qemu/commit/e00e2749ce6194e2757a850e13dc4c337bf3e3d0
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Enable updates for pointer masking variables and thus enable
pointer masking extension
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 36de64b74cc56e95b082e2e26522a22ec75a7c8d
https://github.com/qemu/qemu/commit/36de64b74cc56e95b082e2e26522a22ec75a7c8d
Author: Tommy Wu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add 'ext_smrnmi' in the RISCVCPUConfig
The boolean variable 'ext_smrnmi' is used to determine whether the
Smrnmi extension exists.
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Tommy Wu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5db557f82bff480437275d4cc9e0b5463bc04484
https://github.com/qemu/qemu/commit/5db557f82bff480437275d4cc9e0b5463bc04484
Author: Tommy Wu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add Smrnmi CSRs
The Smrnmi extension adds the 'mnscratch', 'mnepc', 'mncause',
'mnstatus' CSRs.
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Tommy Wu <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c1149f69ab711bf6ccdc1da492f5be47f1ebf67e
https://github.com/qemu/qemu/commit/c1149f69ab711bf6ccdc1da492f5be47f1ebf67e
Author: Tommy Wu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/riscv/riscv_hart.c
M include/hw/riscv/riscv_hart.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Handle Smrnmi interrupt and exception
Because the RNMI interrupt trap handler address is implementation defined.
We add the 'rnmi-interrupt-vector' and 'rnmi-exception-vector' as the property
of the harts. It’s very easy for users to set the address based on their
expectation. This patch also adds the functionality to handle the RNMI signals.
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Tommy Wu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3157a553ec6b9a52ad0aa6b52cca27d3a964167e
https://github.com/qemu/qemu/commit/3157a553ec6b9a52ad0aa6b52cca27d3a964167e
Author: Tommy Wu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Add Smrnmi mnret instruction
This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only
instruction that uses the values in `mnepc` and `mnstatus` to return to the
program counter, privilege mode, and virtualization mode of the
interrupted context.
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Tommy Wu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f9653d4eb2ccaf6fe140e38fb1027a9e829d4062
https://github.com/qemu/qemu/commit/f9653d4eb2ccaf6fe140e38fb1027a9e829d4062
Author: Tommy Wu <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add Smrnmi cpu extension
This adds the properties for ISA extension Smrnmi.
Also, when Smrnmi is present, the firmware (e.g., OpenSBI) must set
mnstatus.NMIE to 1 before enabling any interrupts. Otherwise, all
interrupts will be disabled. Since our current OpenSBI does not
support Smrnmi yet, let's disable Smrnmi for the 'max' type CPU for
now. We can re-enable it once OpenSBI includes proper support for it.
Signed-off-by: Frank Chang <[email protected]>
Signed-off-by: Tommy Wu <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0266fd8b56a4de8180cda9b2064ed2e58d17b3d9
https://github.com/qemu/qemu/commit/0266fd8b56a4de8180cda9b2064ed2e58d17b3d9
Author: Frank Chang <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Add Zicfilp support for Smrnmi
Zicfilp extension introduces the MNPELP (bit 9) in mnstatus.
The MNPELP field holds the previous ELP.
When a RNMI trap is delivered, the MNPELP is set to ELP and ELP set
to NO_LP_EXPECTED. Upon a mnret, if the mnstatus.MNPP holds the
value y, then ELP is set to the value of MNPELP if yLPE is 1;
otherwise, it is set to NO_LP_EXPECTED.
Signed-off-by: Frank Chang <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 7703a1d1e6479084d58ee3106a3c8a72ed7357eb
https://github.com/qemu/qemu/commit/7703a1d1e6479084d58ee3106a3c8a72ed7357eb
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/riscv/virt.c
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
Log Message:
-----------
target/riscv: Have kvm_riscv_get_timebase_frequency() take RISCVCPU cpu
Keep kvm_riscv_get_timebase_frequency() prototype aligned with
the other ones declared in "kvm_riscv.h", have it take a RISCVCPU
cpu as argument. Include "target/riscv/cpu-qom.h" which declares
the RISCVCPU typedef.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cb938a0a24bc911894b6fec1429e2e0cc8b2f948
https://github.com/qemu/qemu/commit/cb938a0a24bc911894b6fec1429e2e0cc8b2f948
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt: Remove unnecessary use of &first_cpu
virt_machine_init() creates the HARTs vCPUs, then later
virt_machine_done() calls create_fdt_sockets(), so the
latter has access to the first vCPU via:
RISCVVirtState {
RISCVHartArrayState {
RISCVCPU *harts;
...
} soc[VIRT_SOCKETS_MAX];
...
} s;
Directly use that instead of the &first_cpu global.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 51c4f3e982daa1d2fffa63e0b73565c948d26d2b
https://github.com/qemu/qemu/commit/51c4f3e982daa1d2fffa63e0b73565c948d26d2b
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add properties for Indirect CSR Access extension
This adds the properties for sxcsrind. Definitions of new registers and
implementations will come with future patches.
Signed-off-by: Kaiwen Xue <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dc0280723dfc64d90e94155985853691d5ab9276
https://github.com/qemu/qemu/commit/dc0280723dfc64d90e94155985853691d5ab9276
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Decouple AIA processing from xiselect and xireg
Since xiselect and xireg also will be of use in sxcsrind, AIA should
have its own separated interface when those CSRs are accessed.
Signed-off-by: Kaiwen Xue <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dbcb6e1ccf3f25292a8700bb18997a4411fad82f
https://github.com/qemu/qemu/commit/dbcb6e1ccf3f25292a8700bb18997a4411fad82f
Author: Atish Patra <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Enable S*stateen bits for AIA
As per the ratified AIA spec v1.0, three stateen bits control AIA CSR
access.
Bit 60 controls the indirect CSRs
Bit 59 controls the most AIA CSR state
Bit 58 controls the IMSIC state such as stopei and vstopei
Enable the corresponding bits in [m|h]stateen and enable corresponding
checks in the CSR accessor functions.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 5e33a20827150345350bede07e26a1bae320e682
https://github.com/qemu/qemu/commit/5e33a20827150345350bede07e26a1bae320e682
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu_bits.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Support generic CSR indirect access
This adds the indirect access registers required by sscsrind/smcsrind
and the operations on them. Note that xiselect and xireg are used for
both AIA and sxcsrind, and the behavior of accessing them depends on
whether each extension is enabled and the value stored in xiselect.
Co-developed-by: Atish Patra <[email protected]>
Signed-off-by: Kaiwen Xue <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f2548886b3dff228b82e91808553616c4b8d14a8
https://github.com/qemu/qemu/commit/f2548886b3dff228b82e91808553616c4b8d14a8
Author: Atish Patra <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Add properties for counter delegation ISA extensions
This adds the properties for counter delegation ISA extensions
(Smcdeleg/Ssccfg). Definitions of new registers and and implementation
will come in the next set of patches.
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e84af935607e3df409cbf0854bc4f4a1b828ce76
https://github.com/qemu/qemu/commit/e84af935607e3df409cbf0854bc4f4a1b828ce76
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Add counter delegation definitions
This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.
Signed-off-by: Kaiwen Xue <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b6504cd0d1ddb766410a951dc9f5bb63059d8eb6
https://github.com/qemu/qemu/commit/b6504cd0d1ddb766410a951dc9f5bb63059d8eb6
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add select value range check for counter delegation
This adds checks in ops performed on xireg and xireg2-xireg6 so that the
counter delegation function will receive a valid xiselect value with the
proper extensions enabled.
Co-developed-by: Atish Patra <[email protected]>
Signed-off-by: Kaiwen Xue <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6247dc2ef70b512523d4495e8ea8349ccd6b0ef0
https://github.com/qemu/qemu/commit/6247dc2ef70b512523d4495e8ea8349ccd6b0ef0
Author: Kaiwen Xue <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add counter delegation/configuration support
The Smcdeleg/Ssccfg adds the support for counter delegation via
S*indcsr and Ssccfg.
It also adds a new shadow CSR scountinhibit and menvcfg enable bit (CDE)
to enable this extension and scountovf virtualization.
Signed-off-by: Kaiwen Xue <[email protected]>
Co-developed-by: Atish Patra <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 04ff272d588695a2a4c328347e767b24fa241408
https://github.com/qemu/qemu/commit/04ff272d588695a2a4c328347e767b24fa241408
Author: Atish Patra <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Invoke pmu init after feature enable
The dependant ISA features are enabled at the end of cpu_realize
in finalize_features. Thus, PMU init should be invoked after that
only. Move the init invocation to riscv_tcg_cpu_finalize_features.
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2a754d6957e70889e7208f4d2d6bdb9714508c9b
https://github.com/qemu/qemu/commit/2a754d6957e70889e7208f4d2d6bdb9714508c9b
Author: Atish Patra <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add implied rule for counter delegation extensions
The counter delegation/configuration extensions depend on the following
extensions.
1. Smcdeleg - To enable counter delegation from M to S
2. S[m|s]csrind - To enable indirect access CSRs
Add an implied rule so that these extensions are enabled by default
if the sscfg extension is enabled.
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: fdb7bce43f9008d83e1edfd260a8165119b61ca5
https://github.com/qemu/qemu/commit/fdb7bce43f9008d83e1edfd260a8165119b61ca5
Author: Atish Patra <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
Add configuration options so that they can be enabled/disabld from
qemu commandline.
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Atish Patra <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 507957eb2acfd321646c98bc853d6c8bafe628d2
https://github.com/qemu/qemu/commit/507957eb2acfd321646c98bc853d6c8bafe628d2
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix henvcfg potentially containing stale bits
With the current implementation, if we had the following scenario:
- Set bit x in menvcfg
- Set bit x in henvcfg
- Clear bit x in menvcfg
then, the internal variable env->henvcfg would still contain bit x due
to both a wrong menvcfg mask used in write_henvcfg() as well as a
missing update of henvcfg upon menvcfg update.
This can lead to some wrong interpretation of the context. In order to
update henvcfg upon menvcfg writing, call write_henvcfg() after writing
menvcfg. Clearing henvcfg upon writing the new value is also needed in
write_henvcfg() as well as clearing henvcfg upper part when writing it
with write_henvcfgh().
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0aadf8162a77a03c79e35e76e16b99cd18ef7916
https://github.com/qemu/qemu/commit/0aadf8162a77a03c79e35e76e16b99cd18ef7916
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add Ssdbltrp CSRs handling
Add ext_ssdbltrp in RISCVCPUConfig and implement MSTATUS.SDT,
{H|M}ENVCFG.DTE and modify the availability of MTVAL2 based on the
presence of the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 72d71d87327f47dc878683f4ff6a21472d5dcfdc
https://github.com/qemu/qemu/commit/72d71d87327f47dc878683f4ff6a21472d5dcfdc
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Implement Ssdbltrp sret, mret and mnret behavior
When the Ssdbltrp extension is enabled, SSTATUS.SDT field is cleared
when executing sret. When executing mret/mnret, SSTATUS.SDT is cleared
when returning to U, VS or VU and VSSTATUS.SDT is cleared when returning
to VU from HS.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 967760f62c7ca5ab6194131f4ff152b37f2d7017
https://github.com/qemu/qemu/commit/967760f62c7ca5ab6194131f4ff152b37f2d7017
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Implement Ssdbltrp exception handling
When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
while SSTATUS.SDT isn't cleared, generate a double trap exception to
M-mode.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b0edcbe755e88f969a5e201c093bad453ba4a13b
https://github.com/qemu/qemu/commit/b0edcbe755e88f969a5e201c093bad453ba4a13b
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv: Add Ssdbltrp ISA extension enable switch
Add the switch to enable the Ssdbltrp ISA extension.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d2e92f1c6d4441221e3ae07dd24613d479b310dc
https://github.com/qemu/qemu/commit/d2e92f1c6d4441221e3ae07dd24613d479b310dc
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Add Smdbltrp CSRs handling
Add `ext_smdbltrp`in RISCVCPUConfig and implement MSTATUS.MDT behavior.
Also set MDT to 1 at reset according to the specification.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f2efb6e793094425ca0b9ee6bafafd7e11eaa666
https://github.com/qemu/qemu/commit/f2efb6e793094425ca0b9ee6bafafd7e11eaa666
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Implement Smdbltrp sret, mret and mnret behavior
When the Ssdbltrp extension is enabled, SSTATUS.MDT field is cleared
when executing sret if executed in M-mode. When executing mret/mnret,
SSTATUS.MDT is cleared.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 00af7d53601b70f1353dabd1c87ffa260aafd27e
https://github.com/qemu/qemu/commit/00af7d53601b70f1353dabd1c87ffa260aafd27e
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: Implement Smdbltrp behavior
When the Smsdbltrp ISA extension is enabled, if a trap happens while
MSTATUS.MDT is already set, it will trigger an abort or an NMI is the
Smrnmi extension is available.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2d8e8259287ced7c689a7c7fad67ad2a417e477c
https://github.com/qemu/qemu/commit/2d8e8259287ced7c689a7c7fad67ad2a417e477c
Author: Clément Léger <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Add Smdbltrp ISA extension enable switch
Add the switch to enable the Smdbltrp ISA extension and disable it for
the max cpu. Indeed, OpenSBI when Smdbltrp is present, M-mode double
trap is enabled by default and MSTATUS.MDT needs to be cleared to avoid
taking a double trap. OpenSBI does not currently support it so disable
it for the max cpu to avoid breaking regression tests.
Signed-off-by: Clément Léger <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: fa622855eaaca8b543e19cf7ba8ab0304a1e4b84
https://github.com/qemu/qemu/commit/fa622855eaaca8b543e19cf7ba8ab0304a1e4b84
Author: Jason Chien <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache
This commit introduces a translation tag to avoid invalidating an entry
that should not be invalidated when IOMMU executes invalidation commands.
E.g. IOTINVAL.VMA with GV=0, AV=0, PSCV=1 invalidates both a mapping
of single stage translation and a mapping of nested translation with
the same PSCID, but only the former one should be invalidated.
Signed-off-by: Jason Chien <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 941f76e2930c2d57e22692e4163d8797529d0491
https://github.com/qemu/qemu/commit/941f76e2930c2d57e22692e4163d8797529d0491
Author: Alexey Baturo <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
Log Message:
-----------
target/riscv: Support Supm and Sspm as part of Zjpm v1.0
The Zjpm v1.0 spec states there should be Supm and Sspm extensions that
are used in profile specification. Enabling Supm extension enables both
Ssnpm and Smnpm, while Sspm enables only Smnpm.
Signed-off-by: Alexey Baturo <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f04cac4f8f254931f2af9d059b2175769e576afa
https://github.com/qemu/qemu/commit/f04cac4f8f254931f2af9d059b2175769e576afa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/char/riscv_htif.c
M hw/char/trace-events
Log Message:
-----------
hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d6430c17d7113d3c38480dc34e59d00b0504e2f7
https://github.com/qemu/qemu/commit/d6430c17d7113d3c38480dc34e59d00b0504e2f7
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-01-19 (Sun, 19 Jan 2025)
Changed paths:
M hw/char/riscv_htif.c
M hw/char/trace-events
M hw/riscv/riscv-iommu.c
M hw/riscv/riscv_hart.c
M hw/riscv/virt.c
M include/hw/riscv/riscv_hart.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_bits.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/gdbstub.c
M target/riscv/helper.h
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_privileged.c.inc
M target/riscv/internals.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/kvm/kvm_riscv.h
M target/riscv/machine.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/pmp.h
M target/riscv/tcg/tcg-cpu.c
M target/riscv/trace-events
M target/riscv/translate.c
M target/riscv/vector_helper.c
M tests/data/acpi/riscv64/virt/RHCT
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20250119-1' of
https://github.com/alistair23/qemu into staging
Second RISC-V PR for 10.0
* Reduce the overhead for simple RISC-V vector unit-stride loads and stores
* Add V bit to GDB priv reg
* Add 'sha' support
* Add traces for exceptions in user mode
* Update Pointer Masking to Zjpm v1.0
* Add Smrnmi support
* Fix timebase-frequency when using KVM acceleration
* Add RISC-V Counter delegation ISA extension support
* Add support for Smdbltrp and Ssdbltrp extensions
* Introduce a translation tag for the IOMMU page table cache
* Support Supm and Sspm as part of Zjpm v1.0
* Convert htif debug prints to trace event
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmeMUUwACgkQr3yVEwxT
# gBNgDQ/+JeqcsbJRX+PZQJEV06tDIJpk+mfaBHUYSGdNkjI9fzowNaxFIEB2vaLt
# 4+xAGMnJ4vMcjJyBcPOn1FKAlowM7MsUNITOF9Rstnyriqnj2UsUZ9YBtkuG6gWH
# ZHoYEKu7mAZoZw5RRx4TatHDXw7TYfUsrDPrn+x6yeCZTq9ruRTlHkzp2LC725Vq
# KTnbWAP7WlqiJaSxB5eIFYT5tYP1Blp0yD358B037C57EU9j5zm2FQdFmVK1+xRF
# dFg/urBIzfAjjkCS/t9DmH+S6NgMEut6udUhllk/KUJAzWvsggc4wZZlWjFOJFJY
# fIxx3alhY3pcm1PYjFpf15Poz6Pqva/KGjwgZafirKQtPbRSzfRkUwcHOYRTQT9j
# abeiB44XPaeIl8Jvw7GLxcWtlJ5NmBrZho+2Z9mIhB/Ix5H3PDgs18Oc/s73P2qQ
# JFLRb7cpYy1HbRc0ugvwAmOTY1t6HX8HAtT+3rNhiXpXnj4RW2C/WU1cEqrg8QkM
# cTPiy2zHoBhAWt9aDK1Kvbhb1vur3JaF7rk9jeKlriFr87Ly+yPU+8mnEDw40NMR
# Tc9nivqmOqqXS5AM9O/W1uzTWzpxIUy7XBy3cuSk0uZCoge4IE2Or7P2Rb2uyaNZ
# RkAo/PL2N1cMjP7gB3kLRtYY7FA+nal66KhfbHPRHqj+ZwUAxzs=
# =F3IG
# -----END PGP SIGNATURE-----
# gpg: Signature made Sat 18 Jan 2025 20:11:40 EST
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu:
(50 commits)
hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events
target/riscv: Support Supm and Sspm as part of Zjpm v1.0
hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache
target/riscv: Add Smdbltrp ISA extension enable switch
target/riscv: Implement Smdbltrp behavior
target/riscv: Implement Smdbltrp sret, mret and mnret behavior
target/riscv: Add Smdbltrp CSRs handling
target/riscv: Add Ssdbltrp ISA extension enable switch
target/riscv: Implement Ssdbltrp exception handling
target/riscv: Implement Ssdbltrp sret, mret and mnret behavior
target/riscv: Add Ssdbltrp CSRs handling
target/riscv: Fix henvcfg potentially containing stale bits
target/riscv: Add configuration for S[m|s]csrind, Smcdeleg/Ssccfg
target/riscv: Add implied rule for counter delegation extensions
target/riscv: Invoke pmu init after feature enable
target/riscv: Add counter delegation/configuration support
target/riscv: Add select value range check for counter delegation
target/riscv: Add counter delegation definitions
target/riscv: Add properties for counter delegation ISA extensions
target/riscv: Support generic CSR indirect access
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/20fac491cfee...d6430c17d711
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