Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: d0ad4118abb1434d6788d9ac5a1612103f88d360
https://github.com/qemu/qemu/commit/d0ad4118abb1434d6788d9ac5a1612103f88d360
Author: Helge Deller <[email protected]>
Date: 2025-01-24 (Fri, 24 Jan 2025)
Changed paths:
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Support up to 256 GiB RAM on 64-bit machines
Allow up to 256 GB RAM, which is the maximum a rp8440 machine (the very
last 64-bit PA-RISC machine) physically supports.
Signed-off-by: Helge Deller <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: c656f293dfe31661e4252d78cfa6cab6372ad5ca
https://github.com/qemu/qemu/commit/c656f293dfe31661e4252d78cfa6cab6372ad5ca
Author: Helge Deller <[email protected]>
Date: 2025-01-24 (Fri, 24 Jan 2025)
Changed paths:
M hw/hppa/machine.c
M target/hppa/cpu.h
Log Message:
-----------
hw/hppa: Fix booting Linux kernel with initrd
Commit 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()")
broke booting the Linux kernel with initrd which may have been provided
on the command line. The problem is, that the mentioned commit zeroes
out initial registers which were preset with addresses for the Linux
kernel and initrd.
Fix it by adding proper variables which are set shortly before starting
the firmware.
Signed-off-by: Helge Deller <[email protected]>
Fixes: 20f7b890173b ("hw/hppa: Reset vCPUs calling resettable_reset()")
Cc: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 8a139ae719616d85d835528a35f41eb23bfa54c7
https://github.com/qemu/qemu/commit/8a139ae719616d85d835528a35f41eb23bfa54c7
Author: Kenneth Jia <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: fix connect_serial_hds_to_uarts
In the loop, we need ignore the index increase when uart == uart_chosen
We should increase the index only after we allocate a serial.
Signed-off-by: Kenneth Jia <[email protected]>
Fixes: d2b3eaefb4d7 ("aspeed: Refactor UART init for multi-SoC machines")
Reviewed-by: Cédric Le Goater <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 134d9e5c0c4ae2fe64817a185730ec8b7835d573
https://github.com/qemu/qemu/commit/134d9e5c0c4ae2fe64817a185730ec8b7835d573
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/sd/sdhci.c
M include/hw/sd/sdhci.h
Log Message:
-----------
hw/sd/sdhci: Introduce a new Write Protected pin inverted property
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24). However, some boards are
design Write Protected pin active high. In other words, write enable the bit 19
should be 0 and write protected the bit 19 should be 1 at the
Present State Register (0x24). To support it, introduces a new "wp-inverted"
property and set it false by default.
Signed-off-by: Jamin Lin <[email protected]>
Acked-by: Cédric Le Goater <[email protected]>
Acked-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: bf8a471a38774800d77f58949bcaea4ca26390a7
https://github.com/qemu/qemu/commit/bf8a471a38774800d77f58949bcaea4ca26390a7
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/arm/aspeed.c
M include/hw/arm/aspeed.h
Log Message:
-----------
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
The Write Protect pin of SDHCI model is default active low to match the SDHCI
spec. So, write enable the bit 19 should be 1 and write protected the bit 19
should be 0 at the Present State Register (0x24).
According to the design of AST2600 EVB, the Write Protected pin is active
high by default. To support it, introduces a new "sdhci_wp_inverted"
property in ASPEED MACHINE State and set it true for AST2600 EVB
and set "wp_inverted" property true of sdhci-generic model.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Acked-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ef2385bb3797a594c85c14452d89a2d884d1df44
https://github.com/qemu/qemu/commit/ef2385bb3797a594c85c14452d89a2d884d1df44
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/timer/aspeed_timer.c
M hw/timer/trace-events
Log Message:
-----------
hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations
The register set have a significant change in AST2700. The TMC00-TMC3C
are used for TIMER0 and TMC40-TMC7C are used for TIMER1. In additional,
TMC20-TMC3C and TMC60-TMC7C are reserved registers for TIMER0 and TIMER1,
respectively.
Besides, each TIMER has their own control and interrupt status register.
In other words, users are able to set control and interrupt status for TIMER0
in one register. Both aspeed_timer_read and aspeed_timer_write callback
functions are not compatible AST2700.
Introduce common read and write functions for ASPEED timers.
Modify the aspeed_timer_read and aspeed_timer_write functions to delegate to
SoC-specific callbacks first.
Update the AST2400, AST2500, AST2600 and AST1030 specific read and write
functions to call the common implementations for common register accesses.
This refactoring improves the organization of call delegation and prepares the
codebase for future SoC-specific specializations, such as the AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8bc691bed881b37079405984334a59e0b6abba01
https://github.com/qemu/qemu/commit/8bc691bed881b37079405984334a59e0b6abba01
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/timer/aspeed_timer.c
M include/hw/timer/aspeed_timer.h
Log Message:
-----------
hw/timer/aspeed: Add AST2700 Support
The timer controller include 8 sets of 32-bit decrement counters, based on
either PCLK or 1MHZ clock and the design of timer controller between AST2600
and AST2700 are almost the same.
TIMER0 – TIMER7 has their own individual control and interrupt status register.
In other words, users are able to set timer control in register TMC10 with
different TIMER base address and clear timer control and interrupt status in
register TMC14 with different TIMER base address.
Introduce new "aspeed_2700_timer_read" and "aspeed_2700_timer_write" callback
functions and a new ast2700 class to support AST2700.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_0000
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3 = 0x12C1_00C0
Base Address of Timer 4 = 0x12C1_0100
Base Address of Timer 5 = 0x12C1_0140
Base Address of Timer 6 = 0x12C1_0180
Base Address of Timer 7 = 0x12C1_01C0
The register address space of each TIMER is "0x40" , and uses the following
formula to get the index and register of each TIMER.
timer_index = offset >> 6;
timer_offset = offset & 0x3f;
The TMC010 is a counter control set and interrupt status register. Write "1" to
TMC10[3:0] will set the specific bits to "1". Introduce a new
"aspeed_2700_timer_set_ctrl" function to handle this register behavior.
The TMC014 is a counter control clear and interrupt status register, to clear
the specific bits to "0", it should write "1" to TMC14[3:0] on the same bit
position. Introduce a new "aspeed_2700_timer_clear_ctrl" function to handle
this register behavior. TMC014 does not support read operation.
Signed-off-by: Jamin Lin <[email protected]>
Acked-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9cdca151f32eb9840aa5a1b3ba01a5b533d27686
https://github.com/qemu/qemu/commit/9cdca151f32eb9840aa5a1b3ba01a5b533d27686
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
aspeed/soc: Support Timer for AST2700
Add Timer model for AST2700 Timer support. The Timer controller include 8 sets
of 32-bit decrement counters.
The base address of TIMER0 to TIMER7 as following.
Base Address of Timer 0 = 0x12C1_0000
Base Address of Timer 1 = 0x12C1_0040
Base Address of Timer 2 = 0x12C1_0080
Base Address of Timer 3 = 0x12C1_00C0
Base Address of Timer 4 = 0x12C1_0100
Base Address of Timer 5 = 0x12C1_0140
Base Address of Timer 6 = 0x12C1_0180
Base Address of Timer 7 = 0x12C1_01C0
The interrupt of TIMER0 to TIMER7 as following.
GICINT16 = TIMER 0 interrupt
GICINT17 = TIMER 1 interrupt
GICINT18 = TIMER 2 interrupt
GICINT19 = TIMER 3 interrupt
GICINT20 = TIMER 4 interrupt
GICINT21 = TIMER 5 interrupt
GICINT22 = TIMER 6 interrupt
GICINT23 = TIMER 7 interrupt
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a03e1382598573eef351c48509ca7abd3ab610e1
https://github.com/qemu/qemu/commit/a03e1382598573eef351c48509ca7abd3ab610e1
Author: Cédric Le Goater <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M tests/functional/test_aarch64_aspeed.py
Log Message:
-----------
test/functional: Update the Aspeed aarch64 test
Bumped SDK version to v09.03. v09.04 is available but not yet
supported in QEMU.
Reviewed-by: Jamin Lin <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f7ae9612fb98d505a44ac24872f6b92e87687813
https://github.com/qemu/qemu/commit/f7ae9612fb98d505a44ac24872f6b92e87687813
Author: Cédric Le Goater <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M tests/functional/aspeed.py
M tests/functional/test_arm_aspeed_ast2500.py
M tests/functional/test_arm_aspeed_ast2600.py
Log Message:
-----------
test/functional: Update buildroot images to 2024.11
The main changes compared to upstream 2024.11 buildroot are
- bumped Linux to version 6.11.11 with a custom config
- changed U-Boot to OpenBMC branch for more support
- included extra target packages
See branch [1] for more details.
There is a slight output change when powering off the machine,
the console now contains :
reboot: Power off not available: System halted
Adjust accordingly the expect string in
do_test_arm_aspeed_buildroot_poweroff().
[1] https://github.com/legoater/buildroot/commits/aspeed-2024.11
Reviewed-by: Jamin Lin <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: e90858464ab90e0e6aaede7f3c9d4750232b9755
https://github.com/qemu/qemu/commit/e90858464ab90e0e6aaede7f3c9d4750232b9755
Author: Cédric Le Goater <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Create sd devices only when defaults are enabled
When the -nodefaults option is set, sd devices should not be
automatically created by the machine. Instead they should be defined
on the command line.
Note that it is not currently possible to define which bus an
"sd-card" device is attached to:
-blockdev node-name=drive0,driver=file,filename=/path/to/file.img \
-device sd-card,drive=drive0,id=sd0
and the first bus named "sd-bus" will be used.
Reviewed-by: Jamin Lin <[email protected]>
Acked-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 668f29e1713b879fa32af213cc2820ea589034d0
https://github.com/qemu/qemu/commit/668f29e1713b879fa32af213cc2820ea589034d0
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/watchdog/wdt_aspeed.c
Log Message:
-----------
aspeed/wdt: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a22acbb252fe308416aafae8069beaf039578f14
https://github.com/qemu/qemu/commit/a22acbb252fe308416aafae8069beaf039578f14
Author: Jamin Lin <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/watchdog/wdt_aspeed.c
Log Message:
-----------
aspeed/wdt: Support software reset mode for AST2600
On the AST2400 and AST2500 platforms, the system can only be reset by enabling
the WDT (Watchdog Timer) and waiting for the WDT timeout. However, starting
from the AST2600 platform, the reset event can be triggered directly and
intentionally by software, without relying on the WDT timeout.
This mechanism, referred to as "software restart", is implemented in hardware.
When using the software restart mechanism, the WDT counter is not enabled.
To trigger a reset generation in software mode, write 0xAEEDF123 to register
0x24 and software mode reset only support SOC reset mode.
A new function, "aspeed_wdt_is_soc_reset_mode", is introduced to determine
whether the SoC reset mode is active.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8b7ccc6ad10cd4a107b4627e9a5606d757607ff2
https://github.com/qemu/qemu/commit/8b7ccc6ad10cd4a107b4627e9a5606d757607ff2
Author: Thomas Huth <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs/system/arm/aspeed: Remove tacoma-bmc from the documentation
The tacoma-bmc machine has recently been removed, so let's remove
it from the documentation now, too.
Fixes: 2b1b66e01f ("arm: Remove tacoma-bmc machine")
Signed-off-by: Thomas Huth <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b5afd8c023a9b2daddcec06917b0ff478eda4783
https://github.com/qemu/qemu/commit/b5afd8c023a9b2daddcec06917b0ff478eda4783
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M hw/hppa/hppa_hardware.h
M hw/hppa/machine.c
M target/hppa/cpu.h
Log Message:
-----------
Merge tag 'hppa-system-for-v10-pull-request' of
https://github.com/hdeller/qemu-hppa into staging
hppa updates
* Fixes booting a Linux kernel which is provided on the command line.
* Allow more than 4GB RAM on 64-bit boxes
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# gpg: Signature made Fri 24 Jan 2025 14:53:34 EST
# gpg: using EDDSA key BCE9123E1AD29F07C049BBDEF712B510A23A0F5F
# gpg: Good signature from "Helge Deller <[email protected]>" [unknown]
# gpg: aka "Helge Deller <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
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* tag 'hppa-system-for-v10-pull-request' of
https://github.com/hdeller/qemu-hppa:
hw/hppa: Fix booting Linux kernel with initrd
hw/hppa: Support up to 256 GiB RAM on 64-bit machines
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 7faf9d2f12ace4c1d04cf1a2b39334eef9a45f22
https://github.com/qemu/qemu/commit/7faf9d2f12ace4c1d04cf1a2b39334eef9a45f22
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-01-27 (Mon, 27 Jan 2025)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/aspeed.c
M hw/arm/aspeed_ast27x0.c
M hw/sd/sdhci.c
M hw/timer/aspeed_timer.c
M hw/timer/trace-events
M hw/watchdog/wdt_aspeed.c
M include/hw/arm/aspeed.h
M include/hw/sd/sdhci.h
M include/hw/timer/aspeed_timer.h
M tests/functional/aspeed.py
M tests/functional/test_aarch64_aspeed.py
M tests/functional/test_arm_aspeed_ast2500.py
M tests/functional/test_arm_aspeed_ast2600.py
Log Message:
-----------
Merge tag 'pull-aspeed-20250127' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Fixed serial definitions on the command line
* Fixed sdhci write protected pin on AST2600 EVB machine
* Added timer support on AST2700 SoC
* Updated buildroot and SDK images of functional tests
* Removed sd devices creation when -nodefaults is used
* Added software reset mode support on AST2600 SoC
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# gpg: Signature made Mon 27 Jan 2025 03:49:16 EST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250127' of https://github.com/legoater/qemu:
docs/system/arm/aspeed: Remove tacoma-bmc from the documentation
aspeed/wdt: Support software reset mode for AST2600
aspeed/wdt: Fix coding style
aspeed: Create sd devices only when defaults are enabled
test/functional: Update buildroot images to 2024.11
test/functional: Update the Aspeed aarch64 test
aspeed/soc: Support Timer for AST2700
hw/timer/aspeed: Add AST2700 Support
hw/timer/aspeed: Refactor Timer Callbacks for SoC-Specific Implementations
hw/arm/aspeed: Invert sdhci write protected pin for AST2600 EVB
hw/sd/sdhci: Introduce a new Write Protected pin inverted property
hw/arm/aspeed: fix connect_serial_hds_to_uarts
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/ed734377ab3f...7faf9d2f12ac
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