Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f0c29a02343d733154a64271124609cb5f117797
https://github.com/qemu/qemu/commit/f0c29a02343d733154a64271124609cb5f117797
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/alpha/fpu_helper.c
Log Message:
-----------
target/alpha: Don't corrupt error_code with unknown softfloat flags
In do_cvttq() we set env->error_code with what is supposed to be a
set of FPCR exception bit values. However, if the set of float
exception flags we get back from softfloat for the conversion
includes a flag which is not one of the three we expect here
(invalid_cvti, invalid, inexact) then we will fall through the
if-ladder and set env->error_code to the unconverted softfloat
exception_flag value. This will then cause us to take a spurious
exception.
This is harmless now, but when we add new floating point exception
flags to softfloat it will cause problems. Add an else clause to the
if-ladder to make it ignore any float exception flags it doesn't care
about.
Specifically, without this fix, 'make check-tcg' will fail for Alpha
when the commit adding float_flag_input_denormal_used lands.
Fixes: aa3bad5b59e7 ("target/alpha: Use float64_to_int64_modulo for CVTTQ")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 6e7998ceb9008e82501c7cf069e5552c7e352c6c
https://github.com/qemu/qemu/commit/6e7998ceb9008e82501c7cf069e5552c7e352c6c
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/igd.c
Log Message:
-----------
vfio/igd: Fix potential overflow in igd_gtt_memory_size()
The risk is mainly theoretical since the applied bit mask will keep
the 'ggms' shift value below 3. Nevertheless, let's use a 64 bit
integer type and resolve the coverity issue.
Resolves: Coverity CID 1585908
Fixes: 1e1eac5f3dcd ("vfio/igd: canonicalize memory size calculations")
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: dee69a8ca6ebc325939dc0b6800becdb26cd9dbf
https://github.com/qemu/qemu/commit/dee69a8ca6ebc325939dc0b6800becdb26cd9dbf
Author: Tomita Moeko <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/pci-quirks.c
A hw/vfio/pci-quirks.h
Log Message:
-----------
vfio/pci: declare generic quirks in a new header file
Declare generic vfio_generic_{window_address,window_data,mirror}_quirk
in newly created pci_quirks.h so that they can be used elsewhere, like
igd.c.
Signed-off-by: Tomita Moeko <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f36e7ba9750cbeffdc465c2d195a232d7cb67555
https://github.com/qemu/qemu/commit/f36e7ba9750cbeffdc465c2d195a232d7cb67555
Author: Tomita Moeko <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/pci-quirks.c
M hw/vfio/pci-quirks.h
Log Message:
-----------
vfio/pci: introduce config_offset field in VFIOConfigMirrorQuirk
Device may only expose a specific portion of PCI config space through a
region in a BAR, such behavior is seen in igd GGC and BDSM mirrors in
BAR0. To handle these, config_offset is introduced to allow mirroring
arbitrary region in PCI config space.
Signed-off-by: Tomita Moeko <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: e45891e0b17884b7170c441eab3a5cdd856946f7
https://github.com/qemu/qemu/commit/e45891e0b17884b7170c441eab3a5cdd856946f7
Author: Tomita Moeko <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/igd.c
Log Message:
-----------
vfio/igd: use VFIOConfigMirrorQuirk for mirrored registers
With the introduction of config_offset field, VFIOConfigMirrorQuirk can
now be used for those mirrored register in igd bar0. This eliminates
the need for the macro intoduced in 1a2623b5c9e7 ("vfio/igd: add macro
for declaring mirrored registers").
Signed-off-by: Tomita Moeko <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 7b3d5b84cbd742356a1afc6b0fa489d0663f235d
https://github.com/qemu/qemu/commit/7b3d5b84cbd742356a1afc6b0fa489d0663f235d
Author: Zhenzhong Duan <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/iommufd.c
Log Message:
-----------
vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()
When iommufd_cdev_ram_block_discard_disable() fails for whatever reason,
errp should be set or else SIGSEV is triggered in vfio_realize() when
error_prepend() is called.
By this chance, use the same error message for both legacy and iommufd
backend.
Fixes: 5ee3dc7af785 ("vfio/iommufd: Implement the iommufd backend")
Signed-off-by: Zhenzhong Duan <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 96b339cc4cc7e3d2da0e615e1851d3250b526ea5
https://github.com/qemu/qemu/commit/96b339cc4cc7e3d2da0e615e1851d3250b526ea5
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M include/qapi/error.h
M util/error.c
Log Message:
-----------
util/error: Introduce warn_report_err_once()
Depending on the configuration of the host and VM, a passthrough
device may generate recurring DMA mapping errors at runtime. In such
cases, reporting the issue once is sufficient.
We have already the warn/error_report_once() routines taking a format
and arguments. Using the same design pattern, add a new warning
variant taking an 'Error *' parameter.
Cc: Markus Armbruster <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Reviewed-by: Markus Armbruster <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cbfbedd6173cf8ff3f374ec6b8e1a17e9fa75872
https://github.com/qemu/qemu/commit/cbfbedd6173cf8ff3f374ec6b8e1a17e9fa75872
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/pci.c
Log Message:
-----------
vfio/pci: Replace "iommu_device" by "vIOMMU"
This is to be consistent with other reported errors related to vIOMMU
devices.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cdc6f2e0c9fcef2027f4fc5f25ddd15e36283e90
https://github.com/qemu/qemu/commit/cdc6f2e0c9fcef2027f4fc5f25ddd15e36283e90
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio: Rephrase comment in vfio_listener_region_add() error path
Rephrase a bit the ending comment about how errors are handled
depending on the phase in which vfio_listener_region_add() is called.
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 80936cf7f38e55f41bf5b482ee04f055c76a0df0
https://github.com/qemu/qemu/commit/80936cf7f38e55f41bf5b482ee04f055c76a0df0
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/helpers.c
M include/hw/vfio/vfio-common.h
Log Message:
-----------
vfio: Introduce vfio_get_vfio_device()
This helper will be useful in the listener handlers to extract the
VFIO device from a memory region using memory_region_owner(). At the
moment, we only care for PCI passthrough devices. If the need arises,
we will add more.
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: aaec00422ba6538ca3e6bfa612bbae155ec15c84
https://github.com/qemu/qemu/commit/aaec00422ba6538ca3e6bfa612bbae155ec15c84
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio: Improve error reporting when MMIO region mapping fails
When the IOMMU address space width is smaller than the physical
address width, a MMIO region of a device can fail to map because the
region is outside the supported IOVA ranges of the VM. In this case,
PCI peer-to-peer transactions on BARs are not supported. This can
occur with the 39-bit IOMMU address space width, as can be the case on
some Intel consumer processors, or when using a vIOMMU device with
default settings.
The current error message is unclear, improve it and also change the
error report to a warning because it is a non fatal condition for the
VM. To prevent excessive log messages, restrict these recurring DMA
mapping errors to a single warning at runtime.
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 889695f8f3c10647cc27a3788b4a3f1d0192926c
https://github.com/qemu/qemu/commit/889695f8f3c10647cc27a3788b4a3f1d0192926c
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M backends/iommufd.c
M hw/vfio/container.c
Log Message:
-----------
vfio: Remove reports of DMA mapping errors in backends
Currently, the mapping handlers of the IOMMU backends, VFIO IOMMU Type
1 aka. legacy and IOMMUFD, return an errno and also report an error.
This can lead to excessive log messages at runtime for recurring DMA
mapping errors. Since these errors are already reported by the callers
in the vfio_container_dma_un/map() routines, simply remove them and
allow the callers to handle the reporting.
The mapping handler of the IOMMUFD backend has a comment suggesting
MMIO region mapping failures return EFAULT. I am not sure this is
entirely true, so keep the EFAULT case until the conditions are
clarified.
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: be7d8579eb5758c0edf81eb068017a56471a77e0
https://github.com/qemu/qemu/commit/be7d8579eb5758c0edf81eb068017a56471a77e0
Author: Cédric Le Goater <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M hw/vfio/common.c
Log Message:
-----------
vfio: Remove superfluous error report in vfio_listener_region_add()
For pseries machines, commit 567b5b309abe ("vfio/pci: Relax DMA map
errors for MMIO regions") introduced 2 error reports to notify the
user of MMIO mapping errors. Consolidate both code paths under one.
Cc: Harsh Prateek Bora <[email protected]>
Cc: Shivaprasad G Bhat <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Reviewed-by: Alex Williamson <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 7ad6a567570ed8cd829c4f05a006e2ba2c86fa4a
https://github.com/qemu/qemu/commit/7ad6a567570ed8cd829c4f05a006e2ba2c86fa4a
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
Log Message:
-----------
fpu: Add float_class_denormal
Currently in softfloat we canonicalize input denormals and so the
code that implements floating point operations does not need to care
whether the input value was originally normal or denormal. However,
both x86 and Arm FEAT_AFP require that an exception flag is set if:
* an input is denormal
* that input is not squashed to zero
* that input is actually used in the calculation (e.g. we
did not find the other input was a NaN)
So we need to track that the input was a non-squashed denormal. To
do this we add a new value to the FloatClass enum. In this commit we
add the value and adjust the code everywhere that looks at FloatClass
values so that the new float_class_denormal behaves identically to
float_class_normal. We will add the code that does the "raise a new
float exception flag if an input was an unsquashed denormal and we
used it" in a subsequent commit.
There should be no behavioural change in this commit.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 029a2083a293f55b7b3d56e16b1546c882d9299c
https://github.com/qemu/qemu/commit/029a2083a293f55b7b3d56e16b1546c882d9299c
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
Log Message:
-----------
fpu: Implement float_flag_input_denormal_used
For the x86 and the Arm FEAT_AFP semantics, we need to be able to
tell the target code that the FPU operation has used an input
denormal. Implement this; when it happens we set the new
float_flag_denormal_input_used.
Note that we only set this when an input denormal is actually used by
the operation: if the operation results in Invalid Operation or
Divide By Zero or the result is a NaN because some other input was a
NaN then we never needed to look at the input denormal and do not set
denormal_input_used.
We mostly do not need to adjust the hardfloat codepaths to deal with
this flag, because almost all hardfloat operations are already gated
on the input not being a denormal, and will fall back to softfloat
for a denormal input. The only exception is the comparison
operations, where we need to add the check for input denormals, which
must now fall back to softfloat where they did not before.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 28f13bccbe6a100f53519d1f32cbb78e407e2b83
https://github.com/qemu/qemu/commit/28f13bccbe6a100f53519d1f32cbb78e407e2b83
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M fpu/softfloat-parts.c.inc
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/hppa/fpu_helper.c
M target/i386/tcg/fpu_helper.c
M target/mips/fpu_helper.h
M target/mips/msa.c
M target/ppc/cpu_init.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/tricore/helper.c
M tests/fp/fp-bench.c
Log Message:
-----------
fpu: allow flushing of output denormals to be after rounding
Currently we handle flushing of output denormals in uncanon_normal
always before we deal with rounding. This works for architectures
that detect tininess before rounding, but is usually not the right
place when the architecture detects tininess after rounding. For
example, for x86 the SDM states that the MXCSR FTZ control bit causes
outputs to be flushed to zero "when it detects a floating-point
underflow condition". This means that we mustn't flush to zero if
the input is such that after rounding it is no longer tiny.
At least one of our guest architectures does underflow detection
after rounding but flushing of denormals before rounding (MIPS MSA);
this means we need to have a config knob for this that is separate
from our existing tininess_before_rounding setting.
Add an ftz_detection flag. For consistency with
tininess_before_rounding, we make it default to "detect ftz after
rounding"; this means that we need to explicitly set the flag to
"detect ftz before rounding" on every existing architecture that sets
flush_to_zero, so that this commit has no behaviour change.
(This means more code change here but for the long term a less
confusing API.)
For several architectures the current behaviour is either
definitely or possibly wrong; annotate those with TODO comments.
These architectures are definitely wrong (and should detect
ftz after rounding):
* x86
* Alpha
For these architectures the spec is unclear:
* MIPS (for non-MSA)
* RX
* SH4
PA-RISC makes ftz detection IMPDEF, but we aren't setting the
"tininess before rounding" setting that we ought to.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 7ea2b119f939ec408cc3fc28cb190343d28af427
https://github.com/qemu/qemu/commit/7ea2b119f939ec408cc3fc28cb190343d28af427
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Define FPCR AH, FIZ, NEP bits
The Armv8.7 FEAT_AFP feature defines three new control bits in
the FPCR:
* FPCR.AH: "alternate floating point mode"; this changes floating
point behaviour in a variety of ways, including:
- the sign of a default NaN is 1, not 0
- if FPCR.FZ is also 1, denormals detected after rounding
with an unbounded exponent has been applied are flushed to zero
- FPCR.FZ does not cause denormalized inputs to be flushed to zero
- miscellaneous other corner-case behaviour changes
* FPCR.FIZ: flush denormalized numbers to zero on input for
most instructions
* FPCR.NEP: makes scalar SIMD operations merge the result with
higher vector elements in one of the source registers, instead
of zeroing the higher elements of the destination
This commit defines the new bits in the FPCR, and allows them to be
read or written when FEAT_AFP is implemented. Actual behaviour
changes will be implemented in subsequent commits.
Note that these are the first FPCR bits which don't appear in the
AArch32 FPSCR view of the register, and which share bit positions
with FPSR bits.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: c2e60204779616daf35ade1bc5ef31f1388e9892
https://github.com/qemu/qemu/commit/c2e60204779616daf35ade1bc5ef31f1388e9892
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Implement FPCR.FIZ handling
Part of FEAT_AFP is the new control bit FPCR.FIZ. This bit affects
flushing of single and double precision denormal inputs to zero for
AArch64 floating point instructions. (For half-precision, the
existing FPCR.FZ16 control remains the only one.)
FPCR.FIZ differs from FPCR.FZ in that if we flush an input denormal
only because of FPCR.FIZ then we should *not* set the cumulative
exception bit FPSR.IDC.
FEAT_AFP also defines that in AArch64 the existing FPCR.FZ only
applies when FPCR.AH is 0.
We can implement this by setting the "flush inputs to zero" state
appropriately when FPCR is written, and by not reflecting the
float_flag_input_denormal status flag into FPSR reads when it is the
result only of FPSR.FIZ.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b3d00d0a448b6ea5750da1a163aeead0287f6c05
https://github.com/qemu/qemu/commit/b3d00d0a448b6ea5750da1a163aeead0287f6c05
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/internals.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Adjust FP behaviour for FPCR.AH = 1
When FPCR.AH is set, various behaviours of AArch64 floating point
operations which are controlled by softfloat config settings change:
* tininess and ftz detection before/after rounding
* NaN propagation order
* result of 0 * Inf + NaN
* default NaN value
When the guest changes the value of the AH bit, switch these config
settings on the fp_status_a64 and fp_status_f16_a64 float_status
fields.
This requires us to make the arm_set_default_fp_behaviours() function
global, since we now need to call it from cpu.c and vfp_helper.c; we
move it to vfp_helper.c so it can be next to the new
arm_set_ah_fp_behaviours().
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: a4550b7be90ccbda06b58b2c965bc87d697ec130
https://github.com/qemu/qemu/commit/a4550b7be90ccbda06b58b2c965bc87d697ec130
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Adjust exception flag handling for AH = 1
When FPCR.AH = 1, some of the cumulative exception flags in the FPSR
behave slightly differently for A64 operations:
* IDC is set when a denormal input is used without flushing
* IXC (Inexact) is set when an output denormal is flushed to zero
Update vfp_get_fpsr_from_host() to do this.
Note that because half-precision operations never set IDC, we now
need to add float_flag_input_denormal_used to the set we mask out of
fp_status_f16_a64.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 731528d35e681eb7e70207f58b8dcce419c8d567
https://github.com/qemu/qemu/commit/731528d35e681eb7e70207f58b8dcce419c8d567
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Add FPCR.AH to tbflags
We are going to need to generate different code in some cases when
FPCR.AH is 1. For example:
* Floating point neg and abs must not flip the sign bit of NaNs
* some insns (FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, and various
BFCVT and BFM bfloat16 ops) need to use a different float_status
to the usual one
Encode FPCR.AH into the A64 tbflags, so we can refer to it at
translate time.
Because we now have a bit in FPCR that affects codegen, we can't mark
the AArch64 FPCR register as being SUPPRESS_TB_END any more; writes
to it will now end the TB and trigger a regeneration of hflags.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 1828053990e3666a51ec08b6e23d1d70a82a68f9
https://github.com/qemu/qemu/commit/1828053990e3666a51ec08b6e23d1d70a82a68f9
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/internals.h
M target/arm/tcg/translate.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Set up float_status to use for FPCR.AH=1 behaviour
When FPCR.AH is 1, the behaviour of some instructions changes:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2, BFMLALB, BFMLALT
* SVE BFCVT, BFCVTNT, BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
* SME BFCVT, BFCVTN, BFMLAL, BFMLSL (these are all in SME2 which
QEMU does not yet implement)
* FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS
The behaviour change is:
* the instructions do not update the FPSR cumulative exception flags
* trapped floating point exceptions are disabled (a no-op for QEMU,
which doesn't implement FPCR.{IDE,IXE,UFE,OFE,DZE,IOE})
* rounding is always round-to-nearest-even regardless of FPCR.RMode
* denormalized inputs and outputs are always flushed to zero, as if
FPCR.{FZ,FIZ} is {1,1}
* FPCR.FZ16 is still honoured for half-precision inputs
(See the Arm ARM DDI0487L.a section A1.5.9.)
We can provide all these behaviours with another pair of float_status fields
which we use only for these insns, when FPCR.AH is 1. These float_status
fields will always have:
* flush_to_zero and flush_inputs_to_zero set for the non-F16 field
* rounding mode set to round-to-nearest-even
and so the only FPCR fields they need to honour are DN and FZ16.
In this commit we only define the new fp_status fields and give them
the required behaviour when FPSR is updated. In subsequent commits
we will arrange to use this new fp_status field for the instructions
that should be affected by FPCR.AH in this way.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: a8559e0e5306c7faa76de8e571d1edf92f436df3
https://github.com/qemu/qemu/commit/a8559e0e5306c7faa76de8e571d1edf92f436df3
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Use FPST_FPCR_AH for FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS
For the instructions FRECPE, FRECPS, FRECPX, FRSQRTE, FRSQRTS, use
FPST_FPCR_AH or FPST_FPCR_AH_F16 when FPCR.AH is 1, so that they get
the required behaviour changes.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b6295046e6b4bc5cb070df702ddb10e3672ac6ff
https://github.com/qemu/qemu/commit/b6295046e6b4bc5cb070df702ddb10e3672ac6ff
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Use FPST_FPCR_AH for BFCVT* insns
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFCVT, BFCVTN, BFCVTN2
* SVE BFCVT, BFCVTNT
so that they get the required behaviour changes.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 8a5a2b943e6a96487d5cf000b39aff8a4faf0821
https://github.com/qemu/qemu/commit/8a5a2b943e6a96487d5cf000b39aff8a4faf0821
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Use FPST_FPCR_AH for BFMLAL*, BFMLSL* insns
When FPCR.AH is 1, use FPST_FPCR_AH for:
* AdvSIMD BFMLALB, BFMLALT
* SVE BFMLALB, BFMLALT, BFMLSLB, BFMLSLT
so that they get the required behaviour changes.
We do this by making gen_gvec_op4_fpst() take an ARMFPStatusFlavour
rather than a bool is_fp16; existing callsites now select
FPST_FPCR_F16_A64 vs FPST_FPCR_A64 themselves rather than passing in
the boolean.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 7025fa996f57f3f767a1e7fe150df21da198118b
https://github.com/qemu/qemu/commit/7025fa996f57f3f767a1e7fe150df21da198118b
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Add FPCR.NEP to TBFLAGS
For FEAT_AFP, we want to emit different code when FPCR.NEP is set, so
that instead of zeroing the high elements of a vector register when
we write the output of a scalar operation to it, we instead merge in
those elements from one of the source registers. Since this affects
the generated code, we need to put FPCR.NEP into the TBFLAGS.
FPCR.NEP is treated as 0 when in streaming SVE mode and FEAT_SME_FA64
is not implemented or not enabled; we can implement this logic in
rebuild_hflags_a64().
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 78dcfe20e92a928375ff18c13b868ce2778c571c
https://github.com/qemu/qemu/commit/78dcfe20e92a928375ff18c13b868ce2778c571c
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Define and use new write_fp_*reg_merging() functions
For FEAT_AFP's FPCR.NEP bit, we need to programmatically change the
behaviour of the writeback of the result for most SIMD scalar
operations, so that instead of zeroing the upper part of the result
register it merges the upper elements from one of the input
registers.
Provide new functions write_fp_*reg_merging() which can be used
instead of the existing write_fp_*reg() functions when we want this
"merge the result with one of the input registers if FPCR.NEP is
enabled" handling, and use them in do_fp3_scalar_with_fpsttype().
Note that (as documented in the description of the FPCR.NEP bit)
which input register to use as the merge source varies by
instruction: for these 2-input scalar operations, the comparison
instructions take from Rm, not Rn.
We'll extend this to also provide the merging behaviour for
the remaining scalar insns in subsequent commits.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 0378199dc2fdf90550f9a819701b0c1709b34eab
https://github.com/qemu/qemu/commit/0378199dc2fdf90550f9a819701b0c1709b34eab
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for 3-input scalar operations
Handle FPCR.NEP for the 3-input scalar operations which use
do_fmla_scalar_idx() and do_fmadd(), by making them call the
appropriate write_fp_*reg_merging() functions.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 053b39aad9a94784d5f1926e50ec7199978525a8
https://github.com/qemu/qemu/commit/053b39aad9a94784d5f1926e50ec7199978525a8
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for BFCVT scalar
Currently we implement BFCVT scalar via do_fp1_scalar(). This works
even though BFCVT is a narrowing operation from 32 to 16 bits,
because we can use write_fp_sreg() for float16. However, FPCR.NEP
support requires that we use write_fp_hreg_merging() for float16
outputs, so we can't continue to borrow the non-narrowing
do_fp1_scalar() function for this. Split out trans_BFCVT_s()
into its own implementation that honours FPCR.NEP.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 3f88032ce23db57e64efb6ce24b760b201106a87
https://github.com/qemu/qemu/commit/3f88032ce23db57e64efb6ce24b760b201106a87
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for 1-input scalar operations
Handle FPCR.NEP for the 1-input scalar operations.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 13ab4eb19088f78851c69faaa8b5c6f3a3821150
https://github.com/qemu/qemu/commit/13ab4eb19088f78851c69faaa8b5c6f3a3821150
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP in do_cvtf_scalar()
Handle FPCR.NEP in the operations handled by do_cvtf_scalar().
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 64339259a9c2c5d504ea5179fc42091e3e4a7b22
https://github.com/qemu/qemu/commit/64339259a9c2c5d504ea5179fc42091e3e4a7b22
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for scalar FABS and FNEG
Handle FPCR.NEP merging for scalar FABS and FNEG; this requires
an extra parameter to do_fp1_scalar_int(), since FMOV scalar
does not have the merging behaviour.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 555639065d5b5310e8e67af383539309784d37dd
https://github.com/qemu/qemu/commit/555639065d5b5310e8e67af383539309784d37dd
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for FCVTXN (scalar)
Unlike the other users of do_2misc_narrow_scalar(), FCVTXN (scalar)
is always double-to-single and must honour FPCR.NEP. Implement this
directly in a trans function rather than using
do_2misc_narrow_scalar().
We still need gen_fcvtxn_sd() and the f_scalar_fcvtxn[] array for
the FCVTXN (vector) insn, so we move those down in the file to
where they are used.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 7bcde0c6dd9e7d150fb530b85f9218270db98638
https://github.com/qemu/qemu/commit/7bcde0c6dd9e7d150fb530b85f9218270db98638
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Handle FPCR.NEP for NEP for FMUL, FMULX scalar by element
do_fp3_scalar_idx() is used only for the FMUL and FMULX scalar by
element instructions; these both need to merge the result with the Rn
register when FPCR.NEP is set.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 2a734f3fe3cf528f3cf2f69600e88797b937201a
https://github.com/qemu/qemu/commit/2a734f3fe3cf528f3cf2f69600e88797b937201a
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for scalar FMIN/FMAX
When FPCR.AH == 1, floating point FMIN and FMAX have some odd special
cases:
* comparing two zeroes (even of different sign) or comparing a NaN
with anything always returns the second argument (possibly
squashed to zero)
* denormal outputs are not squashed to zero regardless of FZ or FZ16
Implement these semantics in new helper functions and select them at
translate time if FPCR.AH is 1 for the scalar FMAX and FMIN insns.
(We will convert the other FMAX and FMIN insns in subsequent
commits.)
Note that FMINNM and FMAXNM are not affected.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: d613e44010658ced19ac9add6a9587bef1d63c67
https://github.com/qemu/qemu/commit/d613e44010658ced19ac9add6a9587bef1d63c67
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for vector FMIN/FMAX
Implement the FPCR.AH == 1 semantics for vector FMIN/FMAX, by
creating new _ah_ versions of the gvec helpers which invoke the
scalar fmin_ah and fmax_ah helpers on each element.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: bb9330b662c62c5e84620f7028859c9b178642d6
https://github.com/qemu/qemu/commit/bb9330b662c62c5e84620f7028859c9b178642d6
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for FMAXV and FMINV
Implement the FPCR.AH semantics for FMAXV and FMINV. These are the
"recursively reduce all lanes of a vector to a scalar result" insns;
we just need to use the _ah_ helper for the reduction step when
FPCR.AH == 1.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 384433e709836209ae34bedda8a2a57992be8e18
https://github.com/qemu/qemu/commit/384433e709836209ae34bedda8a2a57992be8e18
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for FMINP and FMAXP
Implement the FPCR.AH semantics for the pairwise floating
point minimum/maximum insns FMINP and FMAXP.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: dac3a42f39ef1fae52b5b7b15662f3277f9ce7f2
https://github.com/qemu/qemu/commit/dac3a42f39ef1fae52b5b7b15662f3277f9ce7f2
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for SVE FMAXV and FMINV
Implement the FPCR.AH semantics for the SVE FMAXV and FMINV
vector-reduction-to-scalar max/min operations.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: bf92725bb26e6bce2b2267f384d8070595c46daa
https://github.com/qemu/qemu/commit/bf92725bb26e6bce2b2267f384d8070595c46daa
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX immediate
Implement the FPCR.AH semantics for the SVE FMAX and FMIN operations
that take an immediate as the second operand.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 4ba5383bc50d8ef18aed0d6aaa203c331dc0abf5
https://github.com/qemu/qemu/commit/4ba5383bc50d8ef18aed0d6aaa203c331dc0abf5
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Implement FPCR.AH semantics for SVE FMIN/FMAX vector
Implement the FPCR.AH semantics for the SVE FMAX and FMIN
operations that take two vector operands.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: e76df44d2dd06018016f35aff41258ce356d6e40
https://github.com/qemu/qemu/commit/e76df44d2dd06018016f35aff41258ce356d6e40
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement FPCR.AH handling of negation of NaN
FPCR.AH == 1 mandates that negation of a NaN value should not flip
its sign bit. This means we can no longer use gen_vfp_neg*()
everywhere but must instead generate slightly more complex code when
FPCR.AH is set.
Make this change for the scalar FNEG and for those places in
translate-a64.c which were previously directly calling
gen_vfp_neg*().
This change in semantics also affects any other instruction whose
pseudocode calls FPNeg(); in following commits we extend this
change to the other affected instructions.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: d091ce2d3f5bad6df30c686558807bcffb0c5a96
https://github.com/qemu/qemu/commit/d091ce2d3f5bad6df30c686558807bcffb0c5a96
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement FPCR.AH handling for scalar FABS and FABD
FPCR.AH == 1 mandates that taking the absolute value of a NaN should
not change its sign bit. This means we can no longer use
gen_vfp_abs*() everywhere but must instead generate slightly more
complex code when FPCR.AH is set.
Implement these semantics for scalar FABS and FABD. This change also
affects all other instructions whose psuedocode calls FPAbs(); we
will extend the change to those instructions in following commits.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 538deec62339594ecac4434e278b43b9807085e2
https://github.com/qemu/qemu/commit/538deec62339594ecac4434e278b43b9807085e2
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/helper.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in vector FABD
Split the handling of vector FABD so that it calls a different set
of helpers when FPCR.AH is 1, which implement the "no negation of
the sign of a NaN" semantics.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 47d3216240f642102821467809d6719509eebc12
https://github.com/qemu/qemu/commit/47d3216240f642102821467809d6719509eebc12
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FNEG
Make SVE FNEG honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 4de25ed588dd29387af78829197bc16cfa00aa2e
https://github.com/qemu/qemu/commit/4de25ed588dd29387af78829197bc16cfa00aa2e
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FABS
Make SVE FABS honour the FPCR.AH "don't negate the sign of a NaN"
semantics.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 60dd5806608ea9be3fb9b542dadf2909bd0acb76
https://github.com/qemu/qemu/commit/60dd5806608ea9be3fb9b542dadf2909bd0acb76
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FABD
Make the SVE FABD insn honour the FPCR.AH "don't negate the sign
of a NaN" semantics.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 416650ac2ba1f30ddb41bea92fe7b8b7d1f6ec73
https://github.com/qemu/qemu/commit/416650ac2ba1f30ddb41bea92fe7b8b7d1f6ec73
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_internal.h
Log Message:
-----------
target/arm: Handle FPCR.AH in negation steps in SVE FCADD
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this in the same way we did for
the base ASIMD FCADD, by encoding FPCR.AH into the SIMD data field
passed to the helper and using that to decide whether to negate the
values.
The construction of neg_imag and neg_real were done to make it easy
to apply both in parallel with two simple logical operations. This
changed with FPCR.AH, which is more complex than that. Switch to
an approach that follows the pseudocode more closely, by extracting
the 'rot=1' parameter from the SIMD data field and changing the
sign of the appropriate input value.
Note that there was a naming issue with neg_imag and neg_real.
They were named backward, with neg_imag being non-zero for rot=1,
and vice versa. This was combined with reversed usage within the
loop, so that the negation in the end turned out correct.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 72203eefab04a6903328807b0e3c635210031262
https://github.com/qemu/qemu/commit/72203eefab04a6903328807b0e3c635210031262
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in negation steps in FCADD
The negation steps in FCADD must honour FPCR.AH's "don't change the
sign of a NaN" semantics. Implement this by encoding FPCR.AH into
the SIMD data field passed to the helper and using that to decide
whether to negate the values.
The construction of neg_imag and neg_real were done to make it easy
to apply both in parallel with two simple logical operations. This
changed with FPCR.AH, which is more complex than that. Switch to
an approach closer to the pseudocode, where we extract the rot
parameter from the SIMD data word and negate the appropriate
input value.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 28048a3d180b3893912344869dfa64c1e6a7d40f
https://github.com/qemu/qemu/commit/28048a3d180b3893912344869dfa64c1e6a7d40f
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_internal.h
Log Message:
-----------
target/arm: Handle FPCR.AH in FRECPS and FRSQRTS scalar insns
Handle the FPCR.AH semantics that we do not change the sign of an
input NaN in the FRECPS and FRSQRTS scalar insns, by providing
new helper functions that do the CHS part of the operation
differently.
Since the extra helper functions would be very repetitive if written
out longhand, we condense them and the existing non-AH helpers into
being emitted via macros.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: fdf89638dc1ca42222685d06dc0c465e4735cf44
https://github.com/qemu/qemu/commit/fdf89638dc1ca42222685d06dc0c465e4735cf44
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in FRECPS and FRSQRTS vector insns
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in the vector versions of FRECPS and FRSQRTS, by implementing
new vector wrappers that call the _ah_ scalar helpers.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b85d8684c5f6be7d52355e1c8fc7444ee46a8237
https://github.com/qemu/qemu/commit/b85d8684c5f6be7d52355e1c8fc7444ee46a8237
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/helper.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in negation step in FMLS (indexed)
Handle the FPCR.AH "don't negate the sign of a NaN" semantics in FMLS
(indexed). We do this by creating 6 new helpers, which allow us to
do the negation either by XOR (for AH=0) or by muladd flags
(for AH=1).
Signed-off-by: Peter Maydell <[email protected]>
[PMM: Mostly from RTH's patch; error in index order into fns[][]
fixed]
Reviewed-by: Richard Henderson <[email protected]>
Commit: 1fae4f5e9f48f1620c20f33eb1c673276a301548
https://github.com/qemu/qemu/commit/1fae4f5e9f48f1620c20f33eb1c673276a301548
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/helper.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in negation in FMLS (vector)
Handle the FPCR.AH "don't negate the sign of a NaN" semantics
in FMLS (vector), by implementing a new set of helpers for
the AH=1 case.
The float_muladd_negate_product flag produces the same result
as negating either of the multiplication operands, assuming
neither of the operands are NaNs. But since FEAT_AFP does not
negate NaNs, this behaviour is exactly what we need.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 51330e58480b05cd39a9b913be9f83a0530471cb
https://github.com/qemu/qemu/commit/51330e58480b05cd39a9b913be9f83a0530471cb
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/helper-sve.h
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in negation step in SVE FMLS (vector)
Handle the FPCR.AH "don't negate the sign of a NaN" semantics fro the
SVE FMLS (vector) insns, by providing new helpers for the AH=1 case
which end up passing fpcr_ah = true to the do_fmla_zpzzz_* functions
that do the work.
The float*_muladd functions have a flags argument that can
perform optional negation of various operand. We don't use
that for "normal" arm fmla, because the muladd flags are not
applied when an input is a NaN. But since FEAT_AFP does not
negate NaNs, this behaviour is exactly what we need.
The non-AH helpers pass in a zero flags argument and control the
negation via the neg1 and neg3 arguments; the AH helpers always pass
in neg1 and neg3 as zero and control the negation via the flags
argument. This allows us to avoid conditional branches within the
inner loop.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 6dcd51ccf6815578bd34ea64a33a1eda9cc324e5
https://github.com/qemu/qemu/commit/6dcd51ccf6815578bd34ea64a33a1eda9cc324e5
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FTSSEL
The negation step in the SVE FTSSEL insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field
and use that to determine whether to do the negation.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 07e6b8d7526380a8a30081354f12f48f39d3464e
https://github.com/qemu/qemu/commit/07e6b8d7526380a8a30081354f12f48f39d3464e
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FTMAD
The negation step in the SVE FTMAD insn mustn't negate a NaN when
FPCR.AH is set. Pass FPCR.AH to the helper via the SIMD data field,
so we can select the correct behaviour.
Because the operand is known to be negative, negating the operand
is the same as taking the absolute value. Defer this to the muladd
operation via flags, so that it happens after NaN detection, which
is correct for FPCR.AH.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: a7868aaa30e4df6e6040fd96217e1febe247714a
https://github.com/qemu/qemu/commit/a7868aaa30e4df6e6040fd96217e1febe247714a
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in vector FCMLA
The negation step in FCMLA mustn't negate a NaN when FPCR.AH
is set. Handle this by passing FPCR.AH to the helper via the
SIMD data field, and use this to select whether to do the
negation via XOR or via the muladd negate_product flag.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: Expanded commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6d5ccfd44fdcf606ceadaab7c90d44ea7d5f4fe5
https://github.com/qemu/qemu/commit/6d5ccfd44fdcf606ceadaab7c90d44ea7d5f4fe5
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in FCMLA by index
The negation step in FCMLA by index mustn't negate a NaN when
FPCR.AH is set. Use the same approach as vector FCMLA of
passing in FPCR.AH and using it to select whether to negate
by XOR or by the muladd negate_product flag.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: Expanded commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0b5ca769cfae0039d6a71a4dd2d28845f96c4b81
https://github.com/qemu/qemu/commit/0b5ca769cfae0039d6a71a4dd2d28845f96c4b81
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FCMLA
The negation step in SVE FCMLA mustn't negate a NaN when FPCR.AH is
set. Use the same approach as we did for A64 FCMLA of passing in
FPCR.AH and using it to select whether to negate by XOR or by the
muladd negate_product flag.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0fa4b7afd4f78ed6ec0dedffba7dc93c00ca3d83
https://github.com/qemu/qemu/commit/0fa4b7afd4f78ed6ec0dedffba7dc93c00ca3d83
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in FMLSL (by element and vector)
Handle FPCR.AH's requirement to not negate the sign of a NaN
in FMLSL by element and vector, using the usual trick of
negating by XOR when AH=0 and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need toa pass in the
FPCR.AH value via the SIMD data word.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: commit message tweaked]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: f67a16e7d754cde9a55dd1e26ea4db48701b6fb9
https://github.com/qemu/qemu/commit/f67a16e7d754cde9a55dd1e26ea4db48701b6fb9
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FMLSL (indexed)
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need toa pass in the
FPCR.AH value via the SIMD data word.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: commit message tweaked]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: a66c4585fff70ffc4a61e0f5f5528320a55cd9cd
https://github.com/qemu/qemu/commit/a66c4585fff70ffc4a61e0f5f5528320a55cd9cd
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)
Handle FPCR.AH's requirement to not negate the sign of a NaN in SVE
FMLSL (indexed), using the usual trick of negating by XOR when AH=0
and by muladd flags when AH=1.
Since we have the CPUARMState* in the helper anyway, we can
look directly at env->vfp.fpcr and don't need toa pass in the
FPCR.AH value via the SIMD data word.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: tweaked commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: d38a57a3f1ea66c4338a10d70c032741e8786c51
https://github.com/qemu/qemu/commit/d38a57a3f1ea66c4338a10d70c032741e8786c51
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_AFP for '-cpu max'
Now that we have completed the handling for FPCR.{AH,FIZ,NEP}, we
can enable FEAT_AFP for '-cpu max', and document that we support it.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 0ff5c021f04d7dbaec174451e7a0dab3822b1b0d
https://github.com/qemu/qemu/commit/0ff5c021f04d7dbaec174451e7a0dab3822b1b0d
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/helper.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper
FEAT_RPRES implements an "increased precision" variant of the single
precision FRECPE and FRSQRTE instructions from an 8 bit to a 12
bit mantissa. This applies only when FPCR.AH == 1. Note that the
halfprec and double versions of these insns retain the 8 bit
precision regardless.
In this commit we add all the plumbing to make these instructions
call a new helper function when the increased-precision is in
effect. In the following commit we will provide the actual change
in behaviour in the helpers.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: c1567205e000369aec6c73bfbd60219098b34d3e
https://github.com/qemu/qemu/commit/c1567205e000369aec6c73bfbd60219098b34d3e
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Implement increased precision FRECPE
Implement the increased precision variation of FRECPE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRecipEstimate() and
RecipEstimate() functions.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 22330d2b0f6152d87114fec916f323e6726341d3
https://github.com/qemu/qemu/commit/22330d2b0f6152d87114fec916f323e6726341d3
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Implement increased precision FRSQRTE
Implement the increased precision variation of FRSQRTE. In the
pseudocode this corresponds to the handling of the
"increasedprecision" boolean in the FPRSqrtEstimate() and
RecipSqrtEstimate() functions.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b0bf37746bb9d66496ce8ef076c74388aa7ef899
https://github.com/qemu/qemu/commit/b0bf37746bb9d66496ce8ef076c74388aa7ef899
Author: Peter Maydell <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_RPRES for -cpu max
Now the emulation is complete, we can enable FEAT_RPRES for the 'max'
CPU type.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b902f5c62dbf2e796e39af55ed28294ec0467a56
https://github.com/qemu/qemu/commit/b902f5c62dbf2e796e39af55ed28294ec0467a56
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Introduce CPUARMState.vfp.fp_status[]
Move ARMFPStatusFlavour to cpu.h with which to index
this array. For now, place the array in an anonymous
union with the existing structures. Adjust the order
of the existing structures to match the enum.
Simplify fpstatus_ptr() using the new array.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7678859152df85c21380e3cf441eaab94f1a04ac
https://github.com/qemu/qemu/commit/7678859152df85c21380e3cf441eaab94f1a04ac
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/mve_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove standard_fp_status_f16
Replace with fp_status[FPST_STD_F16].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f069b26b8e6b7d03399fc4fd7540229f1cb45e27
https://github.com/qemu/qemu/commit/f069b26b8e6b7d03399fc4fd7540229f1cb45e27
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/mve_helper.c
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove standard_fp_status
Replace with fp_status[FPST_STD].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: fc25b174d5c514d70138bf2e77b1e32649bcead2
https://github.com/qemu/qemu/commit/fc25b174d5c514d70138bf2e77b1e32649bcead2
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove ah_fp_status_f16
Replace with fp_status[FPST_AH_F16].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ee4316f65b49cfdbec64ec99288d677ad68adb00
https://github.com/qemu/qemu/commit/ee4316f65b49cfdbec64ec99288d677ad68adb00
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove ah_fp_status
Replace with fp_status[FPST_AH].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c71296565c0d3763615885306aa6a9904ea32869
https://github.com/qemu/qemu/commit/c71296565c0d3763615885306aa6a9904ea32869
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove fp_status_f16_a64
Replace with fp_status[FPST_A64_F16].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 828def800e864c0ec781ea3eb5488ab186f0e24b
https://github.com/qemu/qemu/commit/828def800e864c0ec781ea3eb5488ab186f0e24b
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove fp_status_f16_a32
Replace with fp_status[FPST_A32_F16].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1c349f43b18608d57a72a3d6d5e95b28a1c14470
https://github.com/qemu/qemu/commit/1c349f43b18608d57a72a3d6d5e95b28a1c14470
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/sme_helper.c
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove fp_status_a64
Replace with fp_status[FPST_A64].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 54afbf663234756ebc89a1cfee0a8d4c578b26f7
https://github.com/qemu/qemu/commit/54afbf663234756ebc89a1cfee0a8d4c578b26f7
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/tcg/vec_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Remove fp_status_a32
Replace with fp_status[FPST_A32]. As this was the last of the
old structures, we can remove the anonymous union and struct.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
[PMM: tweak to account for change to is_ebf()]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f81c46987aad633ff8c9a7d0fece6c3839ccc463
https://github.com/qemu/qemu/commit/f81c46987aad633ff8c9a7d0fece6c3839ccc463
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/mve_helper.c
Log Message:
-----------
target/arm: Simplify fp_status indexing in mve_helper.c
Select on index instead of pointer.
No functional change.
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d75f68047624e5337963690a9a96906fcca3aefe
https://github.com/qemu/qemu/commit/d75f68047624e5337963690a9a96906fcca3aefe
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Simplify DO_VFP_cmp in vfp_helper.c
Pass ARMFPStatusFlavour index instead of fp_status[FOO].
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: bbeed9f06a4e66d444bcde9ef4bdd21e866b7d77
https://github.com/qemu/qemu/commit/bbeed9f06a4e66d444bcde9ef4bdd21e866b7d77
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Read fz16 from env->vfp.fpcr
Read the bit from the source, rather than from the proxy via
get_flush_inputs_to_zero. This makes it clear that it does
not matter which of the float_status structures is used.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: ca4c34e07d1388df8e396520b5e7d60883cd3690
https://github.com/qemu/qemu/commit/ca4c34e07d1388df8e396520b5e7d60883cd3690
Author: Richard Henderson <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Sink fp_status and fpcr access into do_fmlal*
Sink common code from the callers into do_fmlal
and do_fmlal_idx. Reorder the arguments to minimize
the re-sorting from the caller's arguments.
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 617017f8dce8d8f0cd4d175cbfaac0b4077b4a1e
https://github.com/qemu/qemu/commit/617017f8dce8d8f0cd4d175cbfaac0b4077b4a1e
Author: Eric Blake <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M docs/tools/qemu-nbd.rst
M qemu-nbd.c
Log Message:
-----------
qemu-nbd: Allow users to adjust handshake limit
Although defaulting the handshake limit to 10 seconds was a nice QoI
change to weed out intentionally slow clients, it can interfere with
integration testing done with manual NBD_OPT commands over 'nbdsh
--opt-mode'. Expose a command line option to allow the user to alter
the timeout away from the default. This option is unlikely to be used
in enough scenarios to warrant a short option letter.
The option --handshake-limit intentionally differs from the name of
the constant added in commit fb1c2aaa98 (limit instead of max_secs)
and the QMP name to be added in the next commit; this is because
typing a longer command-line name is undesirable and there is
sufficient --help text to document the units.
Signed-off-by: Eric Blake <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Commit: ff12e6a5ff904e68e222b0ba567938943e0f4b68
https://github.com/qemu/qemu/commit/ff12e6a5ff904e68e222b0ba567938943e0f4b68
Author: Eric Blake <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M block/monitor/block-hmp-cmds.c
M blockdev-nbd.c
M include/block/nbd.h
M qapi/block-export.json
Log Message:
-----------
nbd/server: Allow users to adjust handshake limit in QMP
Although defaulting the handshake limit to 10 seconds was a nice QoI
change to weed out intentionally slow clients, it can interfere with
integration testing done with manual NBD_OPT commands over 'nbdsh
--opt-mode'. Expose a QMP knob 'handshake-max-secs' to allow the user
to alter the timeout away from the default.
The parameter name here intentionally matches the spelling of the
constant added in commit fb1c2aaa98, and not the command-line spelling
added in the previous patch for qemu-nbd; that's because in QMP,
longer names serve as good self-documentation, and unlike the command
line, machines don't have problems generating longer spellings.
Signed-off-by: Eric Blake <[email protected]>
Message-ID: <[email protected]>
[eblake: s/max-secs/max-seconds/ in QMP]
Acked-by: Markus Armbruster <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Commit: 5dd3a714d50d2777a33b53c7cb3192fbd49f4bb7
https://github.com/qemu/qemu/commit/5dd3a714d50d2777a33b53c7cb3192fbd49f4bb7
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
R hw/loongarch/acpi-build.c
M hw/loongarch/meson.build
A hw/loongarch/virt-acpi-build.c
Log Message:
-----------
hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build
File acpi-build.c is relative with virt machine type, rename it with
virt-acpi-build.c
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Commit: e733b473b875cb65d7f4544e34fc19491249ae25
https://github.com/qemu/qemu/commit/e733b473b875cb65d7f4544e34fc19491249ae25
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/loongarch/virt-acpi-build.c
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: Rename function prefix name
Replace function prefix name loongarch_xxx with virt_xxx in file
virt-acpi-build.c
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 3754f985a8816a966b72da0ec8fb9e8a3cf689b9
https://github.com/qemu/qemu/commit/3754f985a8816a966b72da0ec8fb9e8a3cf689b9
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/loongarch/meson.build
A hw/loongarch/virt-fdt-build.c
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: Add separate file for fdt building
Similiar with virt-acpi-build.c, file virt-fdt-build.c is added here.
And move functions relative with fdt table building to the file.
It is only code movement and there is no function change.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 28bec94c7da29860c27394b1668afc85762db981
https://github.com/qemu/qemu/commit/28bec94c7da29860c27394b1668afc85762db981
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch/virt: Set iocsr address space when CPU is created
There is only one iocsr address space for the whole virt-machine
board. When CPU is created, the one of percpu points to that of
the board.
Here set iocsr address space when CPU is created rather than IPI
creation stage.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 2d2c37c492770ab627c0e60836198745a45c0385
https://github.com/qemu/qemu/commit/2d2c37c492770ab627c0e60836198745a45c0385
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/loongarch/virt.c
M target/loongarch/cpu.h
Log Message:
-----------
hw/loongarch/virt: Remove unused ipistate
Field ipistate in LoongArch CPU object is not used any more,
remove it here.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 456739ce4347c21b6fa2ec1b6585bc4a6504446f
https://github.com/qemu/qemu/commit/456739ce4347c21b6fa2ec1b6585bc4a6504446f
Author: Bibo Mao <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: CPU irq line connection improvement
Interrupt controller extioi and ipi connect to CPU with irq line method.
With command -smp x, -device la464-loongarch-cpu, smp.cpus is not
accurate for all possible CPU objects, possible_cpu_arch_ids() is used.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 5f1de4d3ce025fcb70b94ebe35241130d990d889
https://github.com/qemu/qemu/commit/5f1de4d3ce025fcb70b94ebe35241130d990d889
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M backends/iommufd.c
M hw/vfio/common.c
M hw/vfio/container.c
M hw/vfio/helpers.c
M hw/vfio/igd.c
M hw/vfio/iommufd.c
M hw/vfio/pci-quirks.c
A hw/vfio/pci-quirks.h
M hw/vfio/pci.c
M include/hw/vfio/vfio-common.h
M include/qapi/error.h
M util/error.c
Log Message:
-----------
Merge tag 'pull-vfio-20250211' of https://github.com/legoater/qemu into
staging
vfio queue:
* Coverity fix
* IGD cleanups using VFIOQuirk
* SIGSEV fix in IOMMUFD host IOMMU device
* Improved error reporting for MMIO region mapping failures
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmerTzQACgkQUaNDx8/7
# 7KHXLw/+LaONyFor+kuorb5et6rzyrE4keIUDv8zDTM4FnwFKP31wX8feQ63o17U
# DQUYN4uM5Ah/PemF/IBCj44x1Eirzl8LW51sMtxg/weCa8xrZOsHjmoKNml4f+zs
# ERzO/KSu9PWEWEyX79XGCcu5VQKl60b8Ra5QMBNKZKjVZpfBTxCjHZFIvQxSJFvm
# gPKHFDtmtbhtBnq3U/N/PwpnUuH4+p6ofz1eKdOcin11CAks7cAt6bl1CIs7sUbC
# ttrrQg6D+UJ5b+ISZjsw5hakfRIdtlZ/lS4jk678gN06108CIMmFPLPaRu27mdX9
# 4wBiMSQM8fFbbHw66FQiPgJeeGAmG/PvdLN4SbRSujkEkKyEyqtH2dRINy9PNXj4
# ZXXugx7xqfPfTEC1lwsyGDdHdHH022V0ScdDpx+K87klRvu30ZjorB7QSCI7x+ZN
# yW2ztZQ2hNH6MsgrKTQS6MLArHgU+h0ycaHy+01jj5UKSs3xAf53wNnx2uoBmKGj
# gZB/tNFg60qeSuW900ybnBTaH60qLs6xzY7evDRa5cqPYJ+z/lRUYp45fmsgQ1yR
# 91PHhC/mQLFjQRc78vF6k7slMm/Fk8JOalZgYPtm+Atdw3ufjOexavoHqN3Sa1Us
# keKnR589kHikPd3zZN7sZzT8wMNTAcRbSy72360+PzEZ1Iiiu+M=
# =wpSw
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 11 Feb 2025 08:23:00 EST
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-vfio-20250211' of https://github.com/legoater/qemu:
vfio: Remove superfluous error report in vfio_listener_region_add()
vfio: Remove reports of DMA mapping errors in backends
vfio: Improve error reporting when MMIO region mapping fails
vfio: Introduce vfio_get_vfio_device()
vfio: Rephrase comment in vfio_listener_region_add() error path
vfio/pci: Replace "iommu_device" by "vIOMMU"
util/error: Introduce warn_report_err_once()
vfio/iommufd: Fix SIGSEV in iommufd_cdev_attach()
vfio/igd: use VFIOConfigMirrorQuirk for mirrored registers
vfio/pci: introduce config_offset field in VFIOConfigMirrorQuirk
vfio/pci: declare generic quirks in a new header file
vfio/igd: Fix potential overflow in igd_gtt_memory_size()
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: afbcca0ea41f109c2a5eae308d636dfcf98eb82b
https://github.com/qemu/qemu/commit/afbcca0ea41f109c2a5eae308d636dfcf98eb82b
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M docs/system/arm/emulation.rst
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M target/alpha/cpu.c
M target/alpha/fpu_helper.c
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/helper.h
M target/arm/internals.h
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/helper-sve.h
M target/arm/tcg/hflags.c
M target/arm/tcg/mve_helper.c
M target/arm/tcg/sme_helper.c
M target/arm/tcg/sve_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.h
M target/arm/tcg/vec_helper.c
M target/arm/tcg/vec_internal.h
M target/arm/vfp_helper.c
M target/hppa/fpu_helper.c
M target/i386/tcg/fpu_helper.c
M target/mips/fpu_helper.h
M target/mips/msa.c
M target/ppc/cpu_init.c
M target/rx/cpu.c
M target/sh4/cpu.c
M target/tricore/helper.c
M tests/fp/fp-bench.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250211' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* target/alpha: Don't corrupt error_code with unknown softfloat flags
* target/arm: Implement FEAT_AFP and FEAT_RPRES
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmereaQZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3gyLEACglOM4E0j1hRl/JZlWD384
# nZL01Hayp9xwSNn28hkXaajCxkErTWLuCZax1g1fBvt/Yqn+E3oFan8gIybMEVgK
# 9ei6/m45fuICSQQhifvYTtYhAMd5uclr0anjRp9gN7FH6aaNPan/ZQYcKYxFq6cp
# RDTF5qiHIgTeXAlU+WiioxravL3A/D+jcQMYLEI5L+Vt5nYNM589PSNFWNLQ6W9e
# Gtmvp0uzrRSZgWxR3nOvhsn1NS/xXK90Zil+GPBo4jf82QVumqKYMsAcireOlxfk
# zTlHXH3PuonGj/ZPLxmiVKYhLb1RglQ9kIs/FHVel18QTz4dJ3DaJp8QXCNHbrKz
# 3aUwSiIh5Y/s3Q/X2Qy3jUHQ5tSjayhIhGFbn6zPdZ+2JZbIEu1Czeparddu/Zlq
# OR0CMVo2Lj/C6OakEU1/YRTKBKiNBaN1eVHi7gjzTDBdbMMC7ZlNuimpFAbthmSC
# szHzkgX8LXHzJqe4vip27yOMFBRPxvst/CXcEoPnjsLEQhLlKjOeFiHuEI+DUvaI
# 24AJ5b0FDdSOEcaFkxFD6gxW8E77MiNtBncfxDxTMKHs/4yFGiDihSPnOCANn3Kk
# zpQIwl0KJAPTA6Cldck9lY7MsKgGPTUNhEThadZlInbp4Uc6T1bvNDtB9b7osDfy
# FeposcM1+GBeuSde0yD6oQ==
# =P3wv
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 11 Feb 2025 11:24:04 EST
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250211' of
https://git.linaro.org/people/pmaydell/qemu-arm: (68 commits)
target/arm: Sink fp_status and fpcr access into do_fmlal*
target/arm: Read fz16 from env->vfp.fpcr
target/arm: Simplify DO_VFP_cmp in vfp_helper.c
target/arm: Simplify fp_status indexing in mve_helper.c
target/arm: Remove fp_status_a32
target/arm: Remove fp_status_a64
target/arm: Remove fp_status_f16_a32
target/arm: Remove fp_status_f16_a64
target/arm: Remove ah_fp_status
target/arm: Remove ah_fp_status_f16
target/arm: Remove standard_fp_status
target/arm: Remove standard_fp_status_f16
target/arm: Introduce CPUARMState.vfp.fp_status[]
target/arm: Enable FEAT_RPRES for -cpu max
target/arm: Implement increased precision FRSQRTE
target/arm: Implement increased precision FRECPE
target/arm: Plumb FEAT_RPRES frecpe and frsqrte through to new helper
target/arm: Enable FEAT_AFP for '-cpu max'
target/arm: Handle FPCR.AH in SVE FMLSLB, FMLSLT (vectors)
target/arm: Handle FPCR.AH in SVE FMLSL (indexed)
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: d384903bb4b7def3f7f0d03e4707ca53f7584f1e
https://github.com/qemu/qemu/commit/d384903bb4b7def3f7f0d03e4707ca53f7584f1e
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M block/monitor/block-hmp-cmds.c
M blockdev-nbd.c
M docs/tools/qemu-nbd.rst
M include/block/nbd.h
M qapi/block-export.json
M qemu-nbd.c
Log Message:
-----------
Merge tag 'pull-nbd-2025-02-11' of https://repo.or.cz/qemu/ericb into staging
NBD patches for 2025-02-11
- Add --handshake-limit option to qemu-nbd
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCAAdFiEEccLMIrHEYCkn0vOqp6FrSiUnQ2oFAmersd8ACgkQp6FrSiUn
# Q2pDUAf/c7inV7W+9vQv15lZoadIJkXAhqu+j1YuITC52gMgmU1QcwXMXRPEak4V
# qEIodiInzOtktMRXr6tbMroQgqo9eNd+VivxVa+J5LBILuZwdpZnLxsVNjblhbfI
# R3swWs2qluh9/1czntRu0J+YVOj3YZnF86Z5+iwEdLQ+i15dtjXDirBRvGCd6miV
# HLiEXwHdyPYb4g50a5oZCf3HhqPOgXOd+NWr4ifGut3bDulQk+FMDeBwV6/fmRPw
# g7dFPHMrAEYMw8tScYTMCoZGSZl0lg1JNuSh/WwgXx7BgXtDDxyP4HaAXlIyOHIA
# FbPU6aNrGZ9EDN4NA688IwUDh+lkmQ==
# =WyjJ
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 11 Feb 2025 15:23:59 EST
# gpg: using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <[email protected]>" [full]
# gpg: aka "Eric Blake (Free Software Programmer)
<[email protected]>" [full]
# gpg: aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2 F3AA A7A1 6B4A 2527 436A
* tag 'pull-nbd-2025-02-11' of https://repo.or.cz/qemu/ericb:
nbd/server: Allow users to adjust handshake limit in QMP
qemu-nbd: Allow users to adjust handshake limit
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: de278e54aefed143526174335f8286f7437d20be
https://github.com/qemu/qemu/commit/de278e54aefed143526174335f8286f7437d20be
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
R hw/loongarch/acpi-build.c
M hw/loongarch/meson.build
A hw/loongarch/virt-acpi-build.c
A hw/loongarch/virt-fdt-build.c
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
M target/loongarch/cpu.h
Log Message:
-----------
Merge tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu into
staging
loongarch queue
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ6wQngAKCRAfewwSUazn
# 0SggAQDk5mp90dBJwu05kioq+Inx/bwxmamweA+FmeqAnoQ79QEApDBPfppkrN2y
# AxNZL0EL5zRFU3zECSTevpRMQ3UoVQk=
# =tLFD
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 11 Feb 2025 22:08:14 EST
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20250212' of https://gitlab.com/bibo-mao/qemu:
hw/loongarch/virt: CPU irq line connection improvement
hw/loongarch/virt: Remove unused ipistate
hw/loongarch/virt: Set iocsr address space when CPU is created
hw/loongarch/virt: Add separate file for fdt building
hw/loongarch/virt: Rename function prefix name
hw/loongarch/virt: Rename filename acpi-build with virt-acpi-build
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/f9edf32ea2e1...de278e54aefe
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