Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: f8af22afec5092ce641fb5e5305f2bb9b232f206
https://github.com/qemu/qemu/commit/f8af22afec5092ce641fb5e5305f2bb9b232f206
Author: Jeuk Kim <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M hw/ufs/ufs.c
Log Message:
-----------
hw/ufs: Fix legacy single doorbell support bit
QEMU UFS has supported both legacy single doorbell and MCQ,
but the LSDBS value was incorrectly set. This change corrects
the LSDBS value to 0.
Signed-off-by: Jeuk Kim <[email protected]>
Commit: e041d3d2165994311a6ee4bee6d1c7864ff81916
https://github.com/qemu/qemu/commit/e041d3d2165994311a6ee4bee6d1c7864ff81916
Author: Jeuk Kim <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tests/qtest/ufs-test.c
Log Message:
-----------
tests/qtest/ufs-test: Cleanup unused code
Removed dead code related to the unimplemented task
management request.
Acked-by: Fabiano Rosas <[email protected]>
Signed-off-by: Jeuk Kim <[email protected]>
Commit: 5cb3566a5860f35a8871277748616b9ab11f5cd2
https://github.com/qemu/qemu/commit/5cb3566a5860f35a8871277748616b9ab11f5cd2
Author: Jeuk Kim <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tests/qtest/ufs-test.c
Log Message:
-----------
tests/qtest/ufs-test: Prepare for MCQ test
In legacy doorbell mode, the command descriptor slot matched
the UTRD slot. To maintain consistency in MCQ mode, command descriptor
slot allocation and deallocation now use a bitmap-based approach.
Acked-by: Fabiano Rosas <[email protected]>
Signed-off-by: Jeuk Kim <[email protected]>
Commit: a54596a96006096798b172a368ae952a231f9f72
https://github.com/qemu/qemu/commit/a54596a96006096798b172a368ae952a231f9f72
Author: Jeuk Kim <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tests/qtest/ufs-test.c
Log Message:
-----------
tests/qtest/ufs-test: Add test code for MCQ functionality
This patch tests whether MCQ initialization and basic read-write
operations work correctly when the MCQ parameter of hw/ufs is enabled.
Acked-by: Fabiano Rosas <[email protected]>
Signed-off-by: Jeuk Kim <[email protected]>
Commit: 0718db23779ab5a4beaf9bf36cfd17743f1d781b
https://github.com/qemu/qemu/commit/0718db23779ab5a4beaf9bf36cfd17743f1d781b
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/tcg.c
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
These should have been removed with the rest. There are
a couple of hosts which can emit guest_base into the
constant pool: aarch64, mips64, ppc64, riscv64.
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and
TCG_TARGET_NEED_POOL_LABELS")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 85f5e838de1424f85aa9a6f372d4d470ccf5ff69
https://github.com/qemu/qemu/commit/85f5e838de1424f85aa9a6f372d4d470ccf5ff69
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-all.c
M docs/devel/multi-thread-tcg.rst
M include/qemu/atomic.h
R include/tcg/oversized-guest.h
M target/arm/ptw.c
M target/riscv/cpu_helper.c
Log Message:
-----------
tcg: Remove TCG_OVERSIZED_GUEST
This is now prohibited in configuration.
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 64493300e68cdc56877c3421fd45be7145c24310
https://github.com/qemu/qemu/commit/64493300e68cdc56877c3421fd45be7145c24310
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
tcg: Drop support for two address registers in gen_ldst
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ccff2232f95e3477e5188307ecd108fda530c72f
https://github.com/qemu/qemu/commit/ccff2232f95e3477e5188307ecd108fda530c72f
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
Since 64-on-32 is now unsupported, guest addresses always
fit in one host register. Drop the replication of opcodes.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 304fd9d95582b92362441af01158ad04cfa8e803
https://github.com/qemu/qemu/commit/304fd9d95582b92362441af01158ad04cfa8e803
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Drop addrhi from prepare_host_addr
The guest address will now always be TCG_TYPE_I32.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1fd43ad683d2ad036537e1769f834e8fcb6ec284
https://github.com/qemu/qemu/commit/1fd43ad683d2ad036537e1769f834e8fcb6ec284
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f47c21817b2084ce7fa9e315573d7d9d24eb37f4
https://github.com/qemu/qemu/commit/f47c21817b2084ce7fa9e315573d7d9d24eb37f4
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a39b5984fad2890d513e5c096e3c075d47257d22
https://github.com/qemu/qemu/commit/a39b5984fad2890d513e5c096e3c075d47257d22
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a3fc7e9a26639a9f7a698ea19e6c68dcc697ce92
https://github.com/qemu/qemu/commit/a3fc7e9a26639a9f7a698ea19e6c68dcc697ce92
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
Log Message:
-----------
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
There is now always only one guest address register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e96fe46de929dd43e0085592355e474067a979c6
https://github.com/qemu/qemu/commit/e96fe46de929dd43e0085592355e474067a979c6
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M plugins/api.c
Log Message:
-----------
plugins: Fix qemu_plugin_read_memory_vaddr parameters
The declaration uses uint64_t for addr.
Fixes: 595cd9ce2ec ("plugins: add plugin API to read guest memory")
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 014b1d2679344117b965a0764b4d3ebc5dbb10d8
https://github.com/qemu/qemu/commit/014b1d2679344117b965a0764b4d3ebc5dbb10d8
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
The declarations use vaddr for size.
Signed-off-by: Richard Henderson <[email protected]>
Commit: bc2c6bcab4cae63ba6ca804d353a722fa4fa90d7
https://github.com/qemu/qemu/commit/bc2c6bcab4cae63ba6ca804d353a722fa4fa90d7
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/translate.c
Log Message:
-----------
target/loongarch: Use VADDR_PRIx for logging pc_next
DisasContextBase.pc_next has type vaddr; use the correct log format.
Signed-off-by: Richard Henderson <[email protected]>
Commit: ced12aa00246d4e0d1fa8b7ac0d9eb16e732f816
https://github.com/qemu/qemu/commit/ced12aa00246d4e0d1fa8b7ac0d9eb16e732f816
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M include/exec/vaddr.h
Log Message:
-----------
include/exec: Change vaddr to uintptr_t
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 59dc7af25d15d19b975024931fbba8df5dd09bca
https://github.com/qemu/qemu/commit/59dc7af25d15d19b975024931fbba8df5dd09bca
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/tlb-common.h
M tcg/arm/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
include/exec: Use uintptr_t in CPUTLBEntry
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host. This shrinks
the size of the structure to 16 bytes on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 070bc0dfd3406dba7081a925c6b7464338ac004c
https://github.com/qemu/qemu/commit/070bc0dfd3406dba7081a925c6b7464338ac004c
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
tcg: Introduce the 'z' constraint for a hardware zero register
For loongarch, mips, riscv and sparc, a zero register is
available all the time. For aarch64, register index 31
depends on context: sometimes it is the stack pointer,
and sometimes it is the zero register.
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This differs from existing
constant constraints in that const_arg[*] is recorded as
false, indicating that the value is in a register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fbb4fd4934b4d9e701a72eb9fcccc51c70599a60
https://github.com/qemu/qemu/commit/fbb4fd4934b4d9e701a72eb9fcccc51c70599a60
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Use 'z' constraint
Note that 'Z' is still used for addsub2.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 016f7bbc4079dfc01104bcc2ffaf520936d21290
https://github.com/qemu/qemu/commit/016f7bbc4079dfc01104bcc2ffaf520936d21290
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cf7ee4dc6f7ee95d60d02f012456b24a0c7d59a7
https://github.com/qemu/qemu/commit/cf7ee4dc6f7ee95d60d02f012456b24a0c7d59a7
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ea9eb781db7cc7d61dcbce560060707d5f3344e5
https://github.com/qemu/qemu/commit/ea9eb781db7cc7d61dcbce560060707d5f3344e5
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a80b12049e3aaf6ee4960f66cda40ccc18ff67a4
https://github.com/qemu/qemu/commit/a80b12049e3aaf6ee4960f66cda40ccc18ff67a4
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e35d88b5327427b62a4b4f4e0753e2e164fbaacf
https://github.com/qemu/qemu/commit/e35d88b5327427b62a4b4f4e0753e2e164fbaacf
Author: Fabiano Rosas <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
elfload: Fix alignment when unmapping excess reservation
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the start of region to be unmapped.
Fixes: c81d1fafa6 ("linux-user: Honor elf alignment when placing images")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1913
Signed-off-by: Fabiano Rosas <[email protected]>
[rth: Align load_end as well.]
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 90a7b2318bfe4fd6f009e01dbbe8abcfa8e4892a
https://github.com/qemu/qemu/commit/90a7b2318bfe4fd6f009e01dbbe8abcfa8e4892a
Author: Andreas Schwab <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M linux-user/aarch64/target_signal.h
M linux-user/arm/target_signal.h
M linux-user/generic/signal.h
M linux-user/i386/target_signal.h
M linux-user/m68k/target_signal.h
M linux-user/microblaze/target_signal.h
M linux-user/ppc/target_signal.h
M linux-user/s390x/target_signal.h
M linux-user/sh4/target_signal.h
M linux-user/x86_64/target_signal.h
M linux-user/xtensa/target_signal.h
Log Message:
-----------
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h. This leads to corrupted
data and out-of-bounds accesses.
Move the definition of TARGET_SA_RESTORER out of generic/signal.h into the
target_signal.h files that need it. Note that m68k has the sa_restorer
field, but does not use it and does not define SA_RESTORER.
Reported-by: Thomas Weißschuh <[email protected]>
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Thomas Weißschuh <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: ae20eb881c6f6de465ad0683727890d77f0dd211
https://github.com/qemu/qemu/commit/ae20eb881c6f6de465ad0683727890d77f0dd211
Author: Mikael Szreder <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M target/sparc/insns.decode
Log Message:
-----------
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Cc: [email protected]
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder <[email protected]>
Acked-by: Artyom Tarasenko <[email protected]>
[rth: Squash patches together, since the second fixes a typo in the first.]
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 6ac1e4e41cc9fb6f2313dab78f3d5f8cd70f2bf7
https://github.com/qemu/qemu/commit/6ac1e4e41cc9fb6f2313dab78f3d5f8cd70f2bf7
Author: Mikael Szreder <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M target/sparc/gdbstub.c
Log Message:
-----------
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and even register indexes. For example, the register index of f32 is 64
and f34 is 65.
Cc: [email protected]
Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
Signed-off-by: Mikael Szreder <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: b313081b5004ea1bdb224aeeaa98e0cc92cb64fa
https://github.com/qemu/qemu/commit/b313081b5004ea1bdb224aeeaa98e0cc92cb64fa
Author: Artyom Tarasenko <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: fake UltraSPARC T1 PCR and PIC registers
Fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 79cc45b4db26fcb02d00677c419f7b66609a96d6
https://github.com/qemu/qemu/commit/79cc45b4db26fcb02d00677c419f7b66609a96d6
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
Eliminate code repetition by using the appropriate helpers.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb
https://github.com/qemu/qemu/commit/a39bdd0f4ba96fcbb6b5bcb6e89591d2b24f52eb
Author: Richard Henderson <[email protected]>
Date: 2025-02-17 (Mon, 17 Feb 2025)
Changed paths:
M tcg/loongarch64/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
These defines never should have been added as they were
never used. Only 32-bit hosts may have these opcodes and
they have them unconditionally.
Fixes: 6cb14e4de29 ("tcg/loongarch64: Add the tcg-target.h file")
Fixes: fb1f70f3685 ("tcg/riscv: Add the tcg-target.h file")
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d6c4d5be7a2d455c3838c6c3c3812a48c47a8208
https://github.com/qemu/qemu/commit/d6c4d5be7a2d455c3838c6c3c3812a48c47a8208
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M hw/ufs/ufs.c
M tests/qtest/ufs-test.c
Log Message:
-----------
Merge tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu into
staging
ufs-next-mcq-test-v1
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# gpg: Signature made Mon 17 Feb 2025 17:21:34 HKT
# gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602
# gpg: Good signature from "Jeuk Kim <[email protected]>" [unknown]
# gpg: aka "Jeuk Kim <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602
* tag 'pull-ufs-20250217' of https://gitlab.com/jeuk20.kim/qemu:
tests/qtest/ufs-test: Add test code for MCQ functionality
tests/qtest/ufs-test: Prepare for MCQ test
tests/qtest/ufs-test: Cleanup unused code
hw/ufs: Fix legacy single doorbell support bit
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: bda596493c1d4628d1d215b5e824afadca649baa
https://github.com/qemu/qemu/commit/bda596493c1d4628d1d215b5e824afadca649baa
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-all.c
M docs/devel/multi-thread-tcg.rst
M docs/devel/tcg-ops.rst
M include/exec/tlb-common.h
M include/exec/vaddr.h
M include/qemu/atomic.h
R include/tcg/oversized-guest.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M linux-user/aarch64/target_signal.h
M linux-user/arm/target_signal.h
M linux-user/elfload.c
M linux-user/generic/signal.h
M linux-user/i386/target_signal.h
M linux-user/m68k/target_signal.h
M linux-user/microblaze/target_signal.h
M linux-user/ppc/target_signal.h
M linux-user/s390x/target_signal.h
M linux-user/sh4/target_signal.h
M linux-user/x86_64/target_signal.h
M linux-user/xtensa/target_signal.h
M plugins/api.c
M target/arm/ptw.c
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/translate.c
M target/riscv/cpu_helper.c
M target/sparc/gdbstub.c
M target/sparc/insns.decode
M target/sparc/translate.c
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20250215-2' of https://gitlab.com/rth7680/qemu into
staging
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
tcg: Cleanups after disallowing 64-on-32
tcg: Introduce constraint for zero register
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
linux-user: Fix alignment when unmapping excess reservation
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
target/sparc: fake UltraSPARC T1 PCR and PIC registers
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# gpg: Signature made Tue 18 Feb 2025 01:57:51 HKT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250215-2' of https://gitlab.com/rth7680/qemu: (27 commits)
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
target/sparc: fake UltraSPARC T1 PCR and PIC registers
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
elfload: Fix alignment when unmapping excess reservation
tcg/sparc64: Use 'z' constraint
tcg/riscv: Use 'z' constraint
tcg/mips: Use 'z' constraint
tcg/loongarch64: Use 'z' constraint
tcg/aarch64: Use 'z' constraint
tcg: Introduce the 'z' constraint for a hardware zero register
include/exec: Use uintptr_t in CPUTLBEntry
include/exec: Change vaddr to uintptr_t
target/loongarch: Use VADDR_PRIx for logging pc_next
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
plugins: Fix qemu_plugin_read_memory_vaddr parameters
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
tcg/ppc: Drop addrhi from prepare_host_addr
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/db7aa99ef894...bda596493c1d
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