Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f051a9c4dc70cd1b6eafa61aec8f3b9344e02e85
https://github.com/qemu/qemu/commit/f051a9c4dc70cd1b6eafa61aec8f3b9344e02e85
Author: William Roche <[email protected]>
Date: 2025-02-11 (Tue, 11 Feb 2025)
Changed paths:
M system/physmem.c
Log Message:
-----------
system/physmem: take into account fd_offset for file fallocate
Punching a hole in a file with fallocate needs to take into account the
fd_offset value for a correct file location.
But guest_memfd internal use doesn't currently consider fd_offset.
Fixes: 4b870dc4d0c0 ("hostmem-file: add offset option")
Signed-off-by: William Roche <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 52012209e1802e67aa186459e3e965f669e553df
https://github.com/qemu/qemu/commit/52012209e1802e67aa186459e3e965f669e553df
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M include/exec/memory.h
Log Message:
-----------
physmem: factor out memory_region_is_ram_device() check in
memory_access_is_direct()
As documented in commit 4a2e242bbb306 ("memory: Don't use memcpy for
ram_device regions"), we disallow direct access to RAM DEVICE regions.
Let's make this clearer to prepare for further changes. Note that romd
regions will never be RAM DEVICE at the same time.
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: e76d7b6b8cd564d4d5ea6e7c7daea541e100caa4
https://github.com/qemu/qemu/commit/e76d7b6b8cd564d4d5ea6e7c7daea541e100caa4
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M include/exec/memory.h
Log Message:
-----------
physmem: factor out RAM/ROMD check in memory_access_is_direct()
Let's factor more of the generic "is this directly accessible" check,
independent of the "write" condition out.
Note that the "!mr->rom_device" check in the write case essentially
disallows the memory_region_is_romd() condition again. Further note that
RAM DEVICE regions are also RAM regions, so we can check for RAM+ROMD
first.
This is a preparation for further changes.
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 7fd970a7d35af543992bf85e77b75de6b8125eb1
https://github.com/qemu/qemu/commit/7fd970a7d35af543992bf85e77b75de6b8125eb1
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M include/exec/memory.h
Log Message:
-----------
physmem: factor out direct access check into
memory_region_supports_direct_access()
Let's factor the complete "directly accessible" check independent of
the "write" condition out so we can reuse it next.
We can now split up the checks RAM and ROMD check, so we really only check
for RAM DEVICE in case of RAM -- ROM DEVICE is neither RAM not RAM DEVICE.
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: d4337aa8e222802d342b9f58440ca8e005b8bf91
https://github.com/qemu/qemu/commit/d4337aa8e222802d342b9f58440ca8e005b8bf91
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M system/physmem.c
Log Message:
-----------
physmem: disallow direct access to RAM DEVICE in address_space_write_rom()
As documented in commit 4a2e242bbb306 ("memory: Don't use memcpy for
ram_device regions"), we disallow direct access to RAM DEVICE regions.
This change implies that address_space_write_rom() and
cpu_memory_rw_debug() won't be able to write to RAM DEVICE regions. It
will also affect cpu_flush_icache_range(), but it's only used by
hw/core/loader.c after writing to ROM, so it is expected to not apply
here with RAM DEVICE.
This fixes direct access to these regions where we don't want direct
access. We'll extend cpu_memory_rw_debug() next to also be able to write to
these (and IO) regions.
This is a preparation for further changes.
Cc: Alex Williamson <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: d732b5a4ac3e8222e9527654f067bb766fdaecb6
https://github.com/qemu/qemu/commit/d732b5a4ac3e8222e9527654f067bb766fdaecb6
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/core/loader.c
M hw/display/apple-gfx.m
M hw/remote/vfio-user-obj.c
M include/exec/memory.h
M system/memory_ldst.c.inc
M system/physmem.c
Log Message:
-----------
memory: pass MemTxAttrs to memory_access_is_direct()
We want to pass another flag that will be stored in MemTxAttrs. So pass
MemTxAttrs directly.
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[peterx: Fix MacOS builds]
Signed-off-by: Peter Xu <[email protected]>
Commit: 425ce9b37b98799b46cd0bed0df3dc3af25ba57a
https://github.com/qemu/qemu/commit/425ce9b37b98799b46cd0bed0df3dc3af25ba57a
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M monitor/hmp-cmds-target.c
Log Message:
-----------
hmp: use cpu_get_phys_page_debug() in hmp_gva2gpa()
We don't need the MemTxAttrs, so let's simply use the simpler function
variant.
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 1cceedd7726556052d3d3bcf08a07b7762f8aa7c
https://github.com/qemu/qemu/commit/1cceedd7726556052d3d3bcf08a07b7762f8aa7c
Author: David Hildenbrand <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/core/cpu-system.c
M include/exec/memattrs.h
M include/exec/memory.h
M system/physmem.c
Log Message:
-----------
physmem: teach cpu_memory_rw_debug() to write to more memory regions
Right now, we only allow for writing to memory regions that allow direct
access using memcpy etc; all other writes are simply ignored. This
implies that debugging guests will not work as expected when writing
to MMIO device regions.
Let's extend cpu_memory_rw_debug() to write to more memory regions,
including MMIO device regions. Reshuffle the condition in
memory_access_is_direct() to make it easier to read and add a comment.
While this change implies that debug access can now also write to MMIO
devices, we now are also permit ELF image loads and similar users of
cpu_memory_rw_debug() to write to MMIO devices; currently we ignore
these writes.
Peter assumes [1] that there's probably a class of guest images, which
will start writing junk (likely zeroes) into device model registers; we
previously would silently ignore any such bogus ELF sections. Likely
these images are of questionable correctness and this can be ignored. If
ever a problem, we could make these cases use address_space_write_rom()
instead, which is left unchanged for now.
This patch is based on previous work by Stefan Zabka.
[1]
https://lore.kernel.org/all/CAFEAcA_2CEJKFyjvbwmpt=on=GgMVamQ5hiiVt+zUr6AY3X=x...@mail.gmail.com/
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/213
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: c1cda1c5f8faf18994dacb8c733ad22e22c2318f
https://github.com/qemu/qemu/commit/c1cda1c5f8faf18994dacb8c733ad22e22c2318f
Author: William Roche <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M accel/kvm/kvm-all.c
M include/exec/cpu-common.h
M system/physmem.c
Log Message:
-----------
system/physmem: handle hugetlb correctly in qemu_ram_remap()
The list of hwpoison pages used to remap the memory on reset
is based on the backend real page size.
To correctly handle hugetlb, we must mmap(MAP_FIXED) a complete
hugetlb page; hugetlb pages cannot be partially mapped.
Signed-off-by: William Roche <[email protected]>
Co-developed-by: David Hildenbrand <[email protected]>
Acked-by: David Hildenbrand <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 30943e496f2b0a49357581af480bdcd74fb338f5
https://github.com/qemu/qemu/commit/30943e496f2b0a49357581af480bdcd74fb338f5
Author: William Roche <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M system/physmem.c
Log Message:
-----------
system/physmem: poisoned memory discard on reboot
Repair poisoned memory location(s), calling ram_block_discard_range():
punching a hole in the backend file when necessary and regenerating
a usable memory.
If the kernel doesn't support the madvise calls used by this function
and we are dealing with anonymous memory, fall back to remapping the
location(s).
Signed-off-by: William Roche <[email protected]>
Acked-by: David Hildenbrand <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: e76fadf93e4d64492206b34fd3d434b515450d2c
https://github.com/qemu/qemu/commit/e76fadf93e4d64492206b34fd3d434b515450d2c
Author: Daniil Tatianin <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M include/system/os-posix.h
M include/system/os-win32.h
M meson.build
M migration/postcopy-ram.c
M os-posix.c
M system/vl.c
Log Message:
-----------
os: add an ability to lock memory on_fault
This will be used in the following commits to make it possible to only
lock memory on fault instead of right away.
Signed-off-by: Daniil Tatianin <[email protected]>
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[peterx: fail os_mlock(on_fault=1) when not supported]
[peterx: use G_GNUC_UNUSED instead of "(void)on_fault", per Dan]
Signed-off-by: Peter Xu <[email protected]>
Commit: cb74f2b8a65cde2eadbcb5574327ac3f49983d8a
https://github.com/qemu/qemu/commit/cb74f2b8a65cde2eadbcb5574327ac3f49983d8a
Author: Daniil Tatianin <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M system/vl.c
Log Message:
-----------
system/vl: extract overcommit option parsing into a helper
This will be extended in the future commits, let's move it out of line
right away so that it's easier to read.
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: Daniil Tatianin <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: cd2e472e54a49c13b0a728cdda7c10c50421e23d
https://github.com/qemu/qemu/commit/cd2e472e54a49c13b0a728cdda7c10c50421e23d
Author: Daniil Tatianin <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M hw/virtio/virtio-mem.c
M include/system/system.h
M migration/postcopy-ram.c
M system/globals.c
M system/vl.c
Log Message:
-----------
system: introduce a new MlockState enum
Replace the boolean value enable_mlock with an enum and add a helper to
decide whether we should be calling os_mlock.
This is a stepping stone towards introducing a new mlock mode, which
will be the third possible state of this enum.
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: Daniil Tatianin <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 13057e064a3edae7abf9ca2c207cdf48b82c5aad
https://github.com/qemu/qemu/commit/13057e064a3edae7abf9ca2c207cdf48b82c5aad
Author: Daniil Tatianin <[email protected]>
Date: 2025-02-12 (Wed, 12 Feb 2025)
Changed paths:
M include/system/system.h
M migration/postcopy-ram.c
M qemu-options.hx
M system/globals.c
M system/vl.c
Log Message:
-----------
overcommit: introduce mem-lock=on-fault
Locking the memory without MCL_ONFAULT instantly prefaults any mmaped
anonymous memory with a write-fault, which introduces a lot of extra
overhead in terms of memory usage when all you want to do is to prevent
kcompactd from migrating and compacting QEMU pages. Add an option to
only lock pages lazily as they're faulted by the process by using
MCL_ONFAULT if asked.
Reviewed-by: Vladimir Sementsov-Ogievskiy <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Signed-off-by: Daniil Tatianin <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Peter Xu <[email protected]>
Commit: 3a3b282879e83efdee1cb752e75351725e07e90a
https://github.com/qemu/qemu/commit/3a3b282879e83efdee1cb752e75351725e07e90a
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/tcg.c
M tcg/tci/tcg-target.h
Log Message:
-----------
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
These should have been removed with the rest. There are
a couple of hosts which can emit guest_base into the
constant pool: aarch64, mips64, ppc64, riscv64.
Fixes: a417ef835058 ("tcg: Remove TCG_TARGET_NEED_LDST_LABELS and
TCG_TARGET_NEED_POOL_LABELS")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Commit: f441b4d19b289f55a378b8d033994f45a333b581
https://github.com/qemu/qemu/commit/f441b4d19b289f55a378b8d033994f45a333b581
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-all.c
M docs/devel/multi-thread-tcg.rst
M include/qemu/atomic.h
R include/tcg/oversized-guest.h
M target/arm/ptw.c
M target/riscv/cpu_helper.c
Log Message:
-----------
tcg: Remove TCG_OVERSIZED_GUEST
This is now prohibited in configuration.
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a0ecb8e49418ab0bb01d47493fafe6a0a357e952
https://github.com/qemu/qemu/commit/a0ecb8e49418ab0bb01d47493fafe6a0a357e952
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/tcg-op-ldst.c
M tcg/tcg.c
Log Message:
-----------
tcg: Drop support for two address registers in gen_ldst
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 50b7a197e1d1782f9366d5e43d1f94700f6236c8
https://github.com/qemu/qemu/commit/50b7a197e1d1782f9366d5e43d1f94700f6236c8
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_qemu_*_{a32,a64}_*
Since 64-on-32 is now unsupported, guest addresses always
fit in one host register. Drop the replication of opcodes.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d9a8889f6d10f586e28f4bfb8611cf0bc36fcaa9
https://github.com/qemu/qemu/commit/d9a8889f6d10f586e28f4bfb8611cf0bc36fcaa9
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Drop addrhi from prepare_host_addr
The guest address will now always be TCG_TYPE_I32.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: dc8e2f8f7840835e51f23b891b75a79101efc91c
https://github.com/qemu/qemu/commit/dc8e2f8f7840835e51f23b891b75a79101efc91c
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0d000618d92344e0575018dcaa8ebc01e2d589b3
https://github.com/qemu/qemu/commit/0d000618d92344e0575018dcaa8ebc01e2d589b3
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7a967f34660c06f8d304fecd118f046fe21cb261
https://github.com/qemu/qemu/commit/7a967f34660c06f8d304fecd118f046fe21cb261
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Drop addrhi from prepare_host_addr
The guest address will now always fit in one register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0cd38379a8f47f3bbfb0b0c8419a7de28f8c9b8c
https://github.com/qemu/qemu/commit/0cd38379a8f47f3bbfb0b0c8419a7de28f8c9b8c
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
Log Message:
-----------
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
There is now always only one guest address register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 09ac62682b8d2a8bac36d068f63a31331cc6259a
https://github.com/qemu/qemu/commit/09ac62682b8d2a8bac36d068f63a31331cc6259a
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M plugins/api.c
Log Message:
-----------
plugins: Fix qemu_plugin_read_memory_vaddr parameters
The declaration uses uint64_t for addr.
Fixes: 595cd9ce2ec ("plugins: add plugin API to read guest memory")
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 252394c95baddf3d61f95cdd0c4697298de425d4
https://github.com/qemu/qemu/commit/252394c95baddf3d61f95cdd0c4697298de425d4
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
The declarations use vaddr for size.
Signed-off-by: Richard Henderson <[email protected]>
Commit: a0ea8654e525a2bd5c4c197948d3ba179ded90c7
https://github.com/qemu/qemu/commit/a0ea8654e525a2bd5c4c197948d3ba179ded90c7
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/translate.c
Log Message:
-----------
target/loongarch: Use VADDR_PRIx for logging pc_next
DisasContextBase.pc_next has type vaddr; use the correct log format.
Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual
addresses")
Signed-off-by: Richard Henderson <[email protected]>
Commit: a630055df39e1960275d0e273af036f794b15662
https://github.com/qemu/qemu/commit/a630055df39e1960275d0e273af036f794b15662
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M target/mips/tcg/octeon_translate.c
Log Message:
-----------
target/mips: Use VADDR_PRIx for logging pc_next
DisasContextBase.pc_next has type vaddr; use the correct log format.
Fixes: 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase for virtual
addresses")
Signed-off-by: Richard Henderson <[email protected]>
Commit: a70af12addd9060fdf8f3dbd42b42e3072c3914f
https://github.com/qemu/qemu/commit/a70af12addd9060fdf8f3dbd42b42e3072c3914f
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M include/exec/vaddr.h
Log Message:
-----------
include/exec: Change vaddr to uintptr_t
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bf455ec50b6fea15b4d2493059365bf94c706273
https://github.com/qemu/qemu/commit/bf455ec50b6fea15b4d2493059365bf94c706273
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/exec/tlb-common.h
M tcg/arm/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
include/exec: Use uintptr_t in CPUTLBEntry
Since we no longer support 64-bit guests on 32-bit hosts,
we can use a 32-bit type on a 32-bit host. This shrinks
the size of the structure to 16 bytes on a 32-bit host.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6b8abd244b9355bc840bc14182aae9043f86f2f6
https://github.com/qemu/qemu/commit/6b8abd244b9355bc840bc14182aae9043f86f2f6
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.h
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target.h
M tcg/riscv/tcg-target.h
M tcg/sparc64/tcg-target.h
M tcg/tcg.c
Log Message:
-----------
tcg: Introduce the 'z' constraint for a hardware zero register
For loongarch, mips, riscv and sparc, a zero register is
available all the time. For aarch64, register index 31
depends on context: sometimes it is the stack pointer,
and sometimes it is the zero register.
Introduce a new general-purpose constraint which maps 0
to TCG_REG_ZERO, if defined. This differs from existing
constant constraints in that const_arg[*] is recorded as
false, indicating that the value is in a register.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3d5939e57f959a30eaf13a7897e56a2388121cc2
https://github.com/qemu/qemu/commit/3d5939e57f959a30eaf13a7897e56a2388121cc2
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Use 'z' constraint
Note that 'Z' is still used for addsub2.
Signed-off-by: Richard Henderson <[email protected]>
Commit: 305370e78d31f742d0b5db4809cf00ef3eeea2a2
https://github.com/qemu/qemu/commit/305370e78d31f742d0b5db4809cf00ef3eeea2a2
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 065c8f64161b4b1334e4d244dfb4e9d66551e4c2
https://github.com/qemu/qemu/commit/065c8f64161b4b1334e4d244dfb4e9d66551e4c2
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f466db1e27131e58d1cfac0d7ce2eb5b28ed22a3
https://github.com/qemu/qemu/commit/f466db1e27131e58d1cfac0d7ce2eb5b28ed22a3
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1bbcae5adaad2d8f026194002f54913be5ee0933
https://github.com/qemu/qemu/commit/1bbcae5adaad2d8f026194002f54913be5ee0933
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Use 'z' constraint
Replace target-specific 'Z' with generic 'z'.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4b7b20a3b72c5000ea71bef505c16e6e628268b6
https://github.com/qemu/qemu/commit/4b7b20a3b72c5000ea71bef505c16e6e628268b6
Author: Fabiano Rosas <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M linux-user/elfload.c
Log Message:
-----------
elfload: Fix alignment when unmapping excess reservation
When complying with the alignment requested in the ELF and unmapping
the excess reservation, having align_end not aligned to the guest page
causes the unmap to be rejected by the alignment check at
target_munmap and later brk adjustments hit an EEXIST.
Fix by aligning the start of region to be unmapped.
Fixes: c81d1fafa6 ("linux-user: Honor elf alignment when placing images")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1913
Signed-off-by: Fabiano Rosas <[email protected]>
[rth: Align load_end as well.]
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 513823e7521a09ed7ad1e32e6454bac3b2cbf52d
https://github.com/qemu/qemu/commit/513823e7521a09ed7ad1e32e6454bac3b2cbf52d
Author: Andreas Schwab <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M linux-user/aarch64/target_signal.h
M linux-user/arm/target_signal.h
M linux-user/generic/signal.h
M linux-user/i386/target_signal.h
M linux-user/m68k/target_signal.h
M linux-user/microblaze/target_signal.h
M linux-user/ppc/target_signal.h
M linux-user/s390x/target_signal.h
M linux-user/sh4/target_signal.h
M linux-user/x86_64/target_signal.h
M linux-user/xtensa/target_signal.h
Log Message:
-----------
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
SA_RESTORER and the associated sa_restorer field of struct sigaction are
an obsolete feature, not expected to be used by future architectures.
They are also absent on RISC-V, LoongArch, Hexagon and OpenRISC, but
defined due to their use of generic/signal.h. This leads to corrupted
data and out-of-bounds accesses.
Move the definition of TARGET_SA_RESTORER out of generic/signal.h into the
target_signal.h files that need it. Note that m68k has the sa_restorer
field, but does not use it and does not define SA_RESTORER.
Reported-by: Thomas Weißschuh <[email protected]>
Signed-off-by: Andreas Schwab <[email protected]>
Reviewed-by: Thomas Weißschuh <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 807c3ebd1e3fc2a1be6cdfc702ccea3fa0d2d9b2
https://github.com/qemu/qemu/commit/807c3ebd1e3fc2a1be6cdfc702ccea3fa0d2d9b2
Author: Mikael Szreder <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M target/sparc/insns.decode
Log Message:
-----------
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
A bug was introduced in commit 0bba7572d40d which causes the fdtox
and fqtox instructions to incorrectly select the destination registers.
More information and a test program can be found in issue #2802.
Cc: [email protected]
Fixes: 0bba7572d40d ("target/sparc: Perform DFPREG/QFPREG in decodetree")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2802
Signed-off-by: Mikael Szreder <[email protected]>
Acked-by: Artyom Tarasenko <[email protected]>
[rth: Squash patches together, since the second fixes a typo in the first.]
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 7a74e468089a58756b438d31a2a9a97f183780d7
https://github.com/qemu/qemu/commit/7a74e468089a58756b438d31a2a9a97f183780d7
Author: Mikael Szreder <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M target/sparc/gdbstub.c
Log Message:
-----------
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
The gdbstub implementation for the Sparc architecture would
incorrectly calculate the the floating point register offset.
This resulted in, for example, registers f32 and f34 to point to
the same value.
The issue was caused by the confusion between even register numbers
and even register indexes. For example, the register index of f32 is 64
and f34 is 65.
Cc: [email protected]
Fixes: 30038fd81808 ("target-sparc: Change fpr representation to doubles.")
Signed-off-by: Mikael Szreder <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 172e7644f336dd82cb8d56cfb964477731f34f43
https://github.com/qemu/qemu/commit/172e7644f336dd82cb8d56cfb964477731f34f43
Author: Artyom Tarasenko <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M target/sparc/insns.decode
M target/sparc/translate.c
Log Message:
-----------
target/sparc: fake UltraSPARC T1 PCR and PIC registers
Fake access to
PCR Performance Control Register
and
PIC Performance Instrumentation Counter.
Ignore writes in privileged mode, and return 0 on reads.
This allows booting Tribblix, MilaX and v9os under Niagara target.
Signed-off-by: Artyom Tarasenko <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 175aa36668d6e91157d5e5b092b441f96f46b05e
https://github.com/qemu/qemu/commit/175aa36668d6e91157d5e5b092b441f96f46b05e
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
Eliminate code repetition by using the appropriate helpers.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e726f65867087d86436de05e9f372a86ec1381a6
https://github.com/qemu/qemu/commit/e726f65867087d86436de05e9f372a86ec1381a6
Author: Richard Henderson <[email protected]>
Date: 2025-02-18 (Tue, 18 Feb 2025)
Changed paths:
M tcg/loongarch64/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
These defines never should have been added as they were
never used. Only 32-bit hosts may have these opcodes and
they have them unconditionally.
Fixes: 6cb14e4de29 ("tcg/loongarch64: Add the tcg-target.h file")
Fixes: fb1f70f3685 ("tcg/riscv: Add the tcg-target.h file")
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7389992c84ee15e6a5513f402bddf4388bcf9679
https://github.com/qemu/qemu/commit/7389992c84ee15e6a5513f402bddf4388bcf9679
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M accel/kvm/kvm-all.c
M hw/core/cpu-system.c
M hw/core/loader.c
M hw/display/apple-gfx.m
M hw/remote/vfio-user-obj.c
M hw/virtio/virtio-mem.c
M include/exec/cpu-common.h
M include/exec/memattrs.h
M include/exec/memory.h
M include/system/os-posix.h
M include/system/os-win32.h
M include/system/system.h
M meson.build
M migration/postcopy-ram.c
M monitor/hmp-cmds-target.c
M os-posix.c
M qemu-options.hx
M system/globals.c
M system/memory_ldst.c.inc
M system/physmem.c
M system/vl.c
Log Message:
-----------
Merge tag 'mem-next-pull-request' of https://gitlab.com/peterx/qemu into
staging
Memory pull request for 10.0
v2 changelog:
- Fix Mac (and possibly some other) build issues for two patches
- os: add an ability to lock memory on_fault
- memory: pass MemTxAttrs to memory_access_is_direct()
List of features:
- William's fix on ram hole punching when with file offset
- Daniil's patchset to introduce mem-lock=on-fault
- William's hugetlb hwpoison fix for size report & remap
- David's series to allow qemu debug writes to MMIOs
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# gpg: Signature made Thu 13 Feb 2025 01:37:04 HKT
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# gpg: Good signature from "Peter Xu <[email protected]>" [full]
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* tag 'mem-next-pull-request' of https://gitlab.com/peterx/qemu:
overcommit: introduce mem-lock=on-fault
system: introduce a new MlockState enum
system/vl: extract overcommit option parsing into a helper
os: add an ability to lock memory on_fault
system/physmem: poisoned memory discard on reboot
system/physmem: handle hugetlb correctly in qemu_ram_remap()
physmem: teach cpu_memory_rw_debug() to write to more memory regions
hmp: use cpu_get_phys_page_debug() in hmp_gva2gpa()
memory: pass MemTxAttrs to memory_access_is_direct()
physmem: disallow direct access to RAM DEVICE in address_space_write_rom()
physmem: factor out direct access check into
memory_region_supports_direct_access()
physmem: factor out RAM/ROMD check in memory_access_is_direct()
physmem: factor out memory_region_is_ram_device() check in
memory_access_is_direct()
system/physmem: take into account fd_offset for file fallocate
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 40efe733e10cc00e4fb4f9f5790a28e744e63c62
https://github.com/qemu/qemu/commit/40efe733e10cc00e4fb4f9f5790a28e744e63c62
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-19 (Wed, 19 Feb 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/tcg-all.c
M docs/devel/multi-thread-tcg.rst
M docs/devel/tcg-ops.rst
M include/exec/tlb-common.h
M include/exec/vaddr.h
M include/qemu/atomic.h
R include/tcg/oversized-guest.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M linux-user/aarch64/target_signal.h
M linux-user/arm/target_signal.h
M linux-user/elfload.c
M linux-user/generic/signal.h
M linux-user/i386/target_signal.h
M linux-user/m68k/target_signal.h
M linux-user/microblaze/target_signal.h
M linux-user/ppc/target_signal.h
M linux-user/s390x/target_signal.h
M linux-user/sh4/target_signal.h
M linux-user/x86_64/target_signal.h
M linux-user/xtensa/target_signal.h
M plugins/api.c
M target/arm/ptw.c
M target/loongarch/tcg/insn_trans/trans_atomic.c.inc
M target/loongarch/tcg/translate.c
M target/mips/tcg/octeon_translate.c
M target/riscv/cpu_helper.c
M target/sparc/gdbstub.c
M target/sparc/insns.decode
M target/sparc/translate.c
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
M tcg/aarch64/tcg-target.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/loongarch64/tcg-target.h
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target.c.inc
M tcg/mips/tcg-target.h
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/riscv/tcg-target.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-con-str.h
M tcg/sparc64/tcg-target.c.inc
M tcg/sparc64/tcg-target.h
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
M tcg/tci/tcg-target.h
Log Message:
-----------
Merge tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu into
staging
tcg: Remove last traces of TCG_TARGET_NEED_POOL_LABELS
tcg: Cleanups after disallowing 64-on-32
tcg: Introduce constraint for zero register
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
linux-user: Fix alignment when unmapping excess reservation
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
target/sparc: fake UltraSPARC T1 PCR and PIC registers
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# gpg: Signature made Wed 19 Feb 2025 00:30:23 HKT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
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* tag 'pull-tcg-20250215-3' of https://gitlab.com/rth7680/qemu: (28 commits)
tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64
tcg/i386: Use tcg_{high,unsigned}_cond in tcg_out_brcond2
target/sparc: fake UltraSPARC T1 PCR and PIC registers
target/sparc: Fix gdbstub incorrectly handling registers f32-f62
target/sparc: Fix register selection for all F*TOx and FxTO* instructions
linux-user: Move TARGET_SA_RESTORER out of generic/signal.h
elfload: Fix alignment when unmapping excess reservation
tcg/sparc64: Use 'z' constraint
tcg/riscv: Use 'z' constraint
tcg/mips: Use 'z' constraint
tcg/loongarch64: Use 'z' constraint
tcg/aarch64: Use 'z' constraint
tcg: Introduce the 'z' constraint for a hardware zero register
include/exec: Use uintptr_t in CPUTLBEntry
include/exec: Change vaddr to uintptr_t
target/mips: Use VADDR_PRIx for logging pc_next
target/loongarch: Use VADDR_PRIx for logging pc_next
accel/tcg: Fix tlb_set_page_with_attrs, tlb_set_page
plugins: Fix qemu_plugin_read_memory_vaddr parameters
tcg: Replace addr{lo,hi}_reg with addr_reg in TCGLabelQemuLdst
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/e0209297cddd...40efe733e10c
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