Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: b819fd6994243aee6f9613edbbacedce4f511c32
https://github.com/qemu/qemu/commit/b819fd6994243aee6f9613edbbacedce4f511c32
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Report correct syndrome for UNDEFINED CNTPS_*_EL1 from EL2 and NS
EL1
The access pseudocode for the CNTPS_TVAL_EL1, CNTPS_CTL_EL1 and
CNTPS_CVAL_EL1 secure timer registers says that they are UNDEFINED
from EL2 or NS EL1. We incorrectly return CP_ACCESS_TRAP from the
access function in these cases, which means that we report the wrong
syndrome value to the target EL.
Use CP_ACCESS_TRAP_UNCATEGORIZED, which reports the correct syndrome
value for an UNDEFINED instruction.
Cc: [email protected]
Fixes: b4d3978c2fd ("target-arm: Add the AArch64 view of the Secure physical
timer")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 1960d9701ef7ed8d24e98def767bbf05d63e6992
https://github.com/qemu/qemu/commit/1960d9701ef7ed8d24e98def767bbf05d63e6992
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Report correct syndrome for UNDEFINED AT ops with wrong NSE, NS
R_NYXTL says that these AT insns should be UNDEFINED if they
would operate on an EL lower than EL3 and SCR_EL3.{NSE,NS} is
set to the Reserved {1, 0}. We were incorrectly reporting
them with the wrong syndrome; use CP_ACCESS_TRAP_UNCATEGORIZED
so they are reported as UNDEFINED.
Cc: [email protected]
Fixes: 1acd00ef1410 ("target/arm/helper: Check SCR_EL3.{NSE, NS} encoding for
AT instructions")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: ccda792945d650bce4609c8dbce8814a220df1bb
https://github.com/qemu/qemu/commit/ccda792945d650bce4609c8dbce8814a220df1bb
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Report correct syndrome for UNDEFINED S1E2 AT ops at EL3
The pseudocode for AT S1E2R and AT S1E2W says that they should be
UNDEFINED if executed at EL3 when EL2 is not enabled. We were
incorrectly using CP_ACCESS_TRAP and reporting the wrong exception
syndrome as a result. Use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: [email protected]
Fixes: 2a47df953202e1 ("target-arm: Wire up AArch64 EL2 and EL3 address
translation ops")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 707d478ed8f2da6f2327e5af780890c1fd9c371a
https://github.com/qemu/qemu/commit/707d478ed8f2da6f2327e5af780890c1fd9c371a
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Report correct syndrome for UNDEFINED LOR sysregs when NS=0
The pseudocode for the accessors for the LOR sysregs says they
are UNDEFINED if SCR_EL3.NS is 0. We were reporting the wrong
syndrome value here; use CP_ACCESS_TRAP_UNCATEGORIZED.
Cc: [email protected]
Fixes: 2d7137c10faf ("target/arm: Implement the ARMv8.1-LOR extension")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 4cf4948651615181c5bc3d0e4a9f5c46be576bb2
https://github.com/qemu/qemu/commit/4cf4948651615181c5bc3d0e4a9f5c46be576bb2
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Make CP_ACCESS_TRAPs to AArch32 EL3 be Monitor traps
In system register access pseudocode the common pattern for
AArch32 registers with access traps to EL3 is:
at EL1 and EL2:
if HaveEL(EL3) && !ELUsingAArch32(EL3) && (SCR_EL3.TERR == 1) then
AArch64.AArch32SystemAccessTrap(EL3, 0x03);
elsif HaveEL(EL3) && ELUsingAArch32(EL3) && (SCR.TERR == 1) then
AArch32.TakeMonitorTrapException();
at EL3:
if (PSTATE.M != M32_Monitor) && (SCR.TERR == 1) then
AArch32.TakeMonitorTrapException();
(taking as an example the ERRIDR access pseudocode).
This implements the behaviour of (in this case) SCR.TERR that
"Accesses to the specified registers from modes other than Monitor
mode generate a Monitor Trap exception" and of SCR_EL3.TERR that
"Accesses of the specified Error Record registers at EL2 and EL1
are trapped to EL3, unless the instruction generates a higher
priority exception".
In QEMU we don't implement this pattern correctly in two ways:
* in access_check_cp_reg() we turn the CP_ACCESS_TRAP_EL3 into
an UNDEF, not a trap to Monitor mode
* in the access functions, we check trap bits like SCR.TERR
only when arm_current_el(env) < 3 -- this is correct for
AArch64 EL3, but misses the "trap non-Monitor-mode execution
at EL3 into Monitor mode" case for AArch32 EL3
In this commit we fix the first of these two issues, by
making access_check_cp_reg() handle CP_ACCESS_TRAP_EL3
as a Monitor trap. This is a kind of exception that we haven't
yet implemented(!), so we need a new EXCP_MON_TRAP for it.
This diverges from the pseudocode approach, where every access check
function explicitly checks for "if EL3 is AArch32" and takes a
monitor trap; if we wanted to be closer to the pseudocode we could
add a new CP_ACCESS_TRAP_MONITOR and make all the accessfns use it
when appropriate. But because there are no non-standard cases in the
pseudocode (i.e. where either it raises a Monitor trap that doesn't
correspond to an AArch64 SystemAccessTrap or where it raises a
SystemAccessTrap that doesn't correspond to a Monitor trap), handling
this all in one place seems less likely to result in future bugs
where we forgot again about this special case when writing an
accessor.
(The cc of stable here is because "hw/intc/arm_gicv3_cpuif: Don't
downgrade monitor traps for AArch32 EL3" which is also cc:stable
will implicitly use the new EXCP_MON_TRAP code path.)
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: d04c6c3c000ab3e588a2b91641310aeea89408f7
https://github.com/qemu/qemu/commit/d04c6c3c000ab3e588a2b91641310aeea89408f7
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif: Don't downgrade monitor traps for AArch32 EL3
In the gicv3_{irq,fiq,irqfiq}_access() functions, there is a check
which downgrades a CP_ACCESS_TRAP_EL3 to CP_ACCESS_TRAP if EL3 is not
AArch64. This has been there since the GIC was first implemented,
but it isn't right: if we are trapping because of SCR.IRQ or SCR.FIQ
then we definitely want to be going to EL3 (doing
AArch32.TakeMonitorTrapException() in pseudocode terms). We might
want to not take a trap at all, but we don't ever want to go to the
default target EL, because that would mean, for instance, taking a
trap to Hyp mode if the trapped access was made from Hyp mode.
(This might have been an attempt to work around our failure to
properly implement Monitor Traps.)
Remove the bogus check.
Cc: [email protected]
Fixes: 359fbe65e01e ("hw/intc/arm_gicv3: Implement GICv3 CPU interface
registers")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 4d436fb05c2a1fff7befc815ebcbb04a14977448
https://github.com/qemu/qemu/commit/4d436fb05c2a1fff7befc815ebcbb04a14977448
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Honour SDCR.TDCC and SCR.TERR in AArch32 EL3 non-Monitor modes
There are not many traps in AArch32 which should trap to Monitor
mode, but these trap bits should trap not just lower ELs to Monitor
mode but also the non-Monitor modes running at EL3 (i.e. Secure
System, Secure Undef, etc).
We get this wrong because the relevant access functions implement the
AArch64-style logic of
if (el < 3 && trap_bit_set) {
return CP_ACCESS_TRAP_EL3;
}
which won't trap the non-Monitor modes at EL3.
Correct this error by using arm_is_el3_or_mon() instead, which
returns true when the CPU is at AArch64 EL3 or AArch32 Monitor mode.
(Since the new callsites are compiled also for the linux-user mode,
we need to provide a dummy implementation for CONFIG_USER_ONLY.)
This affects only:
* trapping of ERRIDR via SCR.TERR
* trapping of the debug channel registers via SDCR.TDCC
* trapping of GICv3 registers via SCR.IRQ and SCR.FIQ
(which we already used arm_is_el3_or_mon() for)
This patch changes the handling of SCR.TERR and SDCR.TDCC. This
patch only changes guest-visible behaviour for "-cpu max" on
the qemu-system-arm binary, because SCR.TERR
and SDCR.TDCC (and indeed the entire SDCR register) only arrived
in Armv8, and the only guest CPU we support which has any v8
features and also starts in AArch32 EL3 is the 32-bit 'max'.
Other uses of CP_ACCESS_TRAP_EL3 don't need changing:
* uses in code paths that can't happen when EL3 is AArch32:
access_trap_aa32s_el1, cpacr_access, cptr_access, nsacr_access
* uses which are in accessfns for AArch64-only registers:
gt_stimer_access, gt_cntpoff_access, access_hxen, access_tpidr2,
access_smpri, access_smprimap, access_lor_ns, access_pauth,
access_mte, access_tfsr_el2, access_scxtnum, access_fgt
* trap bits which exist only in the AArch64 version of the
trap register, not the AArch32 one:
access_tpm, pmreg_access, access_dbgvcr32, access_tdra,
access_tda, access_tdosa (TPM, TDA and TDOSA exist only in
MDCR_EL3, not in SDCR, and we enforce this in sdcr_write())
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: ff8b906a00494601687763446e470ff9b3580be7
https://github.com/qemu/qemu/commit/ff8b906a00494601687763446e470ff9b3580be7
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
Log Message:
-----------
hw/intc/arm_gicv3_cpuif(): Remove redundant tests of is_a64()
In the gicv3_{irq,fiq,irqfiq}_access() functions, in the
arm_current_el(env) == 3 case we do the following test:
if (!is_a64(env) && !arm_is_el3_or_mon(env)) {
r = CP_ACCESS_TRAP_EL3;
}
In this check, the "!is_a64(env)" is redundant, because if
we are at EL3 and in AArch64 then arm_is_el3_or_mon() will
return true and we will skip the if() body anyway.
Remove the unnecessary tests.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 273d0e84ccd1f0a94f893d2f1ab750f812dfa219
https://github.com/qemu/qemu/commit/273d0e84ccd1f0a94f893d2f1ab750f812dfa219
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Support CP_ACCESS_TRAP_EL1 as a CPAccessResult
In the CPAccessResult enum, the CP_ACCESS_TRAP* values indicate the
equivalent of the pseudocode AArch64.SystemAccessTrap(..., 0x18),
causing a trap to a specified exception level with a syndrome value
giving information about the failing instructions. In the
pseudocode, such traps are always taken to a specified target EL. We
support that for target EL of 2 or 3 via CP_ACCESS_TRAP_EL2 and
CP_ACCESS_TRAP_EL3, but the only way to take the access trap to EL1
currently is to use CP_ACCESS_TRAP, which takes the trap to the
"usual target EL" (EL1 if in EL0, otherwise to the current EL).
Add CP_ACCESS_TRAP_EL1 so that access functions can follow the
pseudocode more closely.
(Note that for the common case in the pseudocode of "trap to
EL2 if HCR_EL2.TGE is set, otherwise trap to EL1", we handle
this in raise_exception(), so access functions don't need to
special case it and can use CP_ACCESS_TRAP_EL1.)
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 2d60f1acdb950e85335b018bcaf4ba0f042a350c
https://github.com/qemu/qemu/commit/2d60f1acdb950e85335b018bcaf4ba0f042a350c
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/debug_helper.c
M target/arm/helper.c
Log Message:
-----------
target/arm: Use CP_ACCESS_TRAP_EL1 for traps that are always to EL1
We currently use CP_ACCESS_TRAP in a number of access functions where
we know we're currently at EL0; in this case the "usual target EL"
is EL1, so CP_ACCESS_TRAP and CP_ACCESS_TRAP_EL1 behave the same.
Use CP_ACCESS_TRAP_EL1 to more closely match the pseudocode for
this sort of check.
Note that in the case of the access functions foc cacheop to
PoC or PoU, the code was correct but the comment was wrong:
SCTLR_EL1.UCI traps for DC CVAC, DC CIVAC, DC CVAP, DC CVADP,
DC CVAU and IC IVAU should be system access traps, not UNDEFs.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: f706b67da61aecc54bbdad16bea3fc69e9fd844b
https://github.com/qemu/qemu/commit/f706b67da61aecc54bbdad16bea3fc69e9fd844b
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Use TRAP_UNCATEGORIZED for XScale CPAR traps
On XScale CPUs, there is no EL2 or AArch64, so no syndrome register.
These traps are just UNDEFs in the traditional AArch32 sense, so
CP_ACCESS_TRAP_UNCATEGORIZED is more accurate than CP_ACCESS_TRAP.
This has no visible behavioural change, because the guest doesn't
have a way to see the syndrome value we generate.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: fc0ea471ec26cdc5639809c4ea4b70a80567f432
https://github.com/qemu/qemu/commit/fc0ea471ec26cdc5639809c4ea4b70a80567f432
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Remove CP_ACCESS_TRAP handling
There are no longer any uses of CP_ACCESS_TRAP in access functions,
because we have converted them all to use either CP_ACCESS_TRAP_EL1
or CP_ACCESS_TRAP_UNCATEGORIZED, as appropriate. Remove the handling
of bare CP_ACCESS_TRAP from the access_check_cp_reg() helper, so that
it now asserts if an access function returns a value requesting a
trap without a target EL.
Rename CP_ACCESS_TRAP to CP_ACCESS_TRAP_BIT, to make it clearer
that this is an internal-only definition, not something that
it makes sense to return from an access function. This should
help to avoid future bugs where we return the wrong syndrome
value by mistake.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 86d44c215e91da43555a2cfd58b7c6b725f036fb
https://github.com/qemu/qemu/commit/86d44c215e91da43555a2cfd58b7c6b725f036fb
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/helper.c
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Rename CP_ACCESS_TRAP_UNCATEGORIZED to CP_ACCESS_UNDEFINED
CP_ACCESS_TRAP_UNCATEGORIZED is technically an accurate description
of what this return value from a cpreg accessfn does, but it's liable
to confusion because it doesn't match how the Arm ARM pseudocode
indicates this case. What it does is an EXCP_UDEF with a zero
("uncategorized") syndrome value, which is what an UNDEFINED instruction
does. The pseudocode uses "UNDEFINED" to show this; rename our
constant to CP_ACCESS_UNDEFINED to make the parallel clearer.
Commit created with
sed -i -e 's/CP_ACCESS_TRAP_UNCATEGORIZED/CP_ACCESS_UNDEFINED/' $(git grep -l
CP_ACCESS_TRAP_UNCATEGORIZED)
plus manual editing of the comment.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 2b95a2d01b04afadf510a49ac14b38a59be8c5f5
https://github.com/qemu/qemu/commit/2b95a2d01b04afadf510a49ac14b38a59be8c5f5
Author: Peter Maydell <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Correct errors in WFI/WFE trapping
The code for WFI/WFE trapping has several errors:
* it wasn't using arm_sctlr(), so it would look at SCTLR_EL1
even if the CPU was in the EL2&0 translation regime
* it was raising UNDEF, not Monitor Trap, for traps to
AArch32 EL3 because of SCR.{TWE,TWI}
* it was not honouring SCR.{TWE,TWI} when running in
AArch32 at EL3 not in Monitor mode
* it checked SCR.{TWE,TWI} even on v7 CPUs which don't have
those bits
Fix these bugs.
Cc: [email protected]
Fixes: b1eced713d99 ("target-arm: Add WFx instruction trap support")
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 4ac4d6e77613ccbb9aa55675429dc0b9ae1f8ea6
https://github.com/qemu/qemu/commit/4ac4d6e77613ccbb9aa55675429dc0b9ae1f8ea6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos4210: Replace magic 32 by proper 'GIC_INTERNAL' definition
The 32 IRQ lines skipped are the GIC internal ones.
Use the GIC_INTERNAL definition for clarity.
No logical change.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 284e354566c31687cce260401549a616cf513c60
https://github.com/qemu/qemu/commit/284e354566c31687cce260401549a616cf513c60
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/exynos4210.c
Log Message:
-----------
hw/arm/exynos4210: Specify explicitly the GIC has 64 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6621cf52509b796f3c32a18b74248cf404dbe56f
https://github.com/qemu/qemu/commit/6621cf52509b796f3c32a18b74248cf404dbe56f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/realview.c
Log Message:
-----------
hw/arm/realview: Specify explicitly the GIC has 64 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"). Add the GIC_EXT_IRQS definition (with a comment)
to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2d269a8bbb7fc7148f429b13720c7b5d07bba3c0
https://github.com/qemu/qemu/commit/2d269a8bbb7fc7148f429b13720c7b5d07bba3c0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/xilinx_zynq: Replace IRQ_OFFSET -> GIC_INTERNAL
We already have a definition to distinct GIC internal
IRQs versus external ones, use it. No logical changes.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 92fea7f2e7818d3019b5c29eb8379049a3b1f0c4
https://github.com/qemu/qemu/commit/92fea7f2e7818d3019b5c29eb8379049a3b1f0c4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/xilinx_zynq.c
Log Message:
-----------
hw/arm/xilinx_zynq: Specify explicitly the GIC has 64 external IRQs
Looking at the Zynq 7000 SoC Technical Reference Manual (UG585 v1.14)
on Appendix A: Register Details, the mpcore Interrupt Controller Type
Register (ICDICTR) has the IT_Lines_Number field read-only with value
0x2, described as:
IT_Lines_Number
b00010 = the distributor provides 96 interrupts,
64 external interrupt lines.
Add a GIC_EXT_IRQS definition (with a comment) to make the number of
GIC external IRQs explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e2e5266c4555ed24a4727c9ce6e34eb5213a9ab6
https://github.com/qemu/qemu/commit/e2e5266c4555ed24a4727c9ce6e34eb5213a9ab6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/vexpress.c
Log Message:
-----------
hw/arm/vexpress: Specify explicitly the GIC has 64 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Versatile Express board however expects a fixed set of 64
interrupts (see the fixed IRQ length when this board was added in
commit 2055283bcc8 ("hw/vexpress: Add model of ARM Versatile Express
board"). Add the GIC_EXT_IRQS definition (with a comment) to make
that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2bf8bdcbb4510f206b3d0203c9bb8fb433387a90
https://github.com/qemu/qemu/commit/2bf8bdcbb4510f206b3d0203c9bb8fb433387a90
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/highbank.c
Log Message:
-----------
hw/arm/highbank: Specify explicitly the GIC has 128 external IRQs
When not specified, Cortex-A9MP configures its GIC with 64 external
IRQs, (see commit a32134aad89 "arm:make the number of GIC interrupts
configurable"), and Cortex-15MP to 128 (see commit 528622421eb
"hw/cpu/a15mpcore: Correct default value for num-irq").
The Caldexa Highbank board however expects a fixed set of 128
interrupts (see the fixed IRQ length when this board was added in
commit 2488514cef2 ("arm: SoC model for Calxeda Highbank"). Add the
GIC_EXT_IRQS definition (with a comment) to make that explicit.
Except explicitly setting a property value to its same implicit
value, there is no logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 262f4ab3d5e3fcb6e85e40d9e29d9914c17972ed
https://github.com/qemu/qemu/commit/262f4ab3d5e3fcb6e85e40d9e29d9914c17972ed
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/cpu/a15mpcore.c
M hw/cpu/a9mpcore.c
Log Message:
-----------
hw/cpu/arm_mpcore: Remove default values for GIC external IRQs
Implicit default values are often hard to figure out, better
be explicit. Now that all boards explicitly set the number of
GIC external IRQs, remove the default values (displaying an
error message if it is out of range).
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 464ce71a963b3dfc290cd59c3d1bfedf11c004df
https://github.com/qemu/qemu/commit/464ce71a963b3dfc290cd59c3d1bfedf11c004df
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/Kconfig
M hw/usb/Kconfig
M hw/usb/meson.build
Log Message:
-----------
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
TYPE_CHIPIDEA models an IP block which is also used in TYPE_ZYNQ_MACHINE which
itself is not an IMX device. CONFIG_ZYNQ selects CONFIG_USB_EHCI_SYSBUS while
TYPE_CHIPIDEA is a separate compilation unit, so only works by accident if
CONFIG_IMX is given. Fix that by extracting CONFIG_USB_CHIPIDEA from CONFIG_IMX.
cc: [email protected]
Fixes: 616ec12d0fcc "hw/arm/xilinx_zynq: Fix USB port instantiation"
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: b2ba5ff272e0738c6b82197fe61f73344e5edcfb
https://github.com/qemu/qemu/commit/b2ba5ff272e0738c6b82197fe61f73344e5edcfb
Author: Stephen Longfield <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Use uint32_t in t32_expandimm_imm()
In t32_expandimm_imm(), we take an 8 bit value XY and construct a
32-bit value which might be of the form XY, 00XY00XY, XY00XY00, or
XYXYXYXY. We do this with multiplications, and we use an 'int' type.
For the cases where we're setting the high byte of the 32-bit value
to XY, this means that we do an integer multiplication that might
overflow, and rely on the -fwrapv semantics to keep this from being
undefined behaviour.
It's clearer to use an unsigned type here, because we're really
doing operations on the value considered as a set of bits. The
result is the same.
The return value from the function remains 'int', because this
is a decodetree !function function, and follows the API for those
functions.
Signed-off-by: Stephen Longfield <[email protected]>
Signed-off-by: Roque Arcudia Hernandez <[email protected]>
Message-id: [email protected]
[PMM: Rewrote the commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 70ce076fa6dff60585c229a4b641b13e64bf03cf
https://github.com/qemu/qemu/commit/70ce076fa6dff60585c229a4b641b13e64bf03cf
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M pc-bios/npcm7xx_bootrom.bin
M roms/vbootrom
Log Message:
-----------
roms: Update vbootrom to 1287b6e
This newer vbootrom supports NPCM8xx. Similar to the NPCM7XX one
it supports loading the UBoot from the SPI device and not more.
We updated the npcm7xx bootrom to be compiled from this version.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 269b7effd906d6b22071971b7f5b4cb344403b86
https://github.com/qemu/qemu/commit/269b7effd906d6b22071971b7f5b4cb344403b86
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M MAINTAINERS
M pc-bios/README
M pc-bios/meson.build
A pc-bios/npcm8xx_bootrom.bin
M roms/Makefile
Log Message:
-----------
pc-bios: Add NPCM8XX vBootrom
The bootrom is a minimal bootrom used to load an NPCM8XX image.
The source code is located in the same repo as the NPCM7XX one:
github.com/google/vbootrom/tree/master/npcm8xx.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e9be8467b42f7e2af70694422f4b4d8afe82bf4e
https://github.com/qemu/qemu/commit/e9be8467b42f7e2af70694422f4b4d8afe82bf4e
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/npcm7xx.c
M hw/ssi/npcm7xx_fiu.c
M include/hw/ssi/npcm7xx_fiu.h
Log Message:
-----------
hw/ssi: Make flash size a property in NPCM7XX FIU
This allows different FIUs to have different flash sizes, useful
in NPCM8XX which has multiple different sized FIU modules.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Message-id: [email protected]
[PMM: flash_size must be a uint64_t to build on 32-bit hosts]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 506af2330cd0ef684a48aad12640a7bea8e95247
https://github.com/qemu/qemu/commit/506af2330cd0ef684a48aad12640a7bea8e95247
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/meson.build
R hw/misc/npcm7xx_gcr.c
A hw/misc/npcm_gcr.c
M include/hw/arm/npcm7xx.h
R include/hw/misc/npcm7xx_gcr.h
A include/hw/misc/npcm_gcr.h
Log Message:
-----------
hw/misc: Rename npcm7xx_gcr to npcm_gcr
NPCM7XX and NPCM8XX have a different set of GCRs and the GCR module
needs to fit both. This commit changes the name of the GCR module.
Future commits will add the support for NPCM8XX GCRs.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c99064e63748f993457f1fe658d05c662c0134f1
https://github.com/qemu/qemu/commit/c99064e63748f993457f1fe658d05c662c0134f1
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_gcr.c
M hw/misc/trace-events
M include/hw/arm/npcm7xx.h
M include/hw/misc/npcm_gcr.h
Log Message:
-----------
hw/misc: Move NPCM7XX GCR to NPCM GCR
A lot of NPCM7XX and NPCM8XX GCR modules share the same code,
this commit moves the NPCM7XX GCR to NPCM GCR for these
properties.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8ca2021b9d3aa3e9ef276bdbf04f89677341955c
https://github.com/qemu/qemu/commit/8ca2021b9d3aa3e9ef276bdbf04f89677341955c
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_gcr.c
M include/hw/misc/npcm_gcr.h
Log Message:
-----------
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
These 2 values are different between NPCM7XX and NPCM8XX
GCRs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d9ffb75f2a85a2271dc928849f02f7bada4d1507
https://github.com/qemu/qemu/commit/d9ffb75f2a85a2271dc928849f02f7bada4d1507
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_gcr.c
M include/hw/misc/npcm_gcr.h
Log Message:
-----------
hw/misc: Add support for NPCM8XX GCR
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0ad46bbb56585fc3900f803747c485529869ca22
https://github.com/qemu/qemu/commit/0ad46bbb56585fc3900f803747c485529869ca22
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_gcr.c
M include/hw/misc/npcm_gcr.h
Log Message:
-----------
hw/misc: Store DRAM size in NPCM8XX GCR Module
NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR
module. Since we don't simulate a detailed memory controller, we
need to store this information directly similar to the NPCM7XX's
INCTR3 register.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ca2fd966ea90b2ca02a4eff1afc2b89e963680a1
https://github.com/qemu/qemu/commit/ca2fd966ea90b2ca02a4eff1afc2b89e963680a1
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_gcr.c
M hw/misc/trace-events
Log Message:
-----------
hw/misc: Support 8-bytes memop in NPCM GCR module
The NPCM8xx GCR device can be accessed with 64-bit memory operations.
This patch supports that.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Philippe Mathieu-Daude <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c8283b0f4a7e9397da141d70e73e79341c5df2d7
https://github.com/qemu/qemu/commit/c8283b0f4a7e9397da141d70e73e79341c5df2d7
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/meson.build
R hw/misc/npcm7xx_clk.c
A hw/misc/npcm_clk.c
M include/hw/arm/npcm7xx.h
R include/hw/misc/npcm7xx_clk.h
A include/hw/misc/npcm_clk.h
Log Message:
-----------
hw/misc: Rename npcm7xx_clk to npcm_clk
NPCM7XX and NPCM8XX have a different set of CLK registers. This
commit changes the name of the clk files to be used by both
NPCM7XX and NPCM8XX CLK modules.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ca6d6a94f450f5fba92626704a5758cf4bb4a210
https://github.com/qemu/qemu/commit/ca6d6a94f450f5fba92626704a5758cf4bb4a210
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_clk.c
M hw/misc/trace-events
M include/hw/arm/npcm7xx.h
M include/hw/misc/npcm_clk.h
Log Message:
-----------
hw/misc: Move NPCM7XX CLK to NPCM CLK
A lot of NPCM7XX and NPCM8XX CLK modules share the same code,
this commit moves the NPCM7XX CLK to NPCM CLK for these
properties.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: cf76c4e174e128397763c4ec98b0aa3345bab3be
https://github.com/qemu/qemu/commit/cf76c4e174e128397763c4ec98b0aa3345bab3be
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_clk.c
M hw/misc/npcm_gcr.c
M include/hw/misc/npcm_clk.h
Log Message:
-----------
hw/misc: Add nr_regs and cold_reset_values to NPCM CLK
These 2 values are different between NPCM7XX and NPCM8XX
CLKs. So we add them to the class and assign different values
to them.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4e67d50deaf3132f392266e7251cf7ce17be8fa4
https://github.com/qemu/qemu/commit/4e67d50deaf3132f392266e7251cf7ce17be8fa4
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/misc/npcm_clk.c
M include/hw/misc/npcm_clk.h
Log Message:
-----------
hw/misc: Support NPCM8XX CLK Module Registers
NPCM8XX adds a few new registers and have a different set of reset
values to the CLK modules. This patch supports them.
This patch doesn't support the new clock values generated by these
registers. Currently no modules use these new clock values so they
are not necessary at this point.
Implementation of these clocks might be required when implementing
these modules.
Reviewed-by: Titus Rwantare <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9
https://github.com/qemu/qemu/commit/3d107d36f99c6eec8c8b3cb6bc387b0fcc69d7d9
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/net/meson.build
A hw/net/npcm_pcs.c
M hw/net/trace-events
A include/hw/net/npcm_pcs.h
Log Message:
-----------
hw/net: Add NPCM8XX PCS Module
The PCS exists in NPCM8XX's GMAC1 and is used to control the SGMII
PHY. This implementation contains all the default registers and
the soft reset feature that are required to load the Linux kernel
driver. Further features have not been implemented yet.
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ae0c4d1a12900fdb1d853fe0505e4ba96d4bffef
https://github.com/qemu/qemu/commit/ae0c4d1a12900fdb1d853fe0505e4ba96d4bffef
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M configs/devices/aarch64-softmmu/default.mak
M hw/arm/Kconfig
M hw/arm/meson.build
A hw/arm/npcm8xx.c
A include/hw/arm/npcm8xx.h
Log Message:
-----------
hw/arm: Add NPCM8XX SoC
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7e70eb3cad7c835f2ba447306927721101c0788f
https://github.com/qemu/qemu/commit/7e70eb3cad7c835f2ba447306927721101c0788f
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M hw/arm/meson.build
A hw/arm/npcm8xx_boards.c
M include/hw/arm/npcm8xx.h
Log Message:
-----------
hw/arm: Add NPCM845 Evaluation board
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Hao Wu <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1c3169179b8242866316108386800379c4e22974
https://github.com/qemu/qemu/commit/1c3169179b8242866316108386800379c4e22974
Author: Hao Wu <[email protected]>
Date: 2025-02-20 (Thu, 20 Feb 2025)
Changed paths:
M docs/system/arm/nuvoton.rst
M hw/arm/npcm8xx_boards.c
Log Message:
-----------
docs/system/arm: Add Description for NPCM8XX SoC
NPCM8XX SoC is the successor of the NPCM7XX. It features quad-core
Cortex-A35 (Armv8, 64-bit) CPUs and some additional peripherals.
This document describes the NPCM8XX SoC and an evaluation board
(NPCM 845 EVB).
Signed-off-by: Hao Wu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f41af4c5857b6983766aaffc041580ff170d0679
https://github.com/qemu/qemu/commit/f41af4c5857b6983766aaffc041580ff170d0679
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-21 (Fri, 21 Feb 2025)
Changed paths:
M MAINTAINERS
M configs/devices/aarch64-softmmu/default.mak
M docs/system/arm/nuvoton.rst
M hw/arm/Kconfig
M hw/arm/exynos4210.c
M hw/arm/highbank.c
M hw/arm/meson.build
M hw/arm/npcm7xx.c
A hw/arm/npcm8xx.c
A hw/arm/npcm8xx_boards.c
M hw/arm/realview.c
M hw/arm/vexpress.c
M hw/arm/xilinx_zynq.c
M hw/cpu/a15mpcore.c
M hw/cpu/a9mpcore.c
M hw/intc/arm_gicv3_cpuif.c
M hw/misc/meson.build
R hw/misc/npcm7xx_clk.c
R hw/misc/npcm7xx_gcr.c
A hw/misc/npcm_clk.c
A hw/misc/npcm_gcr.c
M hw/misc/trace-events
M hw/net/meson.build
A hw/net/npcm_pcs.c
M hw/net/trace-events
M hw/ssi/npcm7xx_fiu.c
M hw/usb/Kconfig
M hw/usb/meson.build
M include/hw/arm/npcm7xx.h
A include/hw/arm/npcm8xx.h
R include/hw/misc/npcm7xx_clk.h
R include/hw/misc/npcm7xx_gcr.h
A include/hw/misc/npcm_clk.h
A include/hw/misc/npcm_gcr.h
A include/hw/net/npcm_pcs.h
M include/hw/ssi/npcm7xx_fiu.h
M pc-bios/README
M pc-bios/meson.build
M pc-bios/npcm7xx_bootrom.bin
A pc-bios/npcm8xx_bootrom.bin
M roms/Makefile
M roms/vbootrom
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250220' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Fix some incorrect syndrome values in various sysreg traps
* Clean up sysreg trap code to avoid similar future bugs
* Make boards/SoCs using a9mpcore and a15mpcore objects specify
number of GIC interrupts explicitly
* Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
* target/arm: Use uint32_t in t32_expandimm_imm()
* New board model: NPCM845 Evaluation board "npcm845-evb"
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# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250220' of
https://git.linaro.org/people/pmaydell/qemu-arm: (41 commits)
docs/system/arm: Add Description for NPCM8XX SoC
hw/arm: Add NPCM845 Evaluation board
hw/arm: Add NPCM8XX SoC
hw/net: Add NPCM8XX PCS Module
hw/misc: Support NPCM8XX CLK Module Registers
hw/misc: Add nr_regs and cold_reset_values to NPCM CLK
hw/misc: Move NPCM7XX CLK to NPCM CLK
hw/misc: Rename npcm7xx_clk to npcm_clk
hw/misc: Support 8-bytes memop in NPCM GCR module
hw/misc: Store DRAM size in NPCM8XX GCR Module
hw/misc: Add support for NPCM8XX GCR
hw/misc: Add nr_regs and cold_reset_values to NPCM GCR
hw/misc: Move NPCM7XX GCR to NPCM GCR
hw/misc: Rename npcm7xx_gcr to npcm_gcr
hw/ssi: Make flash size a property in NPCM7XX FIU
pc-bios: Add NPCM8XX vBootrom
roms: Update vbootrom to 1287b6e
target/arm: Use uint32_t in t32_expandimm_imm()
Kconfig: Extract CONFIG_USB_CHIPIDEA from CONFIG_IMX
hw/cpu/arm_mpcore: Remove default values for GIC external IRQs
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/40efe733e10c...f41af4c5857b
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