Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: ab544de12787035edb7ad4994a80f9cd6a6b55d7
https://github.com/qemu/qemu/commit/ab544de12787035edb7ad4994a80f9cd6a6b55d7
Author: Nicolin Chen <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M hw/arm/smmuv3.c
Log Message:
-----------
hw/arm/smmuv3: Fill u.f_cd_fetch.addr for SMMU_EVT_F_CD_FETCH
When we fill in the SMMUEventInfo for SMMU_EVT_F_CD_FETCH we write
the address into the f_ste_fetch member of the union, but then when
we come to read it back in smmuv3_record_event() we will (correctly)
be using the f_cd_fetch member.
This is more like a cosmetics fix since the f_cd_fetch and f_ste_fetch are
basically the same field since they are in the exact same union with exact
same type, but it's conceptually wrong. Use the correct union member.
Signed-off-by: Nicolin Chen <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: f10104aeae3a17f181d5bb37b7fd7dad7fe86cba
https://github.com/qemu/qemu/commit/f10104aeae3a17f181d5bb37b7fd7dad7fe86cba
Author: Matthew R. Ochs <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M docs/system/arm/virt.rst
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Support larger highmem MMIO regions
The MMIO region size required to support virtualized environments with
large PCI BAR regions can exceed the hardcoded limit configured in QEMU.
For example, a VM with multiple NVIDIA Grace-Hopper GPUs passed through
requires more MMIO memory than the amount provided by VIRT_HIGH_PCIE_MMIO
(currently 512GB). Instead of updating VIRT_HIGH_PCIE_MMIO, introduce a
new parameter, highmem-mmio-size, that specifies the MMIO size required
to support the VM configuration.
Example usage with 1TB MMIO region size:
-machine virt,gic-version=3,highmem-mmio-size=1T
Signed-off-by: Matthew R. Ochs <[email protected]>
Reviewed-by: Gavin Shan <[email protected]>
Reviewed-by: Shameer Kolothum <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Reviewed-by: Nicolin Chen <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: cacf4cb2516aa4de94aa80fecb08be4dafa5ed44
https://github.com/qemu/qemu/commit/cacf4cb2516aa4de94aa80fecb08be4dafa5ed44
Author: Peter Maydell <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M monitor/hmp-cmds.c
Log Message:
-----------
monitor/hmp-cmds.c: Clean up hmp_dumpdtb printf
In hmp_dumpdtb(), we print a message when the command succeeds. This
message is missing the trailing \n, so the HMP command prompt is
printed immediately after it. We also weren't capitalizing 'DTB', or
quoting the filename in the message. Fix these nits.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 3c25f487bc0672bf13473f4a7235c3ef592c954c
https://github.com/qemu/qemu/commit/3c25f487bc0672bf13473f4a7235c3ef592c954c
Author: Peter Maydell <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M hw/openrisc/boot.c
M hw/openrisc/openrisc_sim.c
M hw/openrisc/virt.c
M include/hw/openrisc/boot.h
Log Message:
-----------
hw/openrisc: Support monitor dumpdtb command
The openrisc machines don't set MachineState::fdt to point to their
DTB blob. This means that although the command line '-machine
dumpdtb=file.dtb' option works, the equivalent QMP and HMP monitor
commands do not, but instead produce the error "This machine doesn't
have a FDT".
Set MachineState::fdt in openrisc_load_fdt(), when we write it to
guest memory.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: dfd0de718662a58ef2f2ef051939ed4b1a4d5ea7
https://github.com/qemu/qemu/commit/dfd0de718662a58ef2f2ef051939ed4b1a4d5ea7
Author: Peter Maydell <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M hw/mips/boston.c
Log Message:
-----------
hw/mips/boston: Check for error return from boston_fdt_filter()
The function boston_fdt_filter() can return NULL on errors (in which
case it will print an error message). When we call this from the
non-FIT-image codepath, we aren't checking the return value, so we
will plough on with a NULL pointer, and segfault in fdt_totalsize().
Check for errors here.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: db0dd33559ee97a1fe84a1272258646279aca2e2
https://github.com/qemu/qemu/commit/db0dd33559ee97a1fe84a1272258646279aca2e2
Author: Peter Maydell <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M hw/core/loader-fit.c
M hw/mips/boston.c
M include/hw/loader-fit.h
Log Message:
-----------
hw/mips/boston: Support dumpdtb monitor commands
The boston machine doesn't set MachineState::fdt to the DTB blob that
it has loaded or created, which means that the QMP/HMP dumpdtb
monitor commands don't work.
Setting MachineState::fdt is easy in the non-FIT codepath: we can
simply do so immediately before loading the DTB into guest memory.
The FIT codepath is a bit more awkward as currently the FIT loader
throws away the memory that the FDT was in after it loads it into
guest memory. So we add a void *pfdt argument to load_fit() for it
to store the FDT pointer into.
There is some readjustment required of the pointer handling in
loader-fit.c, so that it applies 'const' only where it should (e.g.
the data pointer we get back from fdt_getprop() is const, because
it's into the middle of the input FDT data, but the pointer that
fit_load_image_alloc() should not be const, because it's freshly
allocated memory that the caller can change if it likes).
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 8fd2518ef2f8d34dc9ee53d6915a2a610eb1a659
https://github.com/qemu/qemu/commit/8fd2518ef2f8d34dc9ee53d6915a2a610eb1a659
Author: Peter Maydell <[email protected]>
Date: 2025-02-24 (Mon, 24 Feb 2025)
Changed paths:
M hw/arm/boot.c
M hw/core/machine.c
M hw/loongarch/virt-fdt-build.c
M hw/mips/boston.c
M hw/openrisc/boot.c
M hw/ppc/e500.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M hw/riscv/boot.c
M include/system/device_tree.h
M system/device_tree.c
Log Message:
-----------
hw: Centralize handling of -machine dumpdtb option
Currently we handle the 'dumpdtb' machine sub-option ad-hoc in every
board model that has an FDT. It's up to the board code to make sure
it calls qemu_fdt_dumpdtb() in the right place.
This means we're inconsistent and often just ignore the user's
command line argument:
* if the board doesn't have an FDT at all
* if the board supports FDT, but there happens not to be one
present (usually because of a missing -fdt option)
This isn't very helpful because it gives the user no clue why their
option was ignored.
However, in order to support the QMP/HMP dumpdtb commands we require
now that every FDT machine stores a pointer to the FDT in
MachineState::fdt. This means we can handle -machine dumpdtb
centrally by calling the qmp_dumpdtb() function, unifying its
handling with the QMP/HMP commands. All the board code calls to
qemu_fdt_dumpdtb() can then be removed.
For this commit we retain the existing behaviour that if there
is no FDT we silently ignore the -machine dumpdtb option.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: b61b9d891305abf8fe37f07280ca5a99a10da6cf
https://github.com/qemu/qemu/commit/b61b9d891305abf8fe37f07280ca5a99a10da6cf
Author: Xianglai Li <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: fix vcpu reset command word issue
When the KVM_REG_LOONGARCH_VCPU_RESET command word
is sent to the kernel through the kvm_set_one_reg interface,
the parameter source needs to be a legal address,
otherwise the kernel will return an error and the command word
will fail to be sent.
Signed-off-by: Xianglai Li <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Commit: 7bd4eaa847fcdbc4505d9ab95dafa21791d8302a
https://github.com/qemu/qemu/commit/7bd4eaa847fcdbc4505d9ab95dafa21791d8302a
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/gdbstub.c
Log Message:
-----------
target/loongarch/gdbstub: Fix gdbstub incorrectly handling some registers
Write operation with R32 (orig_a0) and R34 (CSR_BADV) is discarded on
gdbstub implementation for LoongArch system. And return value should
be register size rather than 0, since it is used to calculate offset of
next register such as R33 (PC) in function handle_write_all_regs().
Cc: [email protected]
Fixes: ca61e75071c6 ("target/loongarch: Add gdb support.")
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 0262c8075e9dc62a53a4bd15ea8d92a4c9adf018
https://github.com/qemu/qemu/commit/0262c8075e9dc62a53a4bd15ea8d92a4c9adf018
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Correct maximum physical address in KVM mode
On 3A5000 system, the physical address space width for host is 48,
however 47 bit for KVM VM. For KVM VM, size of physical address space is
the same with that of virtual user space address.
Here modify physical address space width with 47 bit in KVM mode.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 3406b001e6e5992a8cc9b2442216de312b111c07
https://github.com/qemu/qemu/commit/3406b001e6e5992a8cc9b2442216de312b111c07
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Add post init function for kvm mode
Some features such as LBT and PMU are implemented in kvm mode,
With paravirt features in future, post init function is added
for kvm mode, so that property for these features will be created
in kvm post init function.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 780a65bd955dee4e58b2cefb3312e85731eace6e
https://github.com/qemu/qemu/commit/780a65bd955dee4e58b2cefb3312e85731eace6e
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Move kvm specified vCPU property to kvm directory
LBT and PMU feature is supported only in kvm mode, move property
about these two features to function kvm_loongarch_cpu_post_init().
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 5b0502c56412c115f9ff37fad56ff53674676a22
https://github.com/qemu/qemu/commit/5b0502c56412c115f9ff37fad56ff53674676a22
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/kvm/kvm.c
M target/loongarch/loongarch-qmp-cmds.c
Log Message:
-----------
target/loongarch: Add vCPU property for paravirt ipi feature
Property kvm-pv-ipi is added to paravirt ipi feature, it is specially
for kvm mode.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 620d9bd0022e011147c1133ef542c45a0da962e4
https://github.com/qemu/qemu/commit/620d9bd0022e011147c1133ef542c45a0da962e4
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Add paravirt ipi feature detection
Paravirt ipi feature is OnOffAuto type, feature detection is added
to check whether it is supported by KVM host.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 2698cc7c99b50cf4bb127c56e5c90f7f3cba6f0d
https://github.com/qemu/qemu/commit/2698cc7c99b50cf4bb127c56e5c90f7f3cba6f0d
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Enable paravirt ipi feature
The similiar with cpucfg register, paravirt ipi feature is set in
function kvm_arch_put_registers(). Instead the paravirt feature can
be enabled only once, it cannot be changed dynamically.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 610babce1ed83a0fd3af14f5195114d6c5338610
https://github.com/qemu/qemu/commit/610babce1ed83a0fd3af14f5195114d6c5338610
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/kvm/kvm.c
M target/loongarch/loongarch-qmp-cmds.c
Log Message:
-----------
target/loongarch: Add vCPU property for kvm steal time feature
Property kvm-steal-time is added for kvm steal time feature, it is
specially for kvm mode.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 954cc5c311cd4459ce16a3302ff8611d98473d7d
https://github.com/qemu/qemu/commit/954cc5c311cd4459ce16a3302ff8611d98473d7d
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/loongarch/cpu.h
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Add kvm steal time feature detection
Paravirt steal time feature is OnOffAuto type, feature detection is added
to check whether it is supported on KVM host.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: db369c11c90b35f3a6ab59ad78564aea5b30c3da
https://github.com/qemu/qemu/commit/db369c11c90b35f3a6ab59ad78564aea5b30c3da
Author: Bibo Mao <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
M target/loongarch/kvm/kvm.c
Log Message:
-----------
target/loongarch: Enable virtual extioi feature
Feature virtual extioi is loongArch virt machine property rather than
vCPU property in qemu side. However it is vCPU property in KVM kernel
side, here add loongArch virt machine property checking and enable virt
extioi feature when vCPU is created.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: bb09b7bfd37024381970744c71646e0239428897
https://github.com/qemu/qemu/commit/bb09b7bfd37024381970744c71646e0239428897
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/core/machine.c
M system/device_tree-stub.c
M system/device_tree.c
Log Message:
-----------
hw/core/machine.c: Make -machine dumpdtb=file.dtb with no DTB an error
Currently if the user requests via -machine dumpdtb=file.dtb that we
dump the DTB, but the machine doesn't have a DTB, we silently ignore
the option. This is confusing to users, and is a legacy of the old
board-specific implementation of the option, where if the execution
codepath didn't go via a call to qemu_fdt_dumpdtb() we would never
handle the option.
Now we handle the option in one place in machine.c, we can provide
the user with a useful message if they asked us to dump a DTB when
none exists. qmp_dumpdtb() already produces this error; remove the
logic in handle_machine_dumpdtb() that was there specifically to
avoid hitting it.
While we're here, beef up the error message a bit with a hint, and
make it consistent about "an FDT" rather than "a FDT". (In the
qmp_dumpdtb() case this needs an ERRP_GUARD to make
error_append_hint() work when the caller passes error_fatal.)
Note that the three places where we might report "doesn't have an
FDT" are hit in different situations:
(1) in handle_machine_dumpdtb(), if CONFIG_FDT is not set: this is
because the QEMU binary was built without libfdt at all. The
build system will not let you build with a machine type that
needs an FDT but no libfdt, so here we know both that the machine
doesn't use FDT and that QEMU doesn't have the support:
(2) in the device_tree-stub.c qmp_dumpdtb(): this is used when
we had libfdt at build time but the target architecture didn't
enable any machines which did "select DEVICE_TREE", so here we
know that the machine doesn't use FDT.
(3) in qmp_dumpdtb(), if current_machine->fdt is NULL all we know
is that this machine never set it. That might be because it doesn't
use FDT, or it might be because the user didn't pass an FDT
on the command line and the machine doesn't autogenerate an FDT.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2733
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 9b6e986e280f43e3df3baf7aae2069d599b5056c
https://github.com/qemu/qemu/commit/9b6e986e280f43e3df3baf7aae2069d599b5056c
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M target/m68k/cpu.c
Log Message:
-----------
fpu: Make targets specify floatx80 default Inf at runtime
Currently we hardcode at compile time whether the floatx80 default
Infinity value has the explicit integer bit set or not (x86 sets it;
m68k does not). To be able to compile softfloat once for all targets
we'd like to move this setting to runtime.
Define a new FloatX80Behaviour enum which is a set of flags that
define the target's floatx80 handling. Initially we define just one
flag, for whether the default Infinity has the Integer bit set or
not, but we will expand this in future commits to cover the other
floatx80 target specifics that we currently make compile-time
settings.
Define a new function floatx80_default_inf() which returns the
appropriate default Infinity value of the given sign, and use it in
the code that was previously directly using the compile-time constant
floatx80_infinity_{low,high} values when packing an infinity into a
floatx80.
Since floatx80 is highly unlikely to be supported in any new
architecture, and the existing code is generally written as "default
to like x87, with an ifdef for m68k", we make the default value for
the floatx80 behaviour flags be "what x87 does". This means we only
need to change the m68k target to specify the behaviour flags.
(Other users of floatx80 are the Arm NWFPE emulation, which is
obsolete and probably not actually doing the right thing anyway, and
the PPC xsrqpxp insn. Making the default be "like x87" avoids our
needing to review and test for behaviour changes there.)
We will clean up the remaining uses of the floatx80_infinity global
constant in subsequent commits.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: e456d4465b630ab2eed08611c6193f0a880e0ea3
https://github.com/qemu/qemu/commit/e456d4465b630ab2eed08611c6193f0a880e0ea3
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/m68k/softfloat.c
Log Message:
-----------
target/m68k: Avoid using floatx80_infinity global const
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so we can't
continue to use a single global whose value needs to be different
between targets.
Replace the direct uses of floatx80_infinity in target/m68k with
calls to the new floatx80_default_inf() function.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 165ce008d734bc0024dabdbfd1c41738bc5b834f
https://github.com/qemu/qemu/commit/165ce008d734bc0024dabdbfd1c41738bc5b834f
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
target/i386: Avoid using floatx80_infinity global const
The global const floatx80_infinity is (unlike all the other
float*_infinity values) target-specific, because whether the explicit
Integer bit is set or not varies between m68k and i386. We want to
be able to compile softfloat once for multiple targets, so we can't
continue to use a single global whose value needs to be different
between targets.
Replace the direct uses of floatx80_infinity in target/i386 with
calls to the new floatx80_default_inf() function. Note that because
we can ask the function for either a negative or positive infinity,
we don't need to change the sign of a positive infinity via
floatx80_chs() for the negative-Inf case.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 9ea6d1f141426a7da91f1c7ba3d693472f0550a4
https://github.com/qemu/qemu/commit/9ea6d1f141426a7da91f1c7ba3d693472f0550a4
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M include/fpu/softfloat.h
M target/i386/tcg/fpu_helper.c
M target/m68k/fpu_helper.c
Log Message:
-----------
fpu: Pass float_status to floatx80_is_infinity()
Unlike the other float formats, whether a floatx80 value is
considered to be an Infinity is target-dependent. (On x86 if the
explicit integer bit is clear this is a "pseudo-infinity" and not a
valid infinity; m68k does not care about the value of the integer
bit.)
Currently we select this target-specific logic at compile time with
an ifdef. We're going to want to do this at runtime, so change the
floatx80_is_infinity() function to take a float_status.
This commit doesn't change any logic; we'll do that in the
next commit.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 44eb32a9835fe2feb19503e93476eee602daee0b
https://github.com/qemu/qemu/commit/44eb32a9835fe2feb19503e93476eee602daee0b
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat-specialize.c.inc
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M target/m68k/cpu.c
Log Message:
-----------
fpu: Make targets specify whether floatx80 Inf can have Int bit clear
In Intel terminology, a floatx80 Infinity with the explicit integer
bit clear is a "pseudo-infinity"; for x86 these are not valid
infinity values. m68k is looser and does not care whether the
Integer bit is set or clear in an infinity.
Move this setting to runtime rather than using an ifdef in
floatx80_is_infinity().
Since this was the last use of the floatx80_infinity global constant,
we remove it and its definition here.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 765fe845ccb953b77b1b7e0557b13a7b760067b0
https://github.com/qemu/qemu/commit/765fe845ccb953b77b1b7e0557b13a7b760067b0
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat.c
M include/fpu/softfloat.h
M target/i386/tcg/fpu_helper.c
Log Message:
-----------
fpu: Pass float_status to floatx80_invalid_encoding()
The definition of which floatx80 encodings are invalid is
target-specific. Currently we handle this with an ifdef, but we
would like to defer this decision to runtime. In preparation, pass a
float_status argument to floatx80_invalid_encoding().
We will change the implementation from ifdef to looking at
the status argument in the following commit.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: a261d3e331ca06f4d92e689f2bee40d0a0cdee08
https://github.com/qemu/qemu/commit/a261d3e331ca06f4d92e689f2bee40d0a0cdee08
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
M target/m68k/cpu.c
Log Message:
-----------
fpu: Make floatx80 invalid encoding settable at runtime
Because floatx80 has an explicit integer bit, this permits some
odd encodings where the integer bit is not set correctly for the
floating point value type. In In Intel terminology the
categories are:
exp == 0, int = 0, mantissa == 0 : zeroes
exp == 0, int = 0, mantissa != 0 : denormals
exp == 0, int = 1 : pseudo-denormals
0 < exp < 0x7fff, int = 0 : unnormals
0 < exp < 0x7fff, int = 1 : normals
exp == 0x7fff, int = 0, mantissa == 0 : pseudo-infinities
exp == 0x7fff, int = 1, mantissa == 0 : infinities
exp == 0x7fff, int = 0, mantissa != 0 : pseudo-NaNs
exp == 0x7fff, int = 1, mantissa == 0 : NaNs
The usual IEEE cases of zero, denormal, normal, inf and NaN are always valid.
x87 permits as input also pseudo-denormals.
m68k permits all those and also pseudo-infinities, pseudo-NaNs and unnormals.
Currently we have an ifdef in floatx80_invalid_encoding() to select
the x86 vs m68k behaviour. Add new floatx80_behaviour flags to
select whether pseudo-NaN and unnormal are valid, and use these
(plus the existing pseudo_inf_valid flag) to decide whether these
encodings are invalid at runtime.
We leave pseudo-denormals as always-valid, since both x86 and m68k
accept them.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 1e75d8247ff27a307781230898fbcb8fbb9a8298
https://github.com/qemu/qemu/commit/1e75d8247ff27a307781230898fbcb8fbb9a8298
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat-parts.c.inc
M fpu/softfloat.c
M include/fpu/softfloat-types.h
M target/m68k/cpu.c
Log Message:
-----------
fpu: Move m68k_denormal fmt flag into floatx80_behaviour
Currently we compile-time set an 'm68k_denormal' flag in the FloatFmt
for floatx80 for m68k. This controls our handling of what the Intel
documentation calls a "pseudo-denormal": a value where the exponent
field is zero and the explicit integer bit is set.
For x86, the x87 FPU is supposed to accept a pseudo-denormal as
input, but never generate one on output. For m68k, these values are
permitted on input and may be produced on output.
Replace the flag in the FloatFmt with a flag indicating whether the
float format has an explicit bit (which will be true for floatx80 for
all targets, and false for every other float type). Then we can gate
the handling of these pseudo-denormals on the setting of a
floatx80_behaviour flag.
As far as I can see from the code we don't actually handle the
x86-mandated "accept on input but don't generate" behaviour, because
the handling in partsN(canonicalize) looked at fmt->m68k_denormal.
So I have added TODO comments to that effect.
This commit doesn't change any behaviour for any target.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 2e01cfea0735889a1e0481fc783d621779439572
https://github.com/qemu/qemu/commit/2e01cfea0735889a1e0481fc783d621779439572
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat-specialize.c.inc
Log Message:
-----------
fpu: Always decide no_signaling_nans() at runtime
Currently we have a compile-time shortcut where we
return false from no_signaling_nans() on everything except
Xtensa, because we know that's the only target that
might ever set status->no_signaling_nans.
Remove the ifdef, so we always look at the status flag;
this has no behavioural change, but will be necessary
if we want to build softfloat once for all targets.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 3abed4d0eace62910e90c206cb9d5741c6095b12
https://github.com/qemu/qemu/commit/3abed4d0eace62910e90c206cb9d5741c6095b12
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat-specialize.c.inc
M target/hppa/fpu_helper.c
M target/sh4/cpu.c
Log Message:
-----------
fpu: Always decide snan_bit_is_one() at runtime
Currently we have a compile-time shortcut where we return a hardcode
value from snan_bit_is_one() on everything except MIPS, because we
know that's the only target that needs to change
status->no_signaling_nans at runtime.
Remove the ifdef, so we always look at the status flag. This means
we must update the two targets (HPPA and SH4) that were previously
hardcoded to return true so that they set the status flag correctly.
This has no behavioural change, but will be necessary if we want to
build softfloat once for all targets.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: c5d4173fcf04f6de9b9bb0959d1fdfc08254381a
https://github.com/qemu/qemu/commit/c5d4173fcf04f6de9b9bb0959d1fdfc08254381a
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/softfloat.c
Log Message:
-----------
fpu: Don't compile-time disable hardfloat for PPC targets
We happen to know that for the PPC target the FP status flags (and in
particular float_flag_inexact) will always be cleared before a
floating point operation, and so can_use_fpu() will always return
false. So we speed things up a little by forcing QEMU_NO_HARDFLOAT
to true on that target.
We would like to build softfloat once for all targets; that means
removing target-specific ifdefs. Remove the check for TARGET_PPC;
this won't change behaviour because can_use_fpu() will see that
float_flag_inexact is clear and take the softfloat path anyway.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 5d3462b4cde8bedb33362dab0a3ae94d403899b0
https://github.com/qemu/qemu/commit/5d3462b4cde8bedb33362dab0a3ae94d403899b0
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M fpu/meson.build
M fpu/softfloat.c
Log Message:
-----------
fpu: Build only once
Now we have removed all the target-specifics from the softfloat code,
we can switch to building it once for the whole system rather than
once per target.
Signed-off-by: Peter Maydell <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Message-id: [email protected]
Commit: 1deb15c88ab3f1b0788b9e41b08217036eca3c91
https://github.com/qemu/qemu/commit/1deb15c88ab3f1b0788b9e41b08217036eca3c91
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/tcg/meson.build
A target/arm/tcg/vfp_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Move TCG-only VFP code into tcg/ subdir
Most of the target/arm/vfp_helper.c file is purely TCG helper code,
guarded by #ifdef CONFIG_TCG. Move this into a new file in
target/arm/tcg/.
This leaves only the code relating to getting and setting the
FPCR/FPSR/FPSCR in the original file. (Some of this also is
TCG-only, but that needs more careful disentangling.)
Having two vfp_helper.c files might seem a bit confusing,
but once we've finished moving all the helper code out
of the old file we are going to rename it to vfp_fpscr.c.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: e34cfba5e8d7bd631398a09d658dee40b1aef085
https://github.com/qemu/qemu/commit/e34cfba5e8d7bd631398a09d658dee40b1aef085
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/tcg/vfp_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Move FPSCR get/set helpers to tcg/vfp_helper.c
Currently the helper_vfp_get_fpscr() and helper_vfp_set_fpscr()
functions do the actual work of updating the FPSCR, and we have
wrappers vfp_get_fpscr() and vfp_set_fpscr() which we use for calls
from other QEMU C code.
Flip these around so that it is vfp_get_fpscr() and vfp_set_fpscr()
which do the actual work, and helper_vfp_get_fpscr() and
helper_vfp_set_fpscr() which are the wrappers; this allows us to move
them to tcg/vfp_helper.c.
Since this is the last HELPER() we had in arm/vfp_helper.c, we can
drop the include of helper-proto.h.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: b9d3dc45532e696f5ee566edd227a4f46bad0f35
https://github.com/qemu/qemu/commit/b9d3dc45532e696f5ee566edd227a4f46bad0f35
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/internals.h
M target/arm/tcg-stubs.c
M target/arm/tcg/vfp_helper.c
M target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Move softfloat specific FPCR/FPSR handling to tcg/
The softfloat (i.e. TCG) specific handling for the FPCR
and FPSR is abstracted behind five functions:
arm_set_default_fp_behaviours
arm_set_ah_fp_behaviours
vfp_get_fpsr_from_host
vfp_clear_float_status_exc_flags
vfp_set_fpsr_to_host
Currently we rely on the first two calling softfloat functions that
work even in a KVM-only compile because they're defined as inline in
the softfloat header file, and we provide stub versions of the last
three in arm/vfp_helper.c if CONFIG_TCG isn't defined.
Move the softfloat-specific versions of these functions to
tcg/vfp_helper.c, and provide the non-TCG stub versions in
tcg-stubs.c.
This lets us drop the softfloat header include and the last
set of CONFIG_TCG ifdefs from arm/vfp_helper.c.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: cb8bb8472ef83d8c8c6beac37d6db47ab3b68e18
https://github.com/qemu/qemu/commit/cb8bb8472ef83d8c8c6beac37d6db47ab3b68e18
Author: Peter Maydell <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/meson.build
A target/arm/vfp_fpscr.c
R target/arm/vfp_helper.c
Log Message:
-----------
target/arm: Rename vfp_helper.c to vfp_fpscr.c
The vfp_helper.c in the target/arm directory now only has
code for handling FPSCR/FPCR/FPSR in it, and no helper
functions. Rename it to vfp_fpscr.c; this helps keep it
distinct from tcg/vfp_helper.c.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: fd207677a83087454b8afef31651985a1df0d2dd
https://github.com/qemu/qemu/commit/fd207677a83087454b8afef31651985a1df0d2dd
Author: Joelle van Dyne <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: Disable SME feature
macOS 15.2's Hypervisor.framework exposes SME feature on M4 Macs.
However, QEMU's hvf accelerator code does not properly support it
yet, causing QEMU to fail to start when hvf accelerator is used on
these systems, with the error message:
qemu-aarch64-softmmu: cannot disable sme4224
All SME vector lengths are disabled.
With SME enabled, at least one vector length must be enabled.
Ideally we would have SME support on these hosts; however, until that
point, we must suppress the SME feature in the ID registers, so that
users can at least run non-SME guests.
Cc: [email protected]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2665
Signed-off-by: Joelle van Dyne <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: expanded commit message, comment]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 12c365315ab25d364cff24dfeea8d7ff1e752b9f
https://github.com/qemu/qemu/commit/12c365315ab25d364cff24dfeea8d7ff1e752b9f
Author: Joelle van Dyne <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M target/arm/hvf/hvf.c
Log Message:
-----------
target/arm/hvf: sign extend the data for a load operation when SSE=1
In the syndrome value for a data abort, bit 21 is SSE, which is
set to indicate that the abort was on a sign-extending load. When
we handle the data abort from the guest via address_space_read(),
we forgot to handle this and so would return the wrong value if
the guest did a sign-extending load to an MMIO region. Add the
sign-extension of the returned data.
Cc: [email protected]
Signed-off-by: Joelle van Dyne <[email protected]>
Message-id: [email protected]
[PMM: Drop an unnecessary check on 'len'; expand commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2cac20cbf7b01e9a4e404db2ff9bee09ee26f315
https://github.com/qemu/qemu/commit/2cac20cbf7b01e9a4e404db2ff9bee09ee26f315
Author: Pierrick Bouvier <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/misc/npcm_clk.c
Log Message:
-----------
hw/misc/npcm_clk: fix buffer-overflow
Regression introduced by cf76c4
(hw/misc: Add nr_regs and cold_reset_values to NPCM CLK)
cold_reset_values has a different size, depending on device used
(NPCM7xx vs NPCM8xx). However, s->regs has a fixed size, which matches
NPCM8xx. Thus, when initializing a NPCM7xx, we go past cold_reset_values
ending.
Report by asan:
==2066==ERROR: AddressSanitizer: global-buffer-overflow on address
0x55d68a3e97f0 at pc 0x7fcaf2b2d14b bp 0x7ffff0cc3890 sp 0x7ffff0cc3040
READ of size 196 at 0x55d68a3e97f0 thread T0
#0 0x7fcaf2b2d14a in __interceptor_memcpy
../../../../src/libsanitizer/sanitizer_common/sanitizer_common_interceptors.inc:827
#1 0x55d688447e0d in memcpy
/usr/include/x86_64-linux-gnu/bits/string_fortified.h:29
#2 0x55d688447e0d in npcm_clk_enter_reset ../hw/misc/npcm_clk.c:968
#3 0x55d6899b7213 in resettable_phase_enter ../hw/core/resettable.c:136
#4 0x55d6899a1ef7 in bus_reset_child_foreach ../hw/core/bus.c:97
#5 0x55d6899b717d in resettable_child_foreach ../hw/core/resettable.c:92
#6 0x55d6899b717d in resettable_phase_enter ../hw/core/resettable.c:129
#7 0x55d6899b4ead in resettable_container_child_foreach
../hw/core/resetcontainer.c:54
#8 0x55d6899b717d in resettable_child_foreach ../hw/core/resettable.c:92
#9 0x55d6899b717d in resettable_phase_enter ../hw/core/resettable.c:129
#10 0x55d6899b7bfa in resettable_assert_reset ../hw/core/resettable.c:55
#11 0x55d6899b8666 in resettable_reset ../hw/core/resettable.c:45
#12 0x55d688d15cd2 in qemu_system_reset ../system/runstate.c:527
#13 0x55d687fc5edd in qdev_machine_creation_done ../hw/core/machine.c:1738
#14 0x55d688d209bd in qemu_machine_creation_done ../system/vl.c:2779
#15 0x55d688d209bd in qmp_x_exit_preconfig ../system/vl.c:2807
#16 0x55d688d281fb in qemu_init ../system/vl.c:3838
#17 0x55d687ceab12 in main ../system/main.c:68
#18 0x7fcaef006249 (/lib/x86_64-linux-gnu/libc.so.6+0x27249)
#19 0x7fcaef006304 in __libc_start_main
(/lib/x86_64-linux-gnu/libc.so.6+0x27304)
#20 0x55d687cf0010 in _start
(/home/runner/work/qemu-ci/qemu-ci/build/qemu-system-arm+0x371c010)
0x55d68a3e97f0 is located 0 bytes to the right of global variable
'npcm7xx_cold_reset_values' defined in '../hw/misc/npcm_clk.c:134:23'
(0x55d68a3e9780) of size 112
Impacted tests:
Summary of Failures:
check:
2/747 qemu:qtest+qtest-aarch64 / qtest-aarch64/qom-test
ERROR 9.28s killed by signal 6 SIGABRT
4/747 qemu:qtest+qtest-arm / qtest-arm/qom-test
ERROR 7.82s killed by signal 6 SIGABRT
32/747 qemu:qtest+qtest-aarch64 / qtest-aarch64/device-introspect-test
ERROR 10.91s killed by signal 6 SIGABRT
35/747 qemu:qtest+qtest-arm / qtest-arm/device-introspect-test
ERROR 11.33s killed by signal 6 SIGABRT
114/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_pwm-test
ERROR 0.98s killed by signal 6 SIGABRT
115/747 qemu:qtest+qtest-aarch64 / qtest-aarch64/test-hmp
ERROR 2.95s killed by signal 6 SIGABRT
117/747 qemu:qtest+qtest-arm / qtest-arm/test-hmp
ERROR 2.54s killed by signal 6 SIGABRT
151/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_watchdog_timer-test
ERROR 0.96s killed by signal 6 SIGABRT
247/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_adc-test
ERROR 0.96s killed by signal 6 SIGABRT
248/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_gpio-test
ERROR 1.05s killed by signal 6 SIGABRT
249/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_rng-test
ERROR 0.97s killed by signal 6 SIGABRT
250/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_sdhci-test
ERROR 0.97s killed by signal 6 SIGABRT
251/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_smbus-test
ERROR 0.89s killed by signal 6 SIGABRT
252/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_timer-test
ERROR 1.09s killed by signal 6 SIGABRT
253/747 qemu:qtest+qtest-arm / qtest-arm/npcm_gmac-test
ERROR 1.12s killed by signal 6 SIGABRT
255/747 qemu:qtest+qtest-arm / qtest-arm/npcm7xx_emc-test
ERROR 1.05s killed by signal 6 SIGABRT
check-functional:
22/203 qemu:func-thorough+func-arm-thorough+thorough / func-arm-arm_quanta_gsj
ERROR 0.79s exit status 1
38/203 qemu:func-quick+func-aarch64 / func-aarch64-migration
ERROR 1.97s exit status 1
45/203 qemu:func-quick+func-arm / func-arm-migration
ERROR 1.90s exit status 1
Fixes: cf76c4e174e1 ("hw/misc: Add nr_regs and cold_reset_values to NPCM CLK")
Signed-off-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Hao Wu <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: b513766ee968dbfca31034b185f0a0fcf99f4269
https://github.com/qemu/qemu/commit/b513766ee968dbfca31034b185f0a0fcf99f4269
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/usb/hcd-dwc3.c
M include/hw/usb/hcd-dwc3.h
Log Message:
-----------
hw/usb/hcd-dwc3: Align global registers size with Linux
While at it add missing GUSB2RHBCTL register as found in i.MX 8M Plus reference
manual.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: faa2150a527b1919646316dba268b71ced8762a6
https://github.com/qemu/qemu/commit/faa2150a527b1919646316dba268b71ced8762a6
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/pci-host/designware.c
M include/hw/pci-host/designware.h
Log Message:
-----------
hw/pci-host/designware: Prevent device attachment on internal PCIe root bus
On the real device, the PCIe root bus is only connected to a PCIe bridge and
does not allow for direct attachment of devices. Doing so in QEMU results in no
PCI devices being detected by Linux. Instead, PCI devices should plug into the
secondary PCIe bus spawned by the internal PCIe bridge.
Unfortunately, QEMU defaults to plugging devices into the PCIe root bus. To work
around this, every PCI device created on the command line needs an extra
`bus=dw-pcie` option which is error prone. Fix that by marking the PCIe root bus
as full which makes QEMU decend into the child PCIe bus.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0f520f0a9d9516fb3563a9b69c820ac73d2017aa
https://github.com/qemu/qemu/commit/0f520f0a9d9516fb3563a9b69c820ac73d2017aa
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/gpio/Kconfig
M hw/misc/Kconfig
Log Message:
-----------
hw/gpio/pca955*: Move Kconfig switches next to implementations
The move of the Kconfig bits to hw/gpio is fixing a bug in 6328d8ffa6cb9d
("misc/pca955*: Move models under hw/gpio"), which moved the code but forgot to
move the Kconfig sections.
Fixes: 6328d8ffa6cb9d "misc/pca955*: Move models under hw/gpio"
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: a4eefc69b23713c4e5981d9d91a6e15dfd4496fe
https://github.com/qemu/qemu/commit/a4eefc69b23713c4e5981d9d91a6e15dfd4496fe
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M MAINTAINERS
A docs/system/arm/imx8mp-evk.rst
M docs/system/target-arm.rst
M hw/arm/Kconfig
A hw/arm/fsl-imx8mp.c
A hw/arm/imx8mp-evk.c
M hw/arm/meson.build
A include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm: Add i.MX 8M Plus EVK board
As a first step, implement the bare minimum: CPUs, RAM, interrupt controller,
serial. All other devices of the A53 memory map are represented as
TYPE_UNIMPLEMENTED_DEVICE, i.e. the whole memory map is provided. This allows
for running Linux without it crashing due to invalid memory accesses.
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: drop 'static const' from serial_table[] definition to avoid
compile failure on GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 86c2dff9552ad5a9b2febf329a2dbd2620bc2145
https://github.com/qemu/qemu/commit/86c2dff9552ad5a9b2febf329a2dbd2620bc2145
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M MAINTAINERS
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M hw/misc/Kconfig
A hw/misc/imx8mp_analog.c
A hw/misc/imx8mp_ccm.c
M hw/misc/meson.build
M include/hw/arm/fsl-imx8mp.h
A include/hw/misc/imx8mp_analog.h
A include/hw/misc/imx8mp_ccm.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Implement clock tree
Fixes quite a few stack traces during the Linux boot process. Also provides the
clocks for devices added later, e.g. enet1.
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 487967bed65083db33561edc1255ced422bfbff5
https://github.com/qemu/qemu/commit/487967bed65083db33561edc1255ced422bfbff5
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add SNVS
SNVS contains an RTC which allows Linux to deal correctly with time. This is
particularly useful when handling persistent storage which will be done in the
next patch.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a81193c3e9a8220862120d8d4114191f3899f4b3
https://github.com/qemu/qemu/commit/a81193c3e9a8220862120d8d4114191f3899f4b3
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M hw/arm/imx8mp-evk.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add USDHC storage controllers
The USDHC emulation allows for running real-world images such as those generated
by Buildroot. Convert the board documentation accordingly instead of running a
Linux kernel with ephemeral storage.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop 'static const' from usdhc_table[] for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: fd1deb5301f89eb86c0eecadb670beb98aa74ac5
https://github.com/qemu/qemu/commit/fd1deb5301f89eb86c0eecadb670beb98aa74ac5
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M MAINTAINERS
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M hw/pci-host/Kconfig
A hw/pci-host/fsl_imx8m_phy.c
M hw/pci-host/meson.build
M include/hw/arm/fsl-imx8mp.h
A include/hw/pci-host/fsl_imx8m_phy.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add PCIe support
Linux checks for the PLLs in the PHY to be locked, so implement a model
emulating that.
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: a17c1d932ec6ae1a3364eaf34c0660f01f806267
https://github.com/qemu/qemu/commit/a17c1d932ec6ae1a3364eaf34c0660f01f806267
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add GPIO controllers
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop static const from gpio_table for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 764f18afb2b749a9dcfd37bac5709e7a7bcd2589
https://github.com/qemu/qemu/commit/764f18afb2b749a9dcfd37bac5709e7a7bcd2589
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add I2C controllers
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop static const from i2c_table for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 06908a84f036d7cefb834f8d67cf8b80a1791838
https://github.com/qemu/qemu/commit/06908a84f036d7cefb834f8d67cf8b80a1791838
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add SPI controllers
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop static const from spi_table for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1ac21eb8fbb0297716a6c525e91196a247302b2b
https://github.com/qemu/qemu/commit/1ac21eb8fbb0297716a6c525e91196a247302b2b
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add watchdog support
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop static const from wdog_table for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f8b26121762c17af9869b0ec7ccbda6df4ea37f8
https://github.com/qemu/qemu/commit/f8b26121762c17af9869b0ec7ccbda6df4ea37f8
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M hw/timer/imx_gpt.c
M include/hw/arm/fsl-imx8mp.h
M include/hw/timer/imx_gpt.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Implement general purpose timers
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop static const from gpt_attrs for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0c105b261551a9b9fed086a7b9ecd0b6d6063bc4
https://github.com/qemu/qemu/commit/0c105b261551a9b9fed086a7b9ecd0b6d6063bc4
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M hw/arm/imx8mp-evk.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add Ethernet controller
The i.MX 8M Plus SoC actually has two ethernet controllers, the usual ENET one
and a Designware one. There is no device model for the latter, so only add the
ENET one.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4226c39fea1490060163339ae45500bda1b1be05
https://github.com/qemu/qemu/commit/4226c39fea1490060163339ae45500bda1b1be05
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M docs/system/arm/imx8mp-evk.rst
M hw/arm/Kconfig
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add USB support
Split the USB MMIO regions to better keep track of the implemented vs.
unimplemented regions.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
[PMM: drop "static const" from usb_table for GCC 7.5]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1aaf3478684ff1cd02d1b36c32a00bfac9a5dbd5
https://github.com/qemu/qemu/commit/1aaf3478684ff1cd02d1b36c32a00bfac9a5dbd5
Author: Bernhard Beschow <[email protected]>
Date: 2025-02-25 (Tue, 25 Feb 2025)
Changed paths:
M hw/arm/fsl-imx8mp.c
M include/hw/arm/fsl-imx8mp.h
Log Message:
-----------
hw/arm/fsl-imx8mp: Add on-chip RAM
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 50d38b8921837827ea397d4b20c8bc5efe186e53
https://github.com/qemu/qemu/commit/50d38b8921837827ea397d4b20c8bc5efe186e53
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
M target/loongarch/cpu.c
M target/loongarch/cpu.h
M target/loongarch/gdbstub.c
M target/loongarch/kvm/kvm.c
M target/loongarch/loongarch-qmp-cmds.c
Log Message:
-----------
Merge tag 'pull-loongarch-20250225' of https://gitlab.com/bibo-mao/qemu into
staging
loongarch queue
# -----BEGIN PGP SIGNATURE-----
#
# iHUEABYKAB0WIQQNhkKjomWfgLCz0aQfewwSUazn0QUCZ7156AAKCRAfewwSUazn
# 0T2AAQDW4zr8ECab5FH+udeCtGOv2I6gtTT8CwjwhCdHNzsAAgEAxi0JJOjTIMrK
# z657Q4MTeKbTyzi48niXBbI9hKvyhQM=
# =g4Wx
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 25 Feb 2025 16:06:00 HKT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20250225' of https://gitlab.com/bibo-mao/qemu:
target/loongarch: Enable virtual extioi feature
target/loongarch: Add kvm steal time feature detection
target/loongarch: Add vCPU property for kvm steal time feature
target/loongarch: Enable paravirt ipi feature
target/loongarch: Add paravirt ipi feature detection
target/loongarch: Add vCPU property for paravirt ipi feature
target/loongarch: Move kvm specified vCPU property to kvm directory
target/loongarch: Add post init function for kvm mode
target/loongarch: Correct maximum physical address in KVM mode
target/loongarch/gdbstub: Fix gdbstub incorrectly handling some registers
target/loongarch: fix vcpu reset command word issue
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: f1c71206ba2634947d05edb198470248d54f404d
https://github.com/qemu/qemu/commit/f1c71206ba2634947d05edb198470248d54f404d
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-02-26 (Wed, 26 Feb 2025)
Changed paths:
M MAINTAINERS
A docs/system/arm/imx8mp-evk.rst
M docs/system/arm/virt.rst
M docs/system/target-arm.rst
M fpu/meson.build
M fpu/softfloat-parts.c.inc
M fpu/softfloat-specialize.c.inc
M fpu/softfloat.c
M hw/arm/Kconfig
M hw/arm/boot.c
A hw/arm/fsl-imx8mp.c
A hw/arm/imx8mp-evk.c
M hw/arm/meson.build
M hw/arm/smmuv3.c
M hw/arm/virt.c
M hw/core/loader-fit.c
M hw/core/machine.c
M hw/gpio/Kconfig
M hw/loongarch/virt-fdt-build.c
M hw/mips/boston.c
M hw/misc/Kconfig
A hw/misc/imx8mp_analog.c
A hw/misc/imx8mp_ccm.c
M hw/misc/meson.build
M hw/misc/npcm_clk.c
M hw/openrisc/boot.c
M hw/openrisc/openrisc_sim.c
M hw/openrisc/virt.c
M hw/pci-host/Kconfig
M hw/pci-host/designware.c
A hw/pci-host/fsl_imx8m_phy.c
M hw/pci-host/meson.build
M hw/ppc/e500.c
M hw/ppc/pegasos2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M hw/riscv/boot.c
M hw/timer/imx_gpt.c
M hw/usb/hcd-dwc3.c
M include/fpu/softfloat-helpers.h
M include/fpu/softfloat-types.h
M include/fpu/softfloat.h
A include/hw/arm/fsl-imx8mp.h
M include/hw/loader-fit.h
A include/hw/misc/imx8mp_analog.h
A include/hw/misc/imx8mp_ccm.h
M include/hw/openrisc/boot.h
M include/hw/pci-host/designware.h
A include/hw/pci-host/fsl_imx8m_phy.h
M include/hw/timer/imx_gpt.h
M include/hw/usb/hcd-dwc3.h
M include/system/device_tree.h
M monitor/hmp-cmds.c
M system/device_tree-stub.c
M system/device_tree.c
M target/arm/hvf/hvf.c
M target/arm/internals.h
M target/arm/meson.build
M target/arm/tcg-stubs.c
M target/arm/tcg/meson.build
A target/arm/tcg/vfp_helper.c
A target/arm/vfp_fpscr.c
R target/arm/vfp_helper.c
M target/hppa/fpu_helper.c
M target/i386/tcg/fpu_helper.c
M target/m68k/cpu.c
M target/m68k/fpu_helper.c
M target/m68k/softfloat.c
M target/sh4/cpu.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250225' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/smmuv3: Fill u.f_cd_fetch.addr for SMMU_EVT_F_CD_FETCH
* hw/arm/virt: Support larger highmem MMIO regions
* machine: Centralize -machine dumpdtb option handling and report
attempt to dump nonexistent DTB as an error
* fpu: remove target ifdefs and build it only once
* target/arm: Refactor to move TCG-only vfp_helper code into tcg/
* target/arm/hvf: Disable SME feature
* target/arm/hvf: sign extend the data for a load operation when SSE=1
* hw/misc/npcm_clk: fix buffer-overflow
* hw/arm: Add i.MX 8M Plus EVK board ("imx8mp-evk")
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAme+BaQZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3kG0EACuWqAhqYdn2muu1Rc3WQMh
# uMOdb/f7oaqbCpeBEdV1dazWfZJQ1Zk05J31t+tdoYowqM7nS55Vw9zrSntoC6Ll
# IYRzBmGWE+FnsODKhA0wx/lQO08GeMTrkHoGM72hiwIjbuC/Nps9aOQ2GH6WOCjN
# TACXF1dYNpoy+H979yIwGMWH1SSgn1fS+9zw3LsKCGtbnt7g80DyWpb6qlfKPJ78
# KHmpth//sCPbu6UtsFKTBlIb0dYtAWTnRoS834WBq9bw51OPh81WoApSBkjV479z
# kTcLyaJnoTKsPnz+6A/z3Fm/qi4aATk4/eCCT2ry3Oyi3ffafSlBf/KiFqAZ0Fue
# vq6/b/wsVTdyjnkcptmCHJ+6qEhPshNi3F4hu8YOFQsx+6zFR7NUkZrNt/IQIhZB
# DOcjtMFymg/duEbRW9RdLeVC3Ds2qVuxnzEbLmNJntBp+jkhm5QkWf6ZEJ6iviOf
# tSP+SLOFyCT71BdQSIMhLJHS9UPJ3vzgGkN54YCLDYg24aNCMSe0nqLFMxfchQJm
# njn1BdyX4pDibXv6tdDJdtOv3sLgvVaZZKEGlTGtNx8kq8qmXnzIJl6iQSBTrmD5
# qMb4NxaYG6hpzSQOV+XxLQ1BdLNj2qXs90EU1Jqfp378sOdl6Oyx5po5NIcyp36o
# g+GsbLqphJL4DkosoH8eFA==
# =MBWK
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed 26 Feb 2025 02:02:12 HKT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250225' of
https://git.linaro.org/people/pmaydell/qemu-arm: (43 commits)
hw/arm/fsl-imx8mp: Add on-chip RAM
hw/arm/fsl-imx8mp: Add USB support
hw/arm/fsl-imx8mp: Add Ethernet controller
hw/arm/fsl-imx8mp: Implement general purpose timers
hw/arm/fsl-imx8mp: Add watchdog support
hw/arm/fsl-imx8mp: Add SPI controllers
hw/arm/fsl-imx8mp: Add I2C controllers
hw/arm/fsl-imx8mp: Add GPIO controllers
hw/arm/fsl-imx8mp: Add PCIe support
hw/arm/fsl-imx8mp: Add USDHC storage controllers
hw/arm/fsl-imx8mp: Add SNVS
hw/arm/fsl-imx8mp: Implement clock tree
hw/arm: Add i.MX 8M Plus EVK board
hw/gpio/pca955*: Move Kconfig switches next to implementations
hw/pci-host/designware: Prevent device attachment on internal PCIe root bus
hw/usb/hcd-dwc3: Align global registers size with Linux
hw/misc/npcm_clk: fix buffer-overflow
target/arm/hvf: sign extend the data for a load operation when SSE=1
target/arm/hvf: Disable SME feature
target/arm: Rename vfp_helper.c to vfp_fpscr.c
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/b69801dd6b1e...f1c71206ba26
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