Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 6c5a1467f8d0a9e840c8aa193bc110cc76ee80e8
https://github.com/qemu/qemu/commit/6c5a1467f8d0a9e840c8aa193bc110cc76ee80e8
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M tests/functional/qemu_test/testcase.py
Log Message:
-----------
tests/functional: remove unused 'bin_prefix' variable
This was copied over from avocado but has not been used in the new
functional tests.
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 8188356a260ca0201c42d128d8fa86f40160b513
https://github.com/qemu/qemu/commit/8188356a260ca0201c42d128d8fa86f40160b513
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M docs/devel/testing/functional.rst
M tests/functional/qemu_test/testcase.py
Log Message:
-----------
tests/functional: set 'qemu_bin' as an object level field
The 'qemu_bin' field is currently set on the class, despite being
accessed as if it were an object instance field with 'self.qemu_bin'.
This is no obvious need to have it as a class field, so move it into
the object instance.
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 188f71929520940048ec5ba85ea30588e0566e6e
https://github.com/qemu/qemu/commit/188f71929520940048ec5ba85ea30588e0566e6e
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M tests/functional/test_ppc64_tuxrun.py
Log Message:
-----------
tests/functional: reduce tuxrun maxmem to work on 32-bit hosts
maxmem=4G is too large to address on 32-bit hosts, so reduce it
to 2G since the tuxrun tests don't actually need such an elevated
memory limit.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 089fa3d7302b38285ae146de8bbe5cf6ecc04f34
https://github.com/qemu/qemu/commit/089fa3d7302b38285ae146de8bbe5cf6ecc04f34
Author: Song Gao <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: fix 'make check-functional' failed
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0,just check the tlb_ps skip
the function and write a log.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-Id: <[email protected]>
Commit: d882c284a3d4472d827e49a7357198b611900b08
https://github.com/qemu/qemu/commit/d882c284a3d4472d827e49a7357198b611900b08
Author: Song Gao <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/helper.h
M target/loongarch/internals.h
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: check tlb_ps
For LoongArch th min tlb_ps is 12(4KB), for TLB code,
the tlb_ps may be 0,this may case UndefinedBehavior
Add a check-tlb_ps fuction to check tlb_ps,
to make sure the tlb_ps is avalablie. we check tlb_ps
when get the tlb_ps from tlb->misc or CSR bits.
1. cpu reset
set CSR_PWCL.PTBASE and CSR_STLBPS.PS bits a default value
from CSR_PRCFG2;
2. tlb instructions.
some tlb instructions get the tlb_ps from tlb->misc but the
value may has been initialized to 0. we need just check the tlb_ps
skip the function and write a guest log.
3. csrwr instructions.
to make sure CSR_PWCL.PTBASE and CSR_STLBPS.PS bits are avalable,
cheke theses bits and set a default value from CSR_PRCFG2.
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-Id: <[email protected]>
Commit: 42ea7f782a32df4ac58e7d9d73e736def3057ef7
https://github.com/qemu/qemu/commit/42ea7f782a32df4ac58e7d9d73e736def3057ef7
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/test_mem_addr_space.py
Log Message:
-----------
tests/functional: skip memaddr tests on 32-bit builds
If the QEMU binary was built for a 32-bit ELF target we cannot run the
memory address space tests as they all require ability to address more
RAM that can be represented on 32-bit.
We can't use a decorator to skip the tests as we need setUp() to run to
pick the QEMU binary, thus we must call a method at the start of each
test to check and skip it. The functional result is effectively the
same as using a decorator, just less pretty. This code will go away when
32-bit hosts are full dropped from QEMU.
The code allows any non-ELF target since all macOS versions supported
at 64-bit only and we already dropped support for 32-bit Windows.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
[thuth: Add missing byteorder='little' to from_bytes()]
Signed-off-by: Thomas Huth <[email protected]>
Commit: 5ad2c8f357a76bbc502452c60076a4b36708f46a
https://github.com/qemu/qemu/commit/5ad2c8f357a76bbc502452c60076a4b36708f46a
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/qemu_test/tuxruntest.py
Log Message:
-----------
tests/functional: drop unused 'get_tag' method
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 981395889201f556c37e18c7a896d2555ffa4373
https://github.com/qemu/qemu/commit/981395889201f556c37e18c7a896d2555ffa4373
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/qemu_test/uncompress.py
Log Message:
-----------
tests/functional: stop output from zstd command when uncompressing
The zstd command will print incremental decompression progress to stderr
when running. Fortunately it is not on stdout as that would confuse the
TAP parsing, but we should still not have this printed. By switching
from 'check_call' to 'run' with the check=True and capture_output=True
we'll get the desired silence on success, and on failure the raised
exception will automatically include stdout/stderr data for diagnosis
purposes.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 2c92ecb678cddf4bf3ced98f94acd2f3691c21bc
https://github.com/qemu/qemu/commit/2c92ecb678cddf4bf3ced98f94acd2f3691c21bc
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/qemu_test/linuxkernel.py
M tests/functional/test_intel_iommu.py
Log Message:
-----------
tests/functional: Move the code for testing HTTP downloads to a common
function
We are going to use this code in other tests, too, so let's move it
to the qemu_test module to be able to re-use it more easily.
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 7b7f98efa7628a58fae594d3aa51b3c8a10293b3
https://github.com/qemu/qemu/commit/7b7f98efa7628a58fae594d3aa51b3c8a10293b3
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/test_mips_malta.py
Log Message:
-----------
tests/functional/test_mips_malta: Add a network test via the pcnet NIC
The kernel has a driver for the pcnet NIC included, and the initrd has
a "tftp" command, so we can test a simple network transfer here, too.
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: a31001b1c807cc59b2a9aa99845783cb40a27d0c
https://github.com/qemu/qemu/commit/a31001b1c807cc59b2a9aa99845783cb40a27d0c
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/meson.build
Log Message:
-----------
tests/functional: Increase the timeout of the mips64el_replay test
We run the gitlab-CI with the untrusted tests enabled, and
the test_replay_mips64el_malta_5KEc_cpio subtest is rather slow,
so this already hit the standard 90 seconds timeout in the CI.
Increase the timeout for more headroom.
Reported-by: Stefan Hajnoczi <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Stefan Hajnoczi <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 842721581fdbed45fa4738d02df8d28b1eaf28dd
https://github.com/qemu/qemu/commit/842721581fdbed45fa4738d02df8d28b1eaf28dd
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/test_virtio_balloon.py
Log Message:
-----------
tests/functional: fix race in virtio balloon test
There are two race conditions in the recently added virtio balloon
test
* The /dev/vda device node is not ready
* The virtio-balloon driver has not issued the first stats refresh
To fix the former, monitor dmesg for a line about 'vda'.
To fix the latter, retry the stats query until seeing fresh data.
Adding 'quiet' to the kernel command line reduces serial output
which otherwise slows boot, making it less likely to hit the former
race too.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
[thuth: Break long line to avoid checkpatch error]
Signed-off-by: Thomas Huth <[email protected]>
Commit: 4dc11ee468df3ffdaa312a16b4ded3378133bb39
https://github.com/qemu/qemu/commit/4dc11ee468df3ffdaa312a16b4ded3378133bb39
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M tests/functional/test_virtio_balloon.py
Log Message:
-----------
tests/functional/test_virtio_balloon: Only use KVM for running this test
The virtio_balloon test is currently hanging for unknown reasons
when being run on the shared gitlab CI runners (which don't provide
KVM, thus it's running in TCG mode there). All other functional tests
that use the same asset (the Fedora 31 kernel) have already been
marked to work only with KVM in the past, so those other tests are
skipped on the shared gitlab CI runners. As long as the problem isn't
fully understood and fixed, let's do the same with the virtio_balloon
test to avoid that the CI is failing here.
Message-ID: <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: e7f091d0c1750a57fd7ab39db50d1aae1c7647b0
https://github.com/qemu/qemu/commit/e7f091d0c1750a57fd7ab39db50d1aae1c7647b0
Author: Aditya Gupta <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M docs/devel/testing/functional.rst
Log Message:
-----------
doc: add missing 'Asset' type in function test doc
Seems 'Asset' got missed in the documentation by mistake.
Also fix the one spellcheck issue pointed by spellcheck
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 9cbff6f29ee099e7cb331802a1bf9b179c4c3934
https://github.com/qemu/qemu/commit/9cbff6f29ee099e7cb331802a1bf9b179c4c3934
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add docs/devel/testing/functional.rst to the functional section
Add an entry for docs/devel/testing/functional.rst to get notified
on patches that change this file.
Message-ID: <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: dfcee1ea4c52ac60e0a06221eafb7b6253eb10c3
https://github.com/qemu/qemu/commit/dfcee1ea4c52ac60e0a06221eafb7b6253eb10c3
Author: Matthew Rosato <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/s390x/s390-pci-bus.c
M hw/s390x/s390-pci-inst.c
M hw/s390x/s390-pci-vfio.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/s390-pci-bus.h
Log Message:
-----------
s390x/pci: add support for guests that request direct mapping
When receiving a guest mpcifc(4) or mpcifc(6) instruction without the T
bit set, treat this as a request to perform direct mapping instead of
address translation. In order to facilitate this, pin the entirety of
guest memory into the host iommu.
Pinning for the direct mapping case is handled via vfio and its memory
listener. Additionally, ram discard settings are inherited from vfio:
coordinated discards (e.g. virtio-mem) are allowed while uncoordinated
discards (e.g. virtio-balloon) are disabled.
Subsequent guest DMA operations are all expected to be of the format
guest_phys+sdma, allowing them to be used as lookup into the host
iommu table.
Signed-off-by: Matthew Rosato <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: d9b5dfc7122559e5b5959ecf534788b90c3dd102
https://github.com/qemu/qemu/commit/d9b5dfc7122559e5b5959ecf534788b90c3dd102
Author: Matthew Rosato <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/s390x/s390-pci-vfio.c
M include/hw/s390x/s390-pci-clp.h
Log Message:
-----------
s390x/pci: indicate QEMU supports relaxed translation for passthrough
Specifying this bit in the guest CLP response indicates that the guest
can optionally choose to skip translation and instead use
identity-mapped operations.
Tested-by: Niklas Schnelle <[email protected]>
Reviewed-by: Niklas Schnelle <[email protected]>
Signed-off-by: Matthew Rosato <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: a674db604db3fc4ef5267243dc991852f1f1bebc
https://github.com/qemu/qemu/commit/a674db604db3fc4ef5267243dc991852f1f1bebc
Author: JianChunfu <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu-common: Remove the repeated ttb field
SMMUTransCfg->ttb is never used in QEMU, TT base address
can be accessed by SMMUTransCfg->tt[i]->ttb.
Signed-off-by: JianChunfu <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3b2e22c0bbe2ce07123d93961d52f17644562cd7
https://github.com/qemu/qemu/commit/3b2e22c0bbe2ce07123d93961d52f17644562cd7
Author: Patrick Venture <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/gpio/npcm7xx_gpio.c
Log Message:
-----------
hw/gpio: npcm7xx: fixup out-of-bounds access
The reg isn't validated to be a possible register before
it's dereferenced for one case. The mmio space registered
for the gpio device is 4KiB but there aren't that many
registers in the struct.
Cc: [email protected]
Fixes: 526dbbe0874 ("hw/gpio: Add GPIO model for Nuvoton NPCM7xx")
Signed-off-by: Patrick Venture <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5f6b9b0564b69bd9548860419a70e79579d64aeb
https://github.com/qemu/qemu/commit/5f6b9b0564b69bd9548860419a70e79579d64aeb
Author: Thomas Huth <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M MAINTAINERS
M tests/functional/test_arm_sx1.py
Log Message:
-----------
tests/functional/test_arm_sx1: Check whether the serial console is working
The kernel that is used in the sx1 test prints the usual Linux log
onto the serial console, but this test currently ignores it. To
make sure that the serial device is working properly, let's check
for some strings in the output here.
While we're at it, also add the test to the corresponding section
in the MAINTAINERS file.
Signed-off-by: Thomas Huth <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: db6c2192839ee0282d38f6f6666a87e0629fcd13
https://github.com/qemu/qemu/commit/db6c2192839ee0282d38f6f6666a87e0629fcd13
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Apply correct timer offset when calculating deadlines
When we are calculating timer deadlines, the correct definition of
whether or not to apply an offset to the physical count is described
in the Arm ARM DDI4087 rev L.a section D12.2.4.1. This is different
from when the offset should be applied for a direct read of the
counter sysreg.
We got this right for the EL1 physical timer and for the EL1 virtual
timer, but got all the rest wrong: they should be using a zero offset
always.
Factor the offset calculation out into a function that has a comment
documenting exactly which offset it is calculating and which gets the
HYP, SEC, and HYPVIRT cases right.
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: 5709038aa8b4d58b8c201ed53c327074173a35c6
https://github.com/qemu/qemu/commit/5709038aa8b4d58b8c201ed53c327074173a35c6
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
The CNTVOFF_EL2 offset register should only be applied for accessses
to CNTVCT_EL0 and for the EL1 virtual timer (CNTV_*). We were
incorrectly applying it for the EL2 virtual timer (CNTHV_*).
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: bdd641541fbef0a27bf9f60e7eba6f8a31d4706c
https://github.com/qemu/qemu/commit/bdd641541fbef0a27bf9f60e7eba6f8a31d4706c
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
When we added Secure EL2 support, we missed that this needs an update
to the access code for the EL3 physical timer registers. These are
supposed to UNDEF from Secure EL1 when Secure EL2 is enabled.
(Note for stable backporting: for backports to branches where
CP_ACCESS_UNDEFINED is not defined, the old name to use instead
is CP_ACCESS_TRAP_UNCATEGORIZED.)
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: 4aecd4b442d7abb4355896d878ffc9b028625b01
https://github.com/qemu/qemu/commit/4aecd4b442d7abb4355896d878ffc9b028625b01
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
Currently we handle CNTV_TVAL_EL02 by calling gt_tval_read() for the
EL1 virt timer. This is almost correct, but the underlying
CNTV_TVAL_EL0 register behaves slightly differently. CNTV_TVAL_EL02
always applies the CNTVOFF_EL2 offset; CNTV_TVAL_EL0 doesn't do so if
we're at EL2 and HCR_EL2.E2H is 1.
We were getting this wrong, because we ended up in
gt_virt_cnt_offset() and did the E2H check.
Factor out the tval read/write calculation from the selection of the
offset, so that we can special case gt_virt_tval_read() and
gt_virt_tval_write() to unconditionally pass CNTVOFF_EL2.
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: 02c648a0a103a1a7b2c077ec5a81da9907f45544
https://github.com/qemu/qemu/commit/02c648a0a103a1a7b2c077ec5a81da9907f45544
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Refactor handling of timer offset for direct register accesses
When reading or writing the timer registers, sometimes we need to
apply one of the timer offsets. Specifically, this happens for
direct reads of the counter registers CNTPCT_EL0 and CNTVCT_EL0 (and
their self-synchronized variants CNTVCTSS_EL0 and CNTPCTSS_EL0). It
also applies for direct reads and writes of the CNT*_TVAL_EL*
registers that provide the 32-bit downcounting view of each timer.
We currently do this with duplicated code in gt_tval_read() and
gt_tval_write() and a special-case in gt_virt_cnt_read() and
gt_cnt_read(). Refactor this so that we handle it all in a single
function gt_direct_access_timer_offset(), to parallel how we handle
the offset for indirect accesses.
The call in the WFIT helper previously to gt_virt_cnt_offset() is
now to gt_direct_access_timer_offset(); this is the correct
behaviour, but it's not immediately obvious that it shouldn't be
considered an indirect access, so we add an explanatory comment.
This commit should make no behavioural changes.
(Cc to stable because the following bugfix commit will
depend on this one.)
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: f9f99d7ca522339c1de2292f132bb8ddc3471c39
https://github.com/qemu/qemu/commit/f9f99d7ca522339c1de2292f132bb8ddc3471c39
Author: Alex Bennée <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M include/hw/arm/bsa.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gtimer.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement SEL2 physical and virtual timers
When FEAT_SEL2 was implemented the SEL2 timers were missed. This
shows up when building the latest Hafnium with SPMC_AT_EL=2. The
actual implementation utilises the same logic as the rest of the
timers so all we need to do is:
- define the timers and their access functions
- conditionally add the correct system registers
- create a new accessfn as the rules are subtly different to the
existing secure timer
Fixes: e9152ee91c (target/arm: add ARMv8.4-SEL2 system registers)
Signed-off-by: Alex Bennée <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Cc: [email protected]
Cc: Andrei Homescu <[email protected]>
Cc: Arve Hjønnevåg <[email protected]>
Cc: Rémi Denis-Courmont <[email protected]>
[PMM: CP_ACCESS_TRAP_UNCATEGORIZED -> CP_ACCESS_UNDEFINED;
offset logic now in gt_{indirect,direct}_access_timer_offset() ]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 47e2c5510f8c13310bfe738ebaa913bb52feca2a
https://github.com/qemu/qemu/commit/47e2c5510f8c13310bfe738ebaa913bb52feca2a
Author: Alex Bennée <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/gtimer.h
Log Message:
-----------
target/arm: Document the architectural names of our GTIMERs
As we are about to add more physical and virtual timers let's make it
clear what each timer does.
Signed-off-by: Alex Bennée <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
[PMM: Add timer register name prefix to each comment]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5dcaea8bcd82972add29eef350547f922fb4caa2
https://github.com/qemu/qemu/commit/5dcaea8bcd82972add29eef350547f922fb4caa2
Author: Alex Bennée <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm: enable secure EL2 timers for virt machine
Signed-off-by: Alex Bennée <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Cc: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9a9d9e82093efa22e3e2bdaac0f24c823f8786f7
https://github.com/qemu/qemu/commit/9a9d9e82093efa22e3e2bdaac0f24c823f8786f7
Author: Alex Bennée <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/arm/sbsa-ref.c
Log Message:
-----------
hw/arm: enable secure EL2 timers for sbsa machine
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: cde3247651dc998da5dc1005148302a90d72f21f
https://github.com/qemu/qemu/commit/cde3247651dc998da5dc1005148302a90d72f21f
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Correct LDRD atomicity and fault behaviour
Our LDRD implementation is wrong in two respects:
* if the address is 4-aligned and the load crosses a page boundary
and the second load faults and the first load was to the
base register (as in cases like "ldrd r2, r3, [r2]", then we
must not update the base register before taking the fault
* if the address is 8-aligned the access must be a 64-bit
single-copy atomic access, not two 32-bit accesses
Rewrite the handling of the loads in LDRD to use a single
tcg_gen_qemu_ld_i64() and split the result into the destination
registers. This allows us to get the atomicity requirements
right, and also implicitly means that we won't update the
base register too early for the page-crossing case.
Note that because we no longer increment 'addr' by 4 in the course of
performing the LDRD we must change the adjustment value we pass to
op_addr_ri_post() and op_addr_rr_post(): it no longer needs to
subtract 4 to get the correct value to use if doing base register
writeback.
STRD has the same problem with not getting the atomicity right;
we will deal with that in the following commit.
Cc: [email protected]
Reported-by: Stu Grossman <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: ee786ca115045a2b7e86ac3073b0761cb99e0d49
https://github.com/qemu/qemu/commit/ee786ca115045a2b7e86ac3073b0761cb99e0d49
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Correct STRD atomicity
Our STRD implementation doesn't correctly implement the requirement:
* if the address is 8-aligned the access must be a 64-bit
single-copy atomic access, not two 32-bit accesses
Rewrite the handling of STRD to use a single tcg_gen_qemu_st_i64()
of a value produced by concatenating the two 32 bit source registers.
This allows us to get the atomicity right.
As with the LDRD change, now that we don't update 'addr' in the
course of performing the store we need to adjust the offset
we pass to op_addr_ri_post() and op_addr_rr_post().
Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 5be4419c573e78c21be953a4c31947f3087931a5
https://github.com/qemu/qemu/commit/5be4419c573e78c21be953a4c31947f3087931a5
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
All the callers of op_addr_rr_post() and op_addr_ri_post() now pass in
zero for the address_offset, so we can remove that argument.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: cc503abf4ba30ed34bbf18b3fd8eaa8046fae48b
https://github.com/qemu/qemu/commit/cc503abf4ba30ed34bbf18b3fd8eaa8046fae48b
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Make dummy debug registers RAZ, not NOP
In debug_helper.c we provide a few dummy versions of
debug registers:
* DBGVCR (AArch32 only): enable bits for vector-catch
debug events
* MDCCINT_EL1: interrupt enable bits for the DCC
debug communications channel
* DBGVCR32_EL2: the AArch64 accessor for the state in
DBGVCR
We implemented these only to stop Linux crashing on startup,
but we chose to implement them as ARM_CP_NOP. This worked
for Linux where it only cares about trying to write to these
registers, but is very confusing behaviour for anything that
wants to read the registers (perhaps for context state switches),
because the destination register will be left with whatever
random value it happened to have before the read.
Model these registers instead as RAZ.
Fixes: 5e8b12ffbb8c68 ("target-arm: Implement minimal DBGVCR, OSDLR_EL1,
MDCCSR_EL0")
Fixes: 5dbdc4342f479d ("target-arm: Implement dummy MDCCINT_EL1")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2708
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 02ae315467cee589d02dfb89e13a2a6a8de09fc5
https://github.com/qemu/qemu/commit/02ae315467cee589d02dfb89e13a2a6a8de09fc5
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M util/qemu-timer.c
Log Message:
-----------
util/qemu-timer.c: Don't warp timer from timerlist_rearm()
Currently we call icount_start_warp_timer() from timerlist_rearm().
This produces incorrect behaviour, because timerlist_rearm() is
called, for instance, when a timer callback modifies its timer. We
cannot decide here to warp the timer forwards to the next timer
deadline merely because all_cpu_threads_idle() is true, because the
timer callback we were called from (or some other callback later in
the list of callbacks being invoked) may be about to raise a CPU
interrupt and move a CPU from idle to ready.
The only valid place to choose to warp the timer forward is from the
main loop, when we know we have no outstanding IO or timer callbacks
that might be about to wake up a CPU.
For Arm guests, this bug was mostly latent until the refactoring
commit f6fc36deef6abc ("target/arm/helper: Implement
CNTHCTL_EL2.CNT[VP]MASK"), which exposed it because it refactored a
timer callback so that it happened to call timer_mod() first and
raise the interrupt second, when it had previously raised the
interrupt first and called timer_mod() afterwards.
This call seems to have originally derived from the
pre-record-and-replay icount code, which (as of e.g. commit
db1a49726c3c in 2010) in this location did a call to
qemu_notify_event(), necessary to get the icount code in the vCPU
round-robin thread to stop and recalculate the icount deadline when a
timer was reprogrammed from the IO thread. In current QEMU,
everything is done on the vCPU thread when we are in icount mode, so
there's no need to try to notify another thread here.
I suspect that the other reason why this call was doing icount timer
warping is that it pre-dates commit efab87cf79077a from 2015, which
added a call to icount_start_warp_timer() to main_loop_wait(). Once
the call in timerlist_rearm() has been removed, if the timer
callbacks don't cause any CPU to be woken up then we will end up
calling icount_start_warp_timer() from main_loop_wait() when the rr
main loop code calls rr_wait_io_event().
Remove the incorrect call from timerlist_rearm().
Cc: [email protected]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2703
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Tested-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: 84e5ce68c0c2d52d97a66ff2f53697f9ced190a8
https://github.com/qemu/qemu/commit/84e5ce68c0c2d52d97a66ff2f53697f9ced190a8
Author: Peter Maydell <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M include/exec/memop.h
Log Message:
-----------
include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
Expand the example in the comment documenting MO_ATOM_SUBALIGN,
to be clearer about the atomicity guarantees it represents.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 8881b691d2d3613e9d7ff596a46a451b393377a5
https://github.com/qemu/qemu/commit/8881b691d2d3613e9d7ff596a46a451b393377a5
Author: JianChunfu <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M include/hw/arm/smmu-common.h
Log Message:
-----------
hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
Use a similar terminology smmu_hash_remove_by_sid_range() as the one
being used for other hash table matching functions since
smmuv3_invalidate_ste() name is not self explanatory, and introduce a
helper that invokes the g_hash_table_foreach_remove.
No functional change intended.
Signed-off-by: JianChunfu <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7610317f45159b620475aafc7a94c93b66eda7e2
https://github.com/qemu/qemu/commit/7610317f45159b620475aafc7a94c93b66eda7e2
Author: Keith Packard <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/rx/helper.c
Log Message:
-----------
target/rx: Set exception vector base to 0xffffff80
The documentation says the vector is at 0xffffff80, instead of the
previous value of 0xffffffc0. That value must have been a bug because
the standard vector values (20, 21, 23, 25, 30) were all
past the end of the array.
Signed-off-by: Keith Packard <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0ce0739d46983e5e88fa9c149cb305689c9d8c6f
https://github.com/qemu/qemu/commit/0ce0739d46983e5e88fa9c149cb305689c9d8c6f
Author: Keith Packard <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M target/rx/helper.h
Log Message:
-----------
target/rx: Remove TCG_CALL_NO_WG from helpers which write env
Functions which modify TCG globals must not be marked TCG_CALL_NO_WG,
as that tells the optimizer that TCG global values already loaded in
machine registers are still valid, and so any changes which these
helpers make to the CPU state may be ignored.
The target/rx code chooses to put (among other things) all the PSW
bits and also ACC into globals, so the NO_WG flag on various
functions that touch the PSW or ACC is incorrect and must be removed.
This includes all the floating point helper functions, because
update_fpsw() will update PSW Z and S.
Signed-off-by: Keith Packard <[email protected]>
[PMM: Clarified commit message]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: cfadd798dec85f1dc2f3db0debf139e2b92f9c4f
https://github.com/qemu/qemu/commit/cfadd798dec85f1dc2f3db0debf139e2b92f9c4f
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/helper.h
M target/loongarch/internals.h
M target/loongarch/tcg/csr_helper.c
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20250307' of https://gitlab.com/gaosong/qemu into
staging
pull-loongarch-tcg-20250307
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# gpg: WARNING: This key is not certified with a trusted signature!
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# Primary key fingerprint: B8FF 1DA0 D2FD CB2D A09C 6C2C 40A2 FFF2 3926 3EDF
* tag 'pull-loongarch-20250307' of https://gitlab.com/gaosong/qemu:
target/loongarch: check tlb_ps
target/loongarch: fix 'make check-functional' failed
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: e88a579392f74aa7658299f29dc43aca199e4533
https://github.com/qemu/qemu/commit/e88a579392f74aa7658299f29dc43aca199e4533
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M MAINTAINERS
M docs/devel/testing/functional.rst
M hw/s390x/s390-pci-bus.c
M hw/s390x/s390-pci-inst.c
M hw/s390x/s390-pci-vfio.c
M hw/s390x/s390-virtio-ccw.c
M include/hw/s390x/s390-pci-bus.h
M include/hw/s390x/s390-pci-clp.h
M tests/functional/meson.build
M tests/functional/qemu_test/linuxkernel.py
M tests/functional/qemu_test/testcase.py
M tests/functional/qemu_test/tuxruntest.py
M tests/functional/qemu_test/uncompress.py
M tests/functional/test_intel_iommu.py
M tests/functional/test_mem_addr_space.py
M tests/functional/test_mips_malta.py
M tests/functional/test_ppc64_tuxrun.py
M tests/functional/test_virtio_balloon.py
Log Message:
-----------
Merge tag 'pull-request-2025-03-07' of https://gitlab.com/thuth/qemu into
staging
* Bug fixes and some small improvements for functional tests
* Improve performance of s390x PCI passthrough devices with relaxed translation
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# gpg: Good signature from "Thomas Huth <[email protected]>" [full]
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# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-03-07' of https://gitlab.com/thuth/qemu:
s390x/pci: indicate QEMU supports relaxed translation for passthrough
s390x/pci: add support for guests that request direct mapping
MAINTAINERS: Add docs/devel/testing/functional.rst to the functional section
doc: add missing 'Asset' type in function test doc
tests/functional/test_virtio_balloon: Only use KVM for running this test
tests/functional: fix race in virtio balloon test
tests/functional: Increase the timeout of the mips64el_replay test
tests/functional/test_mips_malta: Add a network test via the pcnet NIC
tests/functional: Move the code for testing HTTP downloads to a common
function
tests/functional: stop output from zstd command when uncompressing
tests/functional: drop unused 'get_tag' method
tests/functional: skip memaddr tests on 32-bit builds
tests/functional: reduce tuxrun maxmem to work on 32-bit hosts
tests/functional: set 'qemu_bin' as an object level field
tests/functional: remove unused 'bin_prefix' variable
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: ffbc5e661fc3b73debaec2354bf46273186bf882
https://github.com/qemu/qemu/commit/ffbc5e661fc3b73debaec2354bf46273186bf882
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-08 (Sat, 08 Mar 2025)
Changed paths:
M MAINTAINERS
M hw/arm/sbsa-ref.c
M hw/arm/smmu-common.c
M hw/arm/smmu-internal.h
M hw/arm/smmuv3.c
M hw/arm/trace-events
M hw/arm/virt.c
M hw/gpio/npcm7xx_gpio.c
M include/exec/memop.h
M include/hw/arm/bsa.h
M include/hw/arm/smmu-common.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/debug_helper.c
M target/arm/gtimer.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/op_helper.c
M target/arm/tcg/translate.c
M target/rx/helper.c
M target/rx/helper.h
M tests/functional/test_arm_sx1.py
M util/qemu-timer.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250307' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/smmu-common: Remove the repeated ttb field
* hw/gpio: npcm7xx: fixup out-of-bounds access
* tests/functional/test_arm_sx1: Check whether the serial console is working
* target/arm: Fix minor bugs in generic timer register handling
* target/arm: Implement SEL2 physical and virtual timers
* target/arm: Correct STRD, LDRD atomicity and fault behaviour
* target/arm: Make dummy debug registers RAZ, not NOP
* util/qemu-timer.c: Don't warp timer from timerlist_rearm()
* include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
* hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
* target/rx: Set exception vector base to 0xffffff80
* target/rx: Remove TCG_CALL_NO_WG from helpers which write env
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# c65VNXkbaCIedrSlalMO4w==
# =8typ
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 07 Mar 2025 23:05:28 HKT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250307' of
https://git.linaro.org/people/pmaydell/qemu-arm: (21 commits)
target/rx: Remove TCG_CALL_NO_WG from helpers which write env
target/rx: Set exception vector base to 0xffffff80
hw/arm/smmu: Introduce smmu_configs_inv_sid_range() helper
include/exec/memop.h: Expand comment for MO_ATOM_SUBALIGN
util/qemu-timer.c: Don't warp timer from timerlist_rearm()
target/arm: Make dummy debug registers RAZ, not NOP
target/arm: Drop unused address_offset from op_addr_{rr, ri}_post()
target/arm: Correct STRD atomicity
target/arm: Correct LDRD atomicity and fault behaviour
hw/arm: enable secure EL2 timers for sbsa machine
hw/arm: enable secure EL2 timers for virt machine
target/arm: Document the architectural names of our GTIMERs
target/arm: Implement SEL2 physical and virtual timers
target/arm: Refactor handling of timer offset for direct register accesses
target/arm: Always apply CNTVOFF_EL2 for CNTV_TVAL_EL02 accesses
target/arm: Make CNTPS_* UNDEF from Secure EL1 when Secure EL2 is enabled
target/arm: Don't apply CNTVOFF_EL2 for EL2_VIRT timer
target/arm: Apply correct timer offset when calculating deadlines
tests/functional/test_arm_sx1: Check whether the serial console is working
hw/gpio: npcm7xx: fixup out-of-bounds access
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/98c7362b1efe...ffbc5e661fc3
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