Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 41494da7df8d28eb75eac4799f4b49061fbbf64c
https://github.com/qemu/qemu/commit/41494da7df8d28eb75eac4799f4b49061fbbf64c
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M meson.build
Log Message:
-----------
chardev: express dependency on io/
chardev is using qio functions, so express that in the Meson internal
dependency. (I found this when adding character devices bindings for
Rust; they initially needed the io dependency added by hand).
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: cff666a3aee566889fcc1ab7167ca0a727af7167
https://github.com/qemu/qemu/commit/cff666a3aee566889fcc1ab7167ca0a727af7167
Author: Nabih Estefan <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M scripts/meson-buildoptions.py
Log Message:
-----------
scripts: dump stdin on meson-buildoptions error
Dump sys.stdin when it errors on meson-buildoptions.py, letting us debug
the build errors instead of just saying "Couldn't parse"
Signed-off-by: Nabih Estefan <[email protected]>
Signed-off-by: Patrick Venture <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0b9d05e3c98fe168f3502ccc422b9171467314fa
https://github.com/qemu/qemu/commit/0b9d05e3c98fe168f3502ccc422b9171467314fa
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M docs/devel/rust.rst
M rust/qemu-api/src/cell.rs
Log Message:
-----------
rust: cell: add wrapper for FFI types
Inspired by the same-named type in Linux. This type provides the compiler
with a correct view of what goes on with FFI types. In addition, it
separates the glue code from the bindgen-generated code, allowing
traits such as Send, Sync or Zeroable to be specified independently
for C and Rust structs.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f07a5674cf97b8473e5d06d7b1df9b51e97d553f
https://github.com/qemu/qemu/commit/f07a5674cf97b8473e5d06d7b1df9b51e97d553f
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M docs/devel/rust.rst
M rust/qemu-api-macros/src/lib.rs
M rust/qemu-api/meson.build
M rust/qemu-api/src/cell.rs
Log Message:
-----------
rust: qemu_api_macros: add Wrapper derive macro
Add a derive macro that makes it easy to peel off all the layers of
specialness (UnsafeCell, MaybeUninit, etc.) and just get a pointer
to the wrapped type; and likewise add them back starting from a
*mut.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d7f5ae8b30cc9652a4ddcfeb52076f5aef6d78b6
https://github.com/qemu/qemu/commit/d7f5ae8b30cc9652a4ddcfeb52076f5aef6d78b6
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/vmstate.rs
Log Message:
-----------
rust: vmstate: add std::pin::Pin as transparent wrapper
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e8dc87fef2677dc286b3fe72e04d1b763cf98fef
https://github.com/qemu/qemu/commit/e8dc87fef2677dc286b3fe72e04d1b763cf98fef
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/timer/hpet/src/hpet.rs
Log Message:
-----------
rust: hpet: embed Timer without the Option and Box indirection
This simplifies things for migration, since Option<Box<QEMUTimer>> does not
implement VMState.
This also shows a soundness issue because Timer::new() will leave a NULL
timer list pointer, which can then be dereferenced by Timer::modify(). It
will be fixed shortly.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a32b239699377f09bba08b2e8ae0d167c1488b1f
https://github.com/qemu/qemu/commit/a32b239699377f09bba08b2e8ae0d167c1488b1f
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M meson.build
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/src/timer.rs
Log Message:
-----------
rust: timer: wrap QEMUTimer with Opaque<> and express pinning requirements
Timers must be pinned in memory, because modify() stores a pointer to them
in the TimerList. To express this requirement, change init_full() to take
a pinned reference. Because the only way to obtain a Timer is through
Timer::new(), which is unsafe, modify() can assume that the timer it got
was later initialized; and because the initialization takes a Pin<&mut
Timer> modify() can assume that the timer is pinned. In the future the
pinning requirement will be expressed through the pin_init crate instead.
Note that Timer is a bit different from other users of Opaque, in that
it is created in Rust code rather than C code. This is why it has to
use the unsafe constructors provided by Opaque; and in fact Timer::new()
is also unsafe, because it leaves it to the caller to invoke init_full()
before modify(). Without a call to init_full(), modify() will cause a
NULL pointer dereference.
An alternative could be to combine new() + init_full() by returning a
pinned box; however, using a reference makes it easier to express
the requirement that the opaque outlives the timer.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 9c9a6a889cb3589779b019a343892aa0e9bdb254
https://github.com/qemu/qemu/commit/9c9a6a889cb3589779b019a343892aa0e9bdb254
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/irq.rs
M rust/qemu-api/src/sysbus.rs
Log Message:
-----------
rust: irq: wrap IRQState with Opaque<>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7fb4a99df17c8ae5f5e00d643042b9d95477a426
https://github.com/qemu/qemu/commit/7fb4a99df17c8ae5f5e00d643042b9d95477a426
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/memory.rs
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/qom.rs
Log Message:
-----------
rust: qom: wrap Object with Opaque<>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: fc22d650d54363b8f2bad56aea1dde773f600067
https://github.com/qemu/qemu/commit/fc22d650d54363b8f2bad56aea1dde773f600067
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/vmstate.rs
Log Message:
-----------
rust: qdev: wrap Clock and DeviceState with Opaque<>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 09fda8f5dc925ba059aca539163d16796af6a299
https://github.com/qemu/qemu/commit/09fda8f5dc925ba059aca539163d16796af6a299
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api/src/sysbus.rs
Log Message:
-----------
rust: hpet: do not access fields of SysBusDevice
Fields of SysBusDevice must only be accessed with the BQL taken. Add
a wrapper that verifies that.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f4751c7a42b194eb4166c7f3f294bf89c3e23cd9
https://github.com/qemu/qemu/commit/f4751c7a42b194eb4166c7f3f294bf89c3e23cd9
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/sysbus.rs
Log Message:
-----------
rust: sysbus: wrap SysBusDevice with Opaque<>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: af0868cba33aaf327a49d642b6b0ad3ae3f01240
https://github.com/qemu/qemu/commit/af0868cba33aaf327a49d642b6b0ad3ae3f01240
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/memory.rs
Log Message:
-----------
rust: memory: wrap MemoryRegion with Opaque<>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 48627510a7fed7a045358743e6b869a98931f85e
https://github.com/qemu/qemu/commit/48627510a7fed7a045358743e6b869a98931f85e
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/chardev.rs
M rust/qemu-api/src/qdev.rs
Log Message:
-----------
rust: chardev: wrap Chardev with Opaque<>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2ad011d466697d69f7f9aa84662a6553049f6556
https://github.com/qemu/qemu/commit/2ad011d466697d69f7f9aa84662a6553049f6556
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/bindings.rs
Log Message:
-----------
rust: bindings: remove more unnecessary Send/Sync impls
Send and Sync are now implemented on the opaque wrappers. Remove them
from the bindings module, unless the structs are pure data containers
and/or have no C functions defined on them.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2d0050cbe27fed5233561451e6de64af5ecb6571
https://github.com/qemu/qemu/commit/2d0050cbe27fed5233561451e6de64af5ecb6571
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/meson.build
M rust/qemu-api/src/chardev.rs
M rust/qemu-api/src/zeroable.rs
Log Message:
-----------
rust: chardev: provide basic bindings to character devices
Most of the character device API is pretty simple, with "0 or -errno"
or "number of bytes or -errno" as the convention for return codes.
Add safe wrappers for the API to the CharBackend bindgen-generated
struct.
The API is not complete, but it covers the parts that are used
by the PL011 device, plus qemu_chr_fe_write which is needed to
implement the standard library Write trait.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 959fd759a2a55d90bf18f5b275cf6c7b11b27a79
https://github.com/qemu/qemu/commit/959fd759a2a55d90bf18f5b275cf6c7b11b27a79
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
M rust/hw/char/pl011/src/lib.rs
A rust/hw/char/pl011/src/registers.rs
Log Message:
-----------
rust: pl011: move register definitions out of lib.rs
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 87f5c138363da28449835055299abbae57f39a19
https://github.com/qemu/qemu/commit/87f5c138363da28449835055299abbae57f39a19
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
Log Message:
-----------
rust: pl011: clean up visibilities of callbacks
Do not make callbacks unnecessarily "pub", they are only used
through function pointers.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 9b642097d6b793c161c3d1c540dd19a66e02100f
https://github.com/qemu/qemu/commit/9b642097d6b793c161c3d1c540dd19a66e02100f
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
Log Message:
-----------
rust: pl011: switch to safe chardev operation
Switch bindings::CharBackend with chardev::CharBackend. This removes
occurrences of "unsafe" due to FFI and switches the wrappers for receive,
can_receive and event callbacks to the common ones implemented by
chardev::CharBackend.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: aa50bc4fb9d4fc1dc027c4d70babe0acb6c09971
https://github.com/qemu/qemu/commit/aa50bc4fb9d4fc1dc027c4d70babe0acb6c09971
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
Log Message:
-----------
rust: pl011: pass around registers::Data
The values stored in the Fifo are instances of the bitfield-struct
registers::Data. Convert as soon as possible the value written
into DR, and always refer to the bitfield struct; it's generally
cleaner other than PL011State::receive having to do a double
conversion u8=>u32=>registers::Data.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 519088b7cf6dbdef08d8753b57aa29162b83d1a1
https://github.com/qemu/qemu/commit/519088b7cf6dbdef08d8753b57aa29162b83d1a1
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/Cargo.toml
M rust/hw/char/pl011/src/lib.rs
M rust/hw/timer/hpet/src/hpet.rs
Log Message:
-----------
rust: hpet: decode HPET registers into enums
Generalize timer_and_addr() to decode all registers into a single enum
HPETRegister, and use the TryInto derive to separate valid and
invalid values.
The main advantage lies in checking that all registers are enumerated
in the "match" statements.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5778ce99971f7e09952a1efbac91d0c97d7a0fee
https://github.com/qemu/qemu/commit/5778ce99971f7e09952a1efbac91d0c97d7a0fee
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/cell.rs
Log Message:
-----------
rust: cell: add full example of declaring a SysBusDevice
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 094cd35913bd66228a9a3239e66b1f6f5d667d4b
https://github.com/qemu/qemu/commit/094cd35913bd66228a9a3239e66b1f6f5d667d4b
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-06 (Thu, 06 Mar 2025)
Changed paths:
M rust/qemu-api/src/memory.rs
M rust/qemu-api/src/prelude.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/tests/tests.rs
Log Message:
-----------
rust: qom: remove operations on &mut
The dubious casts of mutable references to objects are not used
anymore: the wrappers for qdev_init_clock_in and for IRQ and MMIO
initialization can be called directly on the subclasses, without
casts, plus they take a shared reference so they can just use
"upcast()" instead of "upcast_mut()". Remove them.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 563b1a35ed1f1151505d4fe5f723827d1b3fd4bc
https://github.com/qemu/qemu/commit/563b1a35ed1f1151505d4fe5f723827d1b3fd4bc
Author: Alex Bennée <[email protected]>
Date: 2025-03-07 (Fri, 07 Mar 2025)
Changed paths:
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
meson.build: default to -gsplit-dwarf for debug info
This option is supported by both gcc (since 4.7) and clang (since
7.0). Not only does this make the linkers job easier by reducing the
amount of ELF it needs to parse it also reduces the total build size
quite considerably. In my case a default build went from 5.8G to
3.9G (vs 1.9G for --disable-debug-info).
The --disable-split-debug option allows distros to keep all the info
together for ease of packaging.
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 816945364f698ae750aa665fce3d121c98e37a6f
https://github.com/qemu/qemu/commit/816945364f698ae750aa665fce3d121c98e37a6f
Author: Peter Maydell <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M rust/hw/char/pl011/src/device.rs
Log Message:
-----------
rust: pl011: Allow NULL chardev argument to pl011_create()
It's valid for the caller to pass a NULL chardev to pl011_create();
this means "don't set the chardev property on the device", which
in turn means "act like there's no chardev". All the chardev
frontend APIs (in C, at least) accept a NULL pointer to mean
"do nothing".
This fixes some failures in 'make check-functional' when Rust support
is enabled.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: ae139d6e9248526dcfe5d522061910509809a778
https://github.com/qemu/qemu/commit/ae139d6e9248526dcfe5d522061910509809a778
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/aspeed.py
Log Message:
-----------
tests/functional: Introduce a new test routine for OpenBMC images
The OpenBMC images currently used by QEMU to test the Aspeed machines
are rather old. To prepare an update to the latest builds, we need to
adjust the console patterns. Introduce a new routine to preserve the
current tests.
Reviewed-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6664b3e255ed89b93e4311361ae62d05313f2ae8
https://github.com/qemu/qemu/commit/6664b3e255ed89b93e4311361ae62d05313f2ae8
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/test_arm_aspeed_palmetto.py
Log Message:
-----------
tests/functional: Update OpenBMC image of palmetto machine
Use the new do_test_arm_aspeed_openbmc() routine to run the latest
OpenBMC firmware build of the palmetto BMC.
Reviewed-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 01050d97e1f342590f5f2db4a6d2b557a8244f44
https://github.com/qemu/qemu/commit/01050d97e1f342590f5f2db4a6d2b557a8244f44
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/aspeed.py
M tests/functional/test_arm_aspeed_romulus.py
Log Message:
-----------
tests/functional: Update OpenBMC image of romulus machine
Use the new do_test_arm_aspeed_openbmc() routine to run the latest
OpenBMC firmware build of the romulus BMC. Remove the older routine
which is now unused.
Reviewed-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3058b634f2785454504328e1710b7cab66a5acf9
https://github.com/qemu/qemu/commit/3058b634f2785454504328e1710b7cab66a5acf9
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/meson.build
A tests/functional/test_arm_aspeed_witherspoon.py
Log Message:
-----------
tests/functional: Introduce a witherspoon machine test
Use do_test_arm_aspeed_openbmc() routine to run the latest OpenBMC
firmware build of the witherspoon BMC.
Reviewed-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b91a1d31106f042df294410214656608e5b2fe2f
https://github.com/qemu/qemu/commit/b91a1d31106f042df294410214656608e5b2fe2f
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/meson.build
A tests/functional/test_arm_aspeed_bletchley.py
Log Message:
-----------
tests/functional: Introduce a bletchley machine test
Use do_test_arm_aspeed_openbmc() to run the latest OpenBMC firmware
build of the bletchley BMC.
Reviewed-by: Patrick Williams <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 136367e567771b7aef49e734817667950413deba
https://github.com/qemu/qemu/commit/136367e567771b7aef49e734817667950413deba
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
aspeed/soc: Support Non-maskable Interrupt for AST2700
QEMU supports GICv3 Non-maskable Interrupt, adds to support Non-maskable
Interrupt for AST2700.
Reference:
https://github.com/qemu/qemu/commit/b36a32ead
Signed-off-by: Jamin Lin <[email protected]>
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Commit: a5b9621024f25b374c270e8f7216e35f911720e6
https://github.com/qemu/qemu/commit/a5b9621024f25b374c270e8f7216e35f911720e6
Author: Cédric Le Goater <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
aspeed: Remove duplicate typename in AspeedSoCClass
The SoC type name is stored under AspeedSoCClass which is
redundant. Use object_get_typename() instead where needed.
Reviewed-by: Andrew Jeffery <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cde8182b8772fc35dc44cd688166c59e7b9c9530
https://github.com/qemu/qemu/commit/cde8182b8772fc35dc44cd688166c59e7b9c9530
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_hace.c
Log Message:
-----------
hw/misc/aspeed_hace: Fix coding style
Fix coding style issues from checkpatch.pl.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 393c908afb39df5ca44b67edf3acb16bb8835cf7
https://github.com/qemu/qemu/commit/393c908afb39df5ca44b67edf3acb16bb8835cf7
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Add AST2700 support
Introduce a new ast2700 class to support AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 7b5d6b47a6c99e3e3c843000c821e6549c8feb01
https://github.com/qemu/qemu/commit/7b5d6b47a6c99e3e3c843000c821e6549c8feb01
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Add HACE support for AST2700
The HACE controller between AST2600 and AST2700 are almost identical.
The HACE controller registers base address starts at 0x1207_0000 and
its alarm interrupt is connected to GICINT4.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Andrew Jeffery <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8e002a693198865632f6bed072c5473a6bb9cf45
https://github.com/qemu/qemu/commit/8e002a693198865632f6bed072c5473a6bb9cf45
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_hace.c
M include/hw/misc/aspeed_hace.h
Log Message:
-----------
hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test
Currently, it does not support the CRYPT command. Instead, it only sends an
interrupt to notify the firmware that the crypt command has completed.
It is a temporary workaround to resolve the boot issue in the Crypto Manager
Self Test.
Introduce a new "use_crypt_workaround" class attribute and set it to true in
the AST2700 HACE model to enable this workaround by default for AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2d082fea485ee455a70ed3e963cdf9a70f34858a
https://github.com/qemu/qemu/commit/2d082fea485ee455a70ed3e963cdf9a70f34858a
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Skipping dram_init in u-boot
Setting BIT6 in VGA0 SCRATCH register will indicate that the ddr traning
is done, therefore skipping the u-boot-spl dram_init() process.
Signed-off-by: Jamin Lin <[email protected]>
Signed-off-by: Troy Lee <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 801e0dad6ad4c4e078f907d825113251e374f6b2
https://github.com/qemu/qemu/commit/801e0dad6ad4c4e078f907d825113251e374f6b2
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for
AST2700
According to the design of the AST2600, it has a Silicon Revision ID Register,
specifically SCU004 and SCU014, to set the Revision ID for the AST2600.
For the AST2600 A3, SCU004 is set to 0x05030303 and SCU014 is set to 0x05030303.
In the "aspeed_ast2600_scu_reset" function, the hardcoded value
"AST2600_A3_SILICON_REV" is set in SCU004, and "s->silicon_rev" is set in
SCU014. The value of "s->silicon_rev" is set by the SOC layer via the
"silicon-rev" property.
However, the design of the AST2700 is different. There are two SCU controllers:
SCU0 (CPU Die) and SCU1 (IO Die). In the AST2700, the firmware reads the SCU
Silicon Revision ID register (SCU0_000) and the SCUIO Silicon Revision ID
register (SCU1_000), combining them into a single 64-bit value.
The upper 32 bits represent the SCUIO, while the lower 32 bits correspond to the
SCU. For example, the AST2700-A1 revision is represented as 0x0601010306010103.
SCUIO_000 occupies bits [63:32] with a value of 0x06010103 and SCU_000 occupies
bits [31:0] with a value of 0x06010103.
Reference:
https://github.com/AspeedTech-BMC/u-boot/blob/aspeed-master-v2023.10/arch/arm/mach-aspeed/ast2700/cpu-info.c
Signed-off-by: Jamin Lin <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 172329c6b281e11feb3d6e60df6754008e23a089
https://github.com/qemu/qemu/commit/172329c6b281e11feb3d6e60df6754008e23a089
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed Update HW Strap Default Values for AST2700
Separate HW Strap Registers for SCU and SCUIO.
AST2700_EVB_HW_STRAP1 is used for the SCU (CPU Die) hw-strap1.
AST2700_EVB_HW_STRAP2 is used for the SCUIO (IO Die) hw-strap1.
Additionally, both default values are updated based on the dump from the EVB.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 720e850f83ef6497d9992c43716fb5d7cc9a2ad2
https://github.com/qemu/qemu/commit/720e850f83ef6497d9992c43716fb5d7cc9a2ad2
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_scu.c
Log Message:
-----------
hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer for
AST2700
There is one hw_strap1 register in the SCU (CPU DIE) and another hw_strap1
register in the SCUIO (IO DIE).
In the "ast2700_a0_resets" function, the hardcoded value "0x00000800" is set in
SCU hw-strap1 (CPU DIE), and in "ast2700_a0_resets_io" the hardcoded value
"0x00000504" is set in SCUIO hw-strap1 (IO DIE). Both values cannot be set via
the SOC layer.
The value of "s->hw_strap1" is set by the SOC layer via the "hw-strap1"
property.
Update the "aspeed_ast2700_scu_reset" function to set the value of
"s->hw_strap1"
in both the SCU and SCUIO hw-strap1 registers.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b741ab395b398058198ba3f055d9d8c4d631122f
https://github.com/qemu/qemu/commit/b741ab395b398058198ba3f055d9d8c4d631122f
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO
There is one hw-strap1 register in the SCU (CPU DIE) and another hw-strap1
register in the SCUIO (IO DIE). The values of these two registers should not be
the same. To reuse the current design of hw-strap, hw-strap1 is assigned to the
SCU and sets the value in the SCU hw-strap1 register, while hw-strap2 is
assigned to the SCUIO and sets the value in the SCUIO hw-strap1 register.
Signed-off-by: Jamin Lin <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8dd163f915cf26277fa175476c0af6898b8fd864
https://github.com/qemu/qemu/commit/8dd163f915cf26277fa175476c0af6898b8fd864
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700
Currently, ASPEED_DEV_SPI_BOOT is set to "0x400000000", which is the DRAM start
address, and the QEMU loader is used to load the U-Boot binary into this
address.
However, if users want to install FMC flash contents as a boot ROM, the DRAM
address 0x400000000 would be overwritten with Boot ROM data. This causes the
AST2700 to fail to boot because the U-Boot data becomes incorrect.
To fix this, change the ASPEED_DEV_SPI_BOOT address to "0x100000000", which is
the FMC0 memory-mapped start address in the AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c5728c3488b936e1cef5d4d83d26df853f8fac6b
https://github.com/qemu/qemu/commit/c5728c3488b936e1cef5d4d83d26df853f8fac6b
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Support setting different memory size
According to the AST2700 datasheet, the INTC(CPU DIE) controller has 16KB
(0x4000) of register space, and the INTCIO (I/O DIE) controller has 1KB (0x400)
of register space.
Introduced a new class attribute "mem_size" to set different memory sizes for
the INTC models in AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 0cffaace0565b68a354c67f147bf8f0f438726e1
https://github.com/qemu/qemu/commit/0cffaace0565b68a354c67f147bf8f0f438726e1
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity
Rename the variables "status_addr" to "status_reg" and "addr" to "reg" because
they are used as register index. This change makes the code more appropriate
and improves readability.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 563afea0aebd15eac74b89467204f4b76b2ee6fa
https://github.com/qemu/qemu/commit/563afea0aebd15eac74b89467204f4b76b2ee6fa
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Introduce dynamic allocation for regs array
Currently, the size of the "regs" array is 0x2000, which is too large. To save
code size and avoid mapping large unused gaps, will update it to only map the
useful set of registers. This update will support multiple sub-regions with
different sizes.
To address the redundant size issue, replace the static "regs" array with a
dynamically allocated "regs" memory.
Introduce a new "aspeed_intc_unrealize" function to free the allocated "regs"
memory.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b008465d655ff3ff314fe1ef81031293b582ebaf
https://github.com/qemu/qemu/commit/b008465d655ff3ff314fe1ef81031293b582ebaf
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Support setting different register size
Currently, the size of the regs array is 0x2000, which is too large. So far,
it only use GICINT128 - GICINT134, and the offsets from 0 to 0x1000 are unused.
To save code size, introduce a new class attribute "reg_size" to set the
different register sizes for the INTC models in AST2700 and add a regs
sub-region in the memory container.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 7ffee511fcf1487e016ae1d11c5e191557a8b804
https://github.com/qemu/qemu/commit/7ffee511fcf1487e016ae1d11c5e191557a8b804
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Reduce regs array size by adding a register sub-region
Currently, the size of the "regs" array is 0x2000, which is too large. So far,
it only uses "GICINT128 to `GICINT134", and the offsets from 0 to 0x1000 are
unused. To save code size and avoid mapping large unused gaps, update to only
map the useful set of registers:
INTC register [0x1000 – 0x1804]
Update "reg_size" to 0x808. Introduce a new class attribute "reg_offset" to set
the start offset of a "INTC" sub-region. Set the "reg_offset" to 0x1000 for INTC
registers.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3d6e15eafb3a3977f6659211e08d112807f20626
https://github.com/qemu/qemu/commit/3d6e15eafb3a3977f6659211e08d112807f20626
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Introduce helper functions for enable and status registers
The behavior of the enable and status registers is almost identical between
INTC(CPU Die) and INTCIO(IO Die). To reduce duplicated code, adds
"aspeed_intc_enable_handler" functions to handle enable register write
behavior and "aspeed_intc_status_handler" functions to handle status
register write behavior. No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 49da40cf5ffca090f6918ba882db8fb9536792a7
https://github.com/qemu/qemu/commit/49da40cf5ffca090f6918ba882db8fb9536792a7
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/aspeed: Add object type name to trace events for better debugging
Currently, these trace events only refer to INTC. To simplify the INTC model,
both INTC(CPU Die) and INTCIO(IO Die) will share the same helper functions.
However, it is difficult to recognize whether these trace events are comes from
INTC or INTCIO. To make these trace events more readable, adds object type name
to the INTC trace events.
Update trace events to include the "name" field for better identification.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: de4e979973ce5c09d0b9a6d8a7aa17ab77c869c8
https://github.com/qemu/qemu/commit/de4e979973ce5c09d0b9a6d8a7aa17ab77c869c8
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0
Currently, AST2700 SoC only supports A0. To support AST2700 A1, rename its IRQ
table and machine name.
To follow the machine deprecation rule, the initial machine "ast2700-evb" is
aliased to "ast2700a0-evb." In the future, we will alias "ast2700-evb" to new
SoCs, such as "ast2700a1-evb."
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 617cacefb7f7062f026994a256f8798d767cff73
https://github.com/qemu/qemu/commit/617cacefb7f7062f026994a256f8798d767cff73
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number
To improve readability, sort the IRQ table by IRQ number.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 28194d5d15b92f0b3f6628236f93001c3fdd0d39
https://github.com/qemu/qemu/commit/28194d5d15b92f0b3f6628236f93001c3fdd0d39
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Support different memory region ops
The previous implementation set the "aspeed_intc_ops" struct, containing read
and write callbacks, to be used when I/O is performed on the INTC region.
Both "aspeed_intc_read" and "aspeed_intc_write" callback functions were used
for INTC (CPU Die).
To support the INTCIO (IO Die) model, introduces a new "reg_ops" class
attribute. This allows setting different memory region operations to support
different INTC models.
Will introduce "aspeed_intcio_read" and "aspeed_intcio_write" callback
functions are used for INTCIO.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 63f3618f9be0f28ff36cd4b5685877715b97e669
https://github.com/qemu/qemu/commit/63f3618f9be0f28ff36cd4b5685877715b97e669
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Rename num_ints to num_inpins for clarity
To support AST2700 A1, some registers of the INTC(CPU Die) support one input
pin to multiple output pins. Renamed "num_ints" to "num_inpins" in the INTC
controller code for better clarity and consistency in naming conventions.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 35c909cd80d4095690bb1c98c263b01d9617de65
https://github.com/qemu/qemu/commit/35c909cd80d4095690bb1c98c263b01d9617de65
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Add support for multiple output pins in INTC
Added support for multiple output pins in the INTC controller to
accommodate the AST2700 A1.
Introduced "num_outpins" to represent the number of output pins. Updated the
IRQ handling logic to initialize and connect output pins separately from input
pins. Modified the "aspeed_soc_ast2700_realize" function to connect source
orgates to INTC and INTC to GIC128 - GIC136. Updated the "aspeed_intc_realize"
function to initialize output pins.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c6c5e63d46add459732d8d8d3b84bd5d26dff0ad
https://github.com/qemu/qemu/commit/c6c5e63d46add459732d8d8d3b84bd5d26dff0ad
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M hw/intc/trace-events
Log Message:
-----------
hw/intc/aspeed: Refactor INTC to support separate input and output pin indices
Refactors the INTC to distinguish between input and output pin indices,
improving interrupt handling clarity and accuracy.
Updated the functions to handle both input and output pin indices.
Added detailed logging for input and output pin indices in trace events.
These changes ensure that the INTC controller can handle multiple input and
output pins, improving support for the AST2700 A1.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ab24c6a2df8e6c8055b6f1dfe80697320b327c50
https://github.com/qemu/qemu/commit/ab24c6a2df8e6c8055b6f1dfe80697320b327c50
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and
register address
The INTC controller supports GICINT128 to GICINT136, mapping 1:1 to input and
output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was used to
derive the IRQ index numbers.
However, the INTC controller also supports GICINT192_201, mapping 1 input IRQ
pin to 10 output IRQ pins. The pin numbers for input and output are different.
It is difficult to use a formula to determine the index number of INTC model
supported input and output IRQs.
To simplify and improve readability, introduces the AspeedINTCIRQ structure to
save the input/output IRQ index and its enable/status register address.
Introduce the "aspeed_2700_intc_irqs" table to store IRQ information for INTC.
Introduce the "aspeed_intc_get_irq" function to retrieve the input/output IRQ
pin index from the provided status/enable register address.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5824e8bf6beb226aa5dee94d4e92b671e9b082f1
https://github.com/qemu/qemu/commit/5824e8bf6beb226aa5dee94d4e92b671e9b082f1
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
Log Message:
-----------
hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
The behavior of the INTC set IRQ is almost identical between INTC and INTCIO.
To reduce duplicated code, introduce the "aspeed_intc_set_irq_handler" function
to handle both INTC and INTCIO IRQ behavior. No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9178ff91f3105d25fef8e595014fbdfba7d9e278
https://github.com/qemu/qemu/commit/9178ff91f3105d25fef8e595014fbdfba7d9e278
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M hw/intc/trace-events
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
This update introduces support for handling multi-output IRQs in the AST2700
interrupt controller (INTC), specifically for GICINT192_201. GICINT192_201 maps
1:10 to input IRQ 0 and output IRQs 0 to 9. Each status bit corresponds to a
specific IRQ.
Implemented "aspeed_intc_set_irq_handler_multi_outpins" to handle IRQs with
multiple output pins. Introduced "aspeed_intc_status_handler_multi_outpins"
for managing status registers associated with multi-output IRQs.
Added new IRQ definitions for GICINT192_201 in INTC.
Adjusted the IRQ array to accommodate 10 input pins and 19 output pins,
aligning with the new GICINT192_201 mappings.
|------------------------------|
| INTC |
|inpin[0:0]--------->outpin[0] |
|inpin[0:1]--------->outpin[1] |
|inpin[0:2]--------->outpin[2] |
|inpin[0:3]--------->outpin[3] |
orgates[0]-------> |inpin[0:4]--------->outpin[4] |
|inpin[0:5]--------->outpin[5] |
|inpin[0:6]--------->outpin[6] |
|inpin[0:7]--------->outpin[7] |
|inpin[0:8]--------->outpin[8] |
|inpin[0:9]--------->outpin[9] |
| |
orgates[1]------> |inpin[1]----------->outpin[10]|
orgates[2]------> |inpin[2]----------->outpin[11]|
orgates[3]------> |inpin[3]----------->outpin[12]|
orgates[4]------> |inpin[4]----------->outpin[13]|
orgates[5]------> |inpin[5]----------->outpin[14]|
orgates[6]------> |inpin[6]----------->outpin[15]|
orgates[7]------> |inpin[7]----------->outpin[16]|
orgates[8]------> |inpin[8]----------->outpin[17]|
orgates[9]------> |inpin[9]----------->outpin[18]|
|------------------------------|
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 38ba38d87df3421ee0b28f9dfaf393456861a8e0
https://github.com/qemu/qemu/commit/38ba38d87df3421ee0b28f9dfaf393456861a8e0
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/intc/aspeed_intc.c
M include/hw/intc/aspeed_intc.h
Log Message:
-----------
hw/intc/aspeed: Add Support for AST2700 INTCIO Controller
Introduce a new ast2700 INTCIO class to support AST2700 INTCIO.
Added new register definitions for INTCIO, including enable and status
registers for IRQs GICINT192 through GICINT197.
Created a dedicated IRQ array for INTCIO, supporting six input pins and six
output pins, aligning with the newly defined registers.
Implemented "aspeed_intcio_read" and "aspeed_intcio_write" to handle
INTCIO-specific register access.
To GICINT196
|
ETH1 |-----------| |--------------------------|
-------->|0 | | INTCIO |
ETH2 | 4| orgates[0]------>|inpin[0]-------->outpin[0]|
-------->|1 5| orgates[1]------>|inpin[1]-------->outpin[1]|
ETH3 | 6| orgates[2]------>|inpin[2]-------->outpin[2]|
-------->|2 19| orgates[3]------>|inpin[3]-------->outpin[3]|
UART0 | 20|-->orgates[4]------>|inpin[4]-------->outpin[4]|
-------->|7 21| orgates[5]------>|inpin[5]-------->outpin[5]|
UART1 | 22| |--------------------------|
-------->|8 23|
UART2 | 24|
-------->|9 25|
UART3 | 26|
---------|10 27|
UART5 | 28|
-------->|11 29|
UART6 | |
-------->|12 30|
UART7 | 31|
-------->|13 |
UART8 | OR[0:31] |
-------->|14 |
UART9 | |
-------->|15 |
UART10 | |
-------->|16 |
UART11 | |
-------->|17 |
UART12 | |
-------->|18 |
|-----------|
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d3b38cbbed845a650819af3ec59d5e463b3fe47a
https://github.com/qemu/qemu/commit/d3b38cbbed845a650819af3ec59d5e463b3fe47a
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/misc/aspeed_scu.c
M include/hw/misc/aspeed_scu.h
Log Message:
-----------
hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
Added new definitions for AST2700_A1_SILICON_REV and AST2750_A1_SILICON_REV to
identify the A1 silicon revisions.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d2c8093567b3681e4439702f129e89156f59afb5
https://github.com/qemu/qemu/commit/d2c8093567b3681e4439702f129e89156f59afb5
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping
Currently, these IRQ tables support from GIC 128 - 136 for AST2700 A0.
These IRQ tables can be reused for AST2700 A1 from GIC 192 - 197.
Updates the interrupt mapping to include support for AST2700 A1 by extending
the existing mappings to the new GIC range.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cd99eda62a5129305d186468f8056618d0b3bd87
https://github.com/qemu/qemu/commit/cd99eda62a5129305d186468f8056618d0b3bd87
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances
Updated Aspeed27x0SoCState to include an intc[2] array instead of a single
AspeedINTCState instance. Modified aspeed_soc_ast2700_get_irq and
aspeed_soc_ast2700_get_irq_index to correctly reference the corresponding
interrupt controller instance and OR gate index.
Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
GIC 192-201.
To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8107448de709a64362c56687764fbd41587c9de9
https://github.com/qemu/qemu/commit/8107448de709a64362c56687764fbd41587c9de9
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
The design of INTC controllers has significantly changed in AST2700 A1.
There are a total of 480 interrupt sources in AST2700 A1. For interrupt numbers
from 0 to 127, they can route directly to PSP, SSP, and TSP. Due to the
limitation of interrupt numbers of processors, the interrupts are merged every
32 sources for interrupt numbers greater than 127.
There are two levels of interrupt controllers, INTC(CPUD Die) and INTCIO
(IO Die). The interrupt sources of INTC are the interrupt numbers from INTC_0 to
INTC_127 and interrupts from INTCIO. The interrupt sources of INTCIO are the
interrupt numbers greater than INTC_127. INTC_IO controls the interrupts
INTC_128 to INTC_319 only.
Currently, only GIC 192 to 201 are supported, and their source interrupts are
from INTCIO and connected to INTC at input pin 0 and output pins 0 to 9 for
GIC 192-201.
The design of the orgates for GICINT 196 is as follows:
It has interrupt sources ranging from 0 to 31, with its output pin connected to
INTCIO "T0 GICINT_196". The output pin is then connected to INTC "GIC_192_201"
at bit 4, and its bit 4 output should be connected to GIC 196.
The design of INTC GIC_192_201 have 10 output pins, mapped as following:
Bit 0 -> GIC 192
Bit 1 -> GIC 193
Bit 2 -> GIC 194
Bit 3 -> GIC 195
Bit 4 -> GIC 196
To support both AST2700 A1 and A0, INTC input pins 1 to 9 and output pins
10 to 18 remain to support GIC 128-136, which source interrupts from INTC.
These will be removed if we decide not to support AST2700 A0 in the future.
|-------------------------------------------------------------------------------------------------------|
| AST2700 A1 Design
|
| To GICINT196
|
|
|
| ETH1 |-----------| |--------------------------|
|--------------| |
| -------->|0 | | INTCIO |
| orgates[0] | |
| ETH2 | 4|
orgates[0]------>|inpin[0]-------->outpin[0]|------->| 0 | |
| -------->|1 5|
orgates[1]------>|inpin[1]-------->outpin[1]|------->| 1 | |
| ETH3 | 6|
orgates[2]------>|inpin[2]-------->outpin[2]|------->| 2 | |
| -------->|2 19|
orgates[3]------>|inpin[3]-------->outpin[3]|------->| 3 OR[0:9] |-----| |
| UART0 |
20|-->orgates[4]------>|inpin[4]-------->outpin[4]|------->| 4 |
| |
| -------->|7 21|
orgates[5]------>|inpin[5]-------->outpin[5]|------->| 5 | | |
| UART1 | 22|
orgates[6]------>|inpin[6]-------->outpin[6]|------->| 6 | | |
| -------->|8 23|
orgates[7]------>|inpin[7]-------->outpin[7]|------->| 7 | | |
| UART2 | 24|
orgates[8]------>|inpin[8]-------->outpin[8]|------->| 8 | | |
| -------->|9 25|
orgates[9]------>|inpin[9]-------->outpin[9]|------->| 9 | | |
| UART3 | 26| |--------------------------|
|--------------| | |
| ---------|10 27|
| |
| UART5 | 28|
| |
| -------->|11 29|
| |
| UART6 | |
| |
| -------->|12 30|
|-----------------------------------------------------------------------| |
| UART7 | 31| |
|
| -------->|13 | |
|
| UART8 | OR[0:31] | | |------------------------------|
|----------| |
| -------->|14 | | | INTC |
| GIC | |
| UART9 | | | |inpin[0:0]--------->outpin[0]
|---------->|192 | |
| -------->|15 | | |inpin[0:1]--------->outpin[1]
|---------->|193 | |
| UART10 | | | |inpin[0:2]--------->outpin[2]
|---------->|194 | |
| -------->|16 | | |inpin[0:3]--------->outpin[3]
|---------->|195 | |
| UART11 | | |--------------> |inpin[0:4]--------->outpin[4]
|---------->|196 | |
| -------->|17 | |inpin[0:5]--------->outpin[5]
|---------->|197 | |
| UART12 | | |inpin[0:6]--------->outpin[6]
|---------->|198 | |
| -------->|18 | |inpin[0:7]--------->outpin[7]
|---------->|199 | |
| |-----------| |inpin[0:8]--------->outpin[8]
|---------->|200 | |
| |inpin[0:9]--------->outpin[9]
|---------->|201 | |
|-------------------------------------------------------------------------------------------------------|
|-------------------------------------------------------------------------------------------------------|
| ETH1 |-----------|
orgates[1]------->|inpin[1]----------->outpin[10]|---------->|128 | |
| -------->|0 |
orgates[2]------->|inpin[2]----------->outpin[11]|---------->|129 | |
| ETH2 | 4|
orgates[3]------->|inpin[3]----------->outpin[12]|---------->|130 | |
| -------->|1 5|
orgates[4]------->|inpin[4]----------->outpin[13]|---------->|131 | |
| ETH3 |
6|---->orgates[5]------->|inpin[5]----------->outpin[14]|---------->|132
| |
| -------->|2 19|
orgates[6]------->|inpin[6]----------->outpin[15]|---------->|133 | |
| UART0 | 20|
orgates[7]------->|inpin[7]----------->outpin[16]|---------->|134 | |
| -------->|7 21|
orgates[8]------->|inpin[8]----------->outpin[17]|---------->|135 | |
| UART1 | 22|
orgates[9]------->|inpin[9]----------->outpin[18]|---------->|136 | |
| -------->|8 23| |------------------------------|
|----------| |
| UART2 | 24|
|
| -------->|9 25| AST2700 A0 Design
|
| UART3 | 26|
|
| -------->|10 27|
|
| UART5 | 28|
|
| -------->|11 29| GICINT132
|
| UART6 | |
|
| -------->|12 30|
|
| UART7 | 31|
|
| -------->|13 |
|
| UART8 | OR[0:31] |
|
| -------->|14 |
|
| UART9 | |
|
| -------->|15 |
|
| UART10 | |
|
| -------->|16 |
|
| UART11 | |
|
| -------->|17 |
|
| UART12 | |
|
| -------->|18 |
|
| |-----------|
|
|
|
|-------------------------------------------------------------------------------------------------------|
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6de4aa8dc54451e5902658648fd3d268284c45e9
https://github.com/qemu/qemu/commit/6de4aa8dc54451e5902658648fd3d268284c45e9
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1
The memory map for AST2700 A1 remains compatible with AST2700 A0. However, the
IRQ mapping has been updated for AST2700 A1, with GIC interrupts now ranging
from 192 to 201. Add a new IRQ map table for AST2700 A1.
Add "aspeed_soc_ast2700a1_class_init" to initialize the AST2700 A1 SoC.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
[ clg: Removed sc->name ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 498c519eb7761b09adf2d2e863cf4a70b186005f
https://github.com/qemu/qemu/commit/498c519eb7761b09adf2d2e863cf4a70b186005f
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Add Machine Support for AST2700 A1
Introduce "aspeed_machine_ast2700a1_evb_class_init" to initialize the
AST2700 A1 EVB.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ecc1a4e966b5d4ce1732ee223eaf40ef37e9a30b
https://github.com/qemu/qemu/commit/ecc1a4e966b5d4ce1732ee223eaf40ef37e9a30b
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
Log Message:
-----------
hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address
To improve readability, sort the memmap table by mapping address
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 827eecb0e8d3cda71c5529909345acda266b2e6d
https://github.com/qemu/qemu/commit/827eecb0e8d3cda71c5529909345acda266b2e6d
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/test_aarch64_aspeed.py
Log Message:
-----------
tests/functional/aspeed: Introduce start_ast2700_test API
Added a new method "start_ast2700_test" to the "AST2x00MachineSDK" class and
this method centralizes the logic for starting the AST2700 test, making it
reusable for different test cases.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8241d6f8d5b7a423dd4289b8140934d96819d019
https://github.com/qemu/qemu/commit/8241d6f8d5b7a423dd4289b8140934d96819d019
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/test_aarch64_aspeed.py
Log Message:
-----------
tests/functional/aspeed: Update temperature hwmon path
Modified the temperature hwmon path to use a wildcard to handle different SDK
versions: "cat /sys/bus/i2c/devices/1-004d/hwmon/hwmon*/temp1_input".
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c77ec95a4b51ed36156c94e06fac056d3dd620b2
https://github.com/qemu/qemu/commit/c77ec95a4b51ed36156c94e06fac056d3dd620b2
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/test_aarch64_aspeed.py
Log Message:
-----------
tests/functional/aspeed: Update test ASPEED SDK v09.05
In ASPEED SDK v09.05, the naming convention for pre-built images has been
updated. The pre-built image for AST2700 A0 has been renamed to
ast2700-a0-default, while ast2700-default is now used for AST2700 A1.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2cab06e930cb724bd8ea7ce7ff0e1f362b41344d
https://github.com/qemu/qemu/commit/2cab06e930cb724bd8ea7ce7ff0e1f362b41344d
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M tests/functional/test_aarch64_aspeed.py
Log Message:
-----------
tests/functional/aspeed: Add test case for AST2700 A1
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5ab179db11ca297c9e89a6d57f954d31965cbd7b
https://github.com/qemu/qemu/commit/5ab179db11ca297c9e89a6d57f954d31965cbd7b
Author: Jamin Lin <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
A docs/specs/aspeed-intc.rst
M docs/specs/index.rst
Log Message:
-----------
docs/specs: Add aspeed-intc
Add AST2700 INTC design guidance and its block diagram.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c9ce8a1ffdedbc55d107c4b5629eca5d1e219165
https://github.com/qemu/qemu/commit/c9ce8a1ffdedbc55d107c4b5629eca5d1e219165
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M linux-user/mmap.c
M linux-user/syscall.c
M linux-user/user-internals.h
Log Message:
-----------
linux-user: Only include 'exec/tb-flush.h' header when necessary
Very few source files require to access "exec/tb-flush.h"
declarations, and except a pair, they all include it
explicitly. No need to overload the generic "user-internals.h".
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Ilya Leoshkevich <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-Id: <[email protected]>
Commit: 019b4e84eda27a006f94ed0faa024babd0a97e97
https://github.com/qemu/qemu/commit/019b4e84eda27a006f94ed0faa024babd0a97e97
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M bsd-user/mmap.c
Log Message:
-----------
bsd-user: Always use mmap_find_vma_aligned() in target_mmap()
Massage target_mmap(): calculate alignment once, then
unconditionally call mmap_find_vma_aligned().
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Warner Losh <[email protected]>
Message-Id: <[email protected]>
Commit: 84d66261bef3cdfea3bd1fb052a7ba38abb34b18
https://github.com/qemu/qemu/commit/84d66261bef3cdfea3bd1fb052a7ba38abb34b18
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M bsd-user/qemu.h
Log Message:
-----------
bsd-user: Propagate alignment argument to mmap_find_vma()
Propagate the alignment to mmap_find_vma(), effectively
embedding mmap_find_vma_aligned() within mmap_find_vma().
Add a comment in do_bsd_shmat() to clarify alignment above
page size is not required.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Warner Losh <[email protected]>
Message-Id: <[email protected]>
Commit: 1405d7e60d8c98a28b29885f70da4f2e4407fbc6
https://github.com/qemu/qemu/commit/1405d7e60d8c98a28b29885f70da4f2e4407fbc6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M bsd-user/qemu.h
A include/user/mmap.h
M linux-user/user-mmap.h
Log Message:
-----------
user: Extract common MMAP API to 'user/mmap.h'
Keep common MMAP-related declarations in a single place.
Note, this disable ThreadSafetyAnalysis on Linux for:
- mmap_fork_start()
- mmap_fork_end().
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Warner Losh <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: ca05578fc80f4253ed19f4c4128a4cbd5b83f0b5
https://github.com/qemu/qemu/commit/ca05578fc80f4253ed19f4c4128a4cbd5b83f0b5
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M cpu-target.c
M hw/core/cpu-system.c
M hw/core/cpu-user.c
M include/hw/core/cpu.h
Log Message:
-----------
cpus: Register VMState per user / system emulation
Simplify cpu-target.c by extracting mixed vmstate code
into the cpu_vmstate_register() / cpu_vmstate_unregister()
helpers, implemented in cpu-user.c and cpu-system.c.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 43610f3184f846da948e8ab9dbc0c5de1e9bde79
https://github.com/qemu/qemu/commit/43610f3184f846da948e8ab9dbc0c5de1e9bde79
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M cpu-target.c
M hw/core/cpu-common.c
Log Message:
-----------
cpus: Build cpu_exec_[un]realizefn() methods once
Now that cpu_exec_realizefn() and cpu_exec_unrealizefn()
methods don't use any target specific definition anymore,
we can move them to cpu-common.c to be able to build them
once.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 30e76638eb35ffe88e95cca2b5af952c14dc336d
https://github.com/qemu/qemu/commit/30e76638eb35ffe88e95cca2b5af952c14dc336d
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M cpu-common.c
M hw/core/cpu-common.c
M hw/core/cpu-system.c
M include/hw/core/cpu.h
Log Message:
-----------
cpus: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: e27fa95fb9d1dd4668e8b1411b47df14253e47fa
https://github.com/qemu/qemu/commit/e27fa95fb9d1dd4668e8b1411b47df14253e47fa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M accel/accel-target.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M accel/tcg/watchpoint.c
Log Message:
-----------
accel: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 18b3abb7224f84364bee200a10413d6be2a1c4c9
https://github.com/qemu/qemu/commit/18b3abb7224f84364bee200a10413d6be2a1c4c9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M bsd-user/signal.c
M linux-user/alpha/target_proc.h
M linux-user/signal.c
Log Message:
-----------
user: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4c5c410ceb4e039a49a120a436cc6183831a778b
https://github.com/qemu/qemu/commit/4c5c410ceb4e039a49a120a436cc6183831a778b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M disas/disas-common.c
Log Message:
-----------
disas: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0368d8d189af0444cd818f4f695beb1d94706f44
https://github.com/qemu/qemu/commit/0368d8d189af0444cd818f4f695beb1d94706f44
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M gdbstub/gdbstub.c
M gdbstub/system.c
M gdbstub/user-target.c
M gdbstub/user.c
Log Message:
-----------
gdbstub: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Acked-by: Alex Bennée <[email protected]>
Message-Id: <[email protected]>
Commit: bd7d74283464491b461bb1136e69963962fd05aa
https://github.com/qemu/qemu/commit/bd7d74283464491b461bb1136e69963962fd05aa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/acpi/cpu.c
M hw/acpi/cpu_hotplug.c
Log Message:
-----------
hw/acpi: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0ebdf989c32031019aa0974dbb6b840fca52991e
https://github.com/qemu/qemu/commit/0ebdf989c32031019aa0974dbb6b840fca52991e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
Log Message:
-----------
target/arm: Prefer cached CpuClass over CPU_GET_CLASS() macro
CpuState caches its CPUClass since commit 6fbdff87062
("cpu: cache CPUClass in CPUState for hot code paths"),
use it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: c0ee4dd1552b73bdde90875ce62e036a3ca8a007
https://github.com/qemu/qemu/commit/c0ee4dd1552b73bdde90875ce62e036a3ca8a007
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M include/hw/core/cpu.h
Log Message:
-----------
cpus: Restrict cpu_has_work() to system emulation
This method is not used on user emulation, because there
is always work to do there.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 8f8dbe04bdafdbe265e9ae25737bb18daacc6ca6
https://github.com/qemu/qemu/commit/8f8dbe04bdafdbe265e9ae25737bb18daacc6ca6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/core/cpu-system.c
M include/hw/core/cpu.h
Log Message:
-----------
cpus: Un-inline cpu_has_work()
In order to expand cpu_has_work(), un-inline it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 72eacd623170dd680557ece6957575c30774cdef
https://github.com/qemu/qemu/commit/72eacd623170dd680557ece6957575c30774cdef
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/core/cpu-system.c
M include/accel/tcg/cpu-ops.h
M include/hw/core/sysemu-cpu-ops.h
Log Message:
-----------
cpus: Introduce SysemuCPUOps::has_work() handler
SysemuCPUOps::has_work() is similar to CPUClass::has_work(),
but only exposed on system emulation.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 35e0769d3f341f9a3fc1de104ac57a3d1080d3e2
https://github.com/qemu/qemu/commit/35e0769d3f341f9a3fc1de104ac57a3d1080d3e2
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/alpha/cpu.c
Log Message:
-----------
target/alpha: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f5e67b6ddad2262fd692caeb6090fa138241306f
https://github.com/qemu/qemu/commit/f5e67b6ddad2262fd692caeb6090fa138241306f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6c8d41eab6d1774105562329eea3a731dd267c5c
https://github.com/qemu/qemu/commit/6c8d41eab6d1774105562329eea3a731dd267c5c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/avr/cpu.c
Log Message:
-----------
target/avr: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 7ec1c634215527782ff508dd88f5bb4e324a3d7f
https://github.com/qemu/qemu/commit/7ec1c634215527782ff508dd88f5bb4e324a3d7f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/hexagon/cpu.c
Log Message:
-----------
target/hexagon: Remove CPUClass:has_work() handler
Remove as unreachable code.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Brian Cain <[email protected]>
Message-Id: <[email protected]>
Commit: 91231d99acec93dc62a524868199801395c9f69a
https://github.com/qemu/qemu/commit/91231d99acec93dc62a524868199801395c9f69a
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/hppa/cpu.c
Log Message:
-----------
target/hppa: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f0bef005712d55463904760533a12480880d9a1e
https://github.com/qemu/qemu/commit/f0bef005712d55463904760533a12480880d9a1e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Move has_work() from CPUClass to SysemuCPUOps
Move has_work() from CPUClass to SysemuCPUOps,
restrict x86_cpu_pending_interrupt() to system.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 87969d6681ac2837cd6c8ce1724a305011f770d9
https://github.com/qemu/qemu/commit/87969d6681ac2837cd6c8ce1724a305011f770d9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/loongarch/cpu.c
Log Message:
-----------
target/loongarch: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4a119cfc6cd7affc07d4b76c1340cf96b6ff0268
https://github.com/qemu/qemu/commit/4a119cfc6cd7affc07d4b76c1340cf96b6ff0268
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/m68k/cpu.c
Log Message:
-----------
target/m68k: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 55f29126b6f980f759e0bdab2e83361b98232305
https://github.com/qemu/qemu/commit/55f29126b6f980f759e0bdab2e83361b98232305
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/microblaze/cpu.c
Log Message:
-----------
target/microblaze: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 85edafe385f538ce3a84ed478faea12e28ab1720
https://github.com/qemu/qemu/commit/85edafe385f538ce3a84ed478faea12e28ab1720
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/mips/cpu.c
M target/mips/internal.h
Log Message:
-----------
target/mips: Move has_work() from CPUClass to SysemuCPUOps
Move has_work() from CPUClass to SysemuCPUOps and
cpu_mips_hw_interrupts_enabled() to system.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6a2b2943145c1dcb44091afa993de6d01824190b
https://github.com/qemu/qemu/commit/6a2b2943145c1dcb44091afa993de6d01824190b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/openrisc/cpu.c
Log Message:
-----------
target/openrisc: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 71e950afe2b9cc43d1c4186c40c1aa0dced1077d
https://github.com/qemu/qemu/commit/71e950afe2b9cc43d1c4186c40c1aa0dced1077d
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 3810e17173c3c1848f44c4fccf0160477a399dab
https://github.com/qemu/qemu/commit/3810e17173c3c1848f44c4fccf0160477a399dab
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/riscv/cpu.c
M target/riscv/internals.h
Log Message:
-----------
target/riscv: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 52df41e3536865ee3bea1bd22426b3cb84186165
https://github.com/qemu/qemu/commit/52df41e3536865ee3bea1bd22426b3cb84186165
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/rx/cpu.c
Log Message:
-----------
target/rx: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0df9781074cab07dcb526b6e83bd0570eab3afe8
https://github.com/qemu/qemu/commit/0df9781074cab07dcb526b6e83bd0570eab3afe8
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/s390x/s390x-internal.h
Log Message:
-----------
target/s390x: Restrict I/O handler installers to system emulation
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f54c047e866802aa9c82f226dbb6b2542c4ff245
https://github.com/qemu/qemu/commit/f54c047e866802aa9c82f226dbb6b2542c4ff245
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/s390x/cpu-system.c
M target/s390x/cpu.c
M target/s390x/interrupt.c
M target/s390x/s390x-internal.h
Log Message:
-----------
target/s390x: Move has_work() from CPUClass to SysemuCPUOps
Move has_work() from CPUClass to SysemuCPUOps, move
s390_cpu_has_work() to cpu-system.c so it is only build
for system emulation binaries, restrict functions not
used anymore on user emulation in interrupt.c.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 644a8119bd54b075029acf7fad7740afb4fe9e63
https://github.com/qemu/qemu/commit/644a8119bd54b075029acf7fad7740afb4fe9e63
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/sh4/cpu.c
Log Message:
-----------
target/sh4: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 82f0f44d62b3faacc447a68d05f3b58d3567ec5b
https://github.com/qemu/qemu/commit/82f0f44d62b3faacc447a68d05f3b58d3567ec5b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/sparc/cpu.c
Log Message:
-----------
target/sparc: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: d55ea95f256f1300edea837136f2a3841d20c588
https://github.com/qemu/qemu/commit/d55ea95f256f1300edea837136f2a3841d20c588
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/tricore/cpu.c
Log Message:
-----------
target/tricore: Move has_work() from CPUClass to SysemuCPUOps
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f37799c6c1d2e8fb43f5e1f100f26c5401d9b3ff
https://github.com/qemu/qemu/commit/f37799c6c1d2e8fb43f5e1f100f26c5401d9b3ff
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M target/xtensa/cpu.c
Log Message:
-----------
target/xtensa: Move has_work() from CPUClass to SysemuCPUOps
Move has_work() from CPUClass to SysemuCPUOps, simplifying
xtensa_cpu_has_work() by directly using CPU env.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: d0a4ccae953b7482a682b9b9f8619804059ecc89
https://github.com/qemu/qemu/commit/d0a4ccae953b7482a682b9b9f8619804059ecc89
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M hw/core/cpu-common.c
M hw/core/cpu-system.c
M hw/core/cpu-user.c
M include/hw/core/cpu.h
M include/hw/core/sysemu-cpu-ops.h
Log Message:
-----------
cpus: Remove CPUClass::has_work() handler
All handlers have been converted to SysemuCPUOps::has_work().
Remove CPUClass::has_work along with cpu_common_has_work() and
simplify cpu_has_work(), making SysemuCPUOps::has_work handler
mandatory.
Note, since cpu-common.c is in meson's common_ss[] source set, we
must define cpu_exec_class_post_init() in cpu-target.c (which is
in the specific_ss[] source set) to have CONFIG_USER_ONLY defined.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Commit: 8ff6ff09b9890ba390395d7510eca1025f7284df
https://github.com/qemu/qemu/commit/8ff6ff09b9890ba390395d7510eca1025f7284df
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-03-09 (Sun, 09 Mar 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Consolidate core exec/vCPU handling section
Some common cpu/exec files are listed under the 'TCG CPUs'
section. Move them to the generic 'Overall Guest CPU Cores'
one where they belong.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 1843a0c01d06049f517fea7e155e5236e7287276
https://github.com/qemu/qemu/commit/1843a0c01d06049f517fea7e155e5236e7287276
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-10 (Mon, 10 Mar 2025)
Changed paths:
M docs/devel/rust.rst
M meson.build
M meson_options.txt
M rust/Cargo.toml
M rust/hw/char/pl011/src/device.rs
M rust/hw/char/pl011/src/lib.rs
A rust/hw/char/pl011/src/registers.rs
M rust/hw/timer/hpet/src/hpet.rs
M rust/qemu-api-macros/src/lib.rs
M rust/qemu-api/meson.build
M rust/qemu-api/src/bindings.rs
M rust/qemu-api/src/cell.rs
M rust/qemu-api/src/chardev.rs
M rust/qemu-api/src/irq.rs
M rust/qemu-api/src/memory.rs
M rust/qemu-api/src/prelude.rs
M rust/qemu-api/src/qdev.rs
M rust/qemu-api/src/qom.rs
M rust/qemu-api/src/sysbus.rs
M rust/qemu-api/src/timer.rs
M rust/qemu-api/src/vmstate.rs
M rust/qemu-api/src/zeroable.rs
M rust/qemu-api/tests/tests.rs
M scripts/meson-buildoptions.py
M scripts/meson-buildoptions.sh
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* scripts: dump stdin on meson-buildoptions error
* rust: introduce qemu_api::cell::Opaque<>
* rust: express pinning requirements for timers
* rust: hpet: decode HPET registers into enums
* rust: cell: add full example of declaring a SysBusDevice
* rust: qom: remove operations on &mut
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# gpg: Signature made Sun 09 Mar 2025 18:29:16 HKT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [full]
# gpg: aka "Paolo Bonzini <[email protected]>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (25 commits)
rust: pl011: Allow NULL chardev argument to pl011_create()
meson.build: default to -gsplit-dwarf for debug info
rust: qom: remove operations on &mut
rust: cell: add full example of declaring a SysBusDevice
rust: hpet: decode HPET registers into enums
rust: pl011: pass around registers::Data
rust: pl011: switch to safe chardev operation
rust: pl011: clean up visibilities of callbacks
rust: pl011: move register definitions out of lib.rs
rust: chardev: provide basic bindings to character devices
rust: bindings: remove more unnecessary Send/Sync impls
rust: chardev: wrap Chardev with Opaque<>
rust: memory: wrap MemoryRegion with Opaque<>
rust: sysbus: wrap SysBusDevice with Opaque<>
rust: hpet: do not access fields of SysBusDevice
rust: qdev: wrap Clock and DeviceState with Opaque<>
rust: qom: wrap Object with Opaque<>
rust: irq: wrap IRQState with Opaque<>
rust: timer: wrap QEMUTimer with Opaque<> and express pinning requirements
rust: hpet: embed Timer without the Option and Box indirection
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 2e14ac3c9ca25c974bb300c45c5b0303862c177d
https://github.com/qemu/qemu/commit/2e14ac3c9ca25c974bb300c45c5b0303862c177d
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-10 (Mon, 10 Mar 2025)
Changed paths:
A docs/specs/aspeed-intc.rst
M docs/specs/index.rst
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0.c
M hw/intc/aspeed_intc.c
M hw/intc/trace-events
M hw/misc/aspeed_hace.c
M hw/misc/aspeed_scu.c
M include/hw/arm/aspeed_soc.h
M include/hw/intc/aspeed_intc.h
M include/hw/misc/aspeed_hace.h
M include/hw/misc/aspeed_scu.h
M tests/functional/aspeed.py
M tests/functional/meson.build
M tests/functional/test_aarch64_aspeed.py
A tests/functional/test_arm_aspeed_bletchley.py
M tests/functional/test_arm_aspeed_palmetto.py
M tests/functional/test_arm_aspeed_romulus.py
A tests/functional/test_arm_aspeed_witherspoon.py
Log Message:
-----------
Merge tag 'pull-aspeed-20250309' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Updated Aspeed OpenBMC functional test images
* Introduced functional tests for witherspoon and bletchley machines
* Added support for Non-maskable Interrupt on AST2700 SoC
* Fixed HW strapping on AST2700 SoC
* Added AST2700 HACE support
* Added AST2700 A1 SoC support
* Intoduced new ast2700a1-evb machine
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# gpg: Signature made Sun 09 Mar 2025 21:49:57 HKT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250309' of https://github.com/legoater/qemu: (46 commits)
docs/specs: Add aspeed-intc
tests/functional/aspeed: Add test case for AST2700 A1
tests/functional/aspeed: Update test ASPEED SDK v09.05
tests/functional/aspeed: Update temperature hwmon path
tests/functional/aspeed: Introduce start_ast2700_test API
hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address
hw/arm/aspeed: Add Machine Support for AST2700 A1
hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1
hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1
hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances
hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping
hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions
hw/intc/aspeed: Add Support for AST2700 INTCIO Controller
hw/intc/aspeed: Add Support for Multi-Output IRQ Handling
hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication
hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and
register address
hw/intc/aspeed: Refactor INTC to support separate input and output pin indices
hw/intc/aspeed: Add support for multiple output pins in INTC
hw/intc/aspeed: Rename num_ints to num_inpins for clarity
hw/intc/aspeed: Support different memory region ops
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 5136598e2667f35ef3dc1d757616a266bd5eb3a2
https://github.com/qemu/qemu/commit/5136598e2667f35ef3dc1d757616a266bd5eb3a2
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-10 (Mon, 10 Mar 2025)
Changed paths:
M MAINTAINERS
M accel/accel-target.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/translate-all.c
M accel/tcg/watchpoint.c
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M bsd-user/qemu.h
M bsd-user/signal.c
M cpu-common.c
M cpu-target.c
M disas/disas-common.c
M gdbstub/gdbstub.c
M gdbstub/system.c
M gdbstub/user-target.c
M gdbstub/user.c
M hw/acpi/cpu.c
M hw/acpi/cpu_hotplug.c
M hw/core/cpu-common.c
M hw/core/cpu-system.c
M hw/core/cpu-user.c
M include/accel/tcg/cpu-ops.h
M include/hw/core/cpu.h
M include/hw/core/sysemu-cpu-ops.h
A include/user/mmap.h
M linux-user/alpha/target_proc.h
M linux-user/mmap.c
M linux-user/signal.c
M linux-user/syscall.c
M linux-user/user-internals.h
M linux-user/user-mmap.h
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/tcg/cpu-v7m.c
M target/avr/cpu.c
M target/hexagon/cpu.c
M target/hppa/cpu.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/mips/internal.h
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/riscv/cpu.c
M target/riscv/internals.h
M target/rx/cpu.c
M target/s390x/cpu-system.c
M target/s390x/cpu.c
M target/s390x/interrupt.c
M target/s390x/s390x-internal.h
M target/sh4/cpu.c
M target/sparc/cpu.c
M target/tricore/cpu.c
M target/xtensa/cpu.c
Log Message:
-----------
Merge tag 'accel-cpus-20250309' of https://github.com/philmd/qemu into staging
Generic CPUs / accelerators patch queue
- Reduce "exec/tb-flush.h" inclusion on linux-user
- Consider alignment in bsd-user's mmap_find_vma()
- Unify MMAP common user emulation API
- Simplify cpu-target.c further
- Prefer cached CpuClass over CPU_GET_CLASS() macro
- Restrict CPU has_work() handlers to system emulation
- Consolidate core exec/vCPU section in MAINTAINERS
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# gpg: Signature made Mon 10 Mar 2025 01:50:16 HKT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>"
[full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'accel-cpus-20250309' of https://github.com/philmd/qemu: (38 commits)
MAINTAINERS: Consolidate core exec/vCPU handling section
cpus: Remove CPUClass::has_work() handler
target/xtensa: Move has_work() from CPUClass to SysemuCPUOps
target/tricore: Move has_work() from CPUClass to SysemuCPUOps
target/sparc: Move has_work() from CPUClass to SysemuCPUOps
target/sh4: Move has_work() from CPUClass to SysemuCPUOps
target/s390x: Move has_work() from CPUClass to SysemuCPUOps
target/s390x: Restrict I/O handler installers to system emulation
target/rx: Move has_work() from CPUClass to SysemuCPUOps
target/riscv: Move has_work() from CPUClass to SysemuCPUOps
target/ppc: Move has_work() from CPUClass to SysemuCPUOps
target/openrisc: Move has_work() from CPUClass to SysemuCPUOps
target/mips: Move has_work() from CPUClass to SysemuCPUOps
target/microblaze: Move has_work() from CPUClass to SysemuCPUOps
target/m68k: Move has_work() from CPUClass to SysemuCPUOps
target/loongarch: Move has_work() from CPUClass to SysemuCPUOps
target/i386: Move has_work() from CPUClass to SysemuCPUOps
target/hppa: Move has_work() from CPUClass to SysemuCPUOps
target/hexagon: Remove CPUClass:has_work() handler
target/avr: Move has_work() from CPUClass to SysemuCPUOps
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/d9a4282c4b69...5136598e2667
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