Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: cbb698a2ba568f9746dee00ed59c442787103674
https://github.com/qemu/qemu/commit/cbb698a2ba568f9746dee00ed59c442787103674
Author: Markus Armbruster <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M qapi/block-core.json
Log Message:
-----------
qapi/block-core: Improve x-blockdev-change documentation
The description of feature @unstable is three paragraphs. The second
and third became part of the description by accident in commit
9fb49daabfb (qapi: Mark unstable QMP parts with feature 'unstable').
The second paragraph describes a defect in terms of the
implementation. Fine, but doesn't belong into user-facing
documentation. Turn it into a TODO section.
Rewrite everything else for clarity and completeness.
Signed-off-by: Markus Armbruster <[email protected]>
Message-ID: <[email protected]>
Acked-by: Alberto Garcia <[email protected]>
Commit: 8fad36626009ef51b52f4cdf08e29cc66284e41d
https://github.com/qemu/qemu/commit/8fad36626009ef51b52f4cdf08e29cc66284e41d
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi_domain: isolate TYPE_CHECKING imports
When using the annotations feature, type hints do not need to be
imported at runtime, only at type check time. Move type-check-only
imports into a conditional to reduce the number of imports needed at
runtime.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: e36afc7bcc193da144f5d45c7c37eb62835b3ab1
https://github.com/qemu/qemu/commit/e36afc7bcc193da144f5d45c7c37eb62835b3ab1
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi-domain: always store fully qualified name in signode
Currently, only the definition name is stored in the tree metadata; but
the node property is confusingly called "fullname". Rectify this by
always storing the FQN in the tree metadata.
... While we're here, re-organize the code in preparation for namespace
support to make it a bit easier to add additional components of the
FQN. With this change, there is now extremely little code left that's
taken directly from the Python domain :)
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 74d40b011c27dc343ad56022a322d212135c96ed
https://github.com/qemu/qemu/commit/74d40b011c27dc343ad56022a322d212135c96ed
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi_domain: add namespace support to FQN
This patch adds a namespace component to the "Fully Qualified Name", in
the form of "domain:module.name". As there are no namespace directives
or options yet, this component will simply be empty as of this patch.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 9ca404f0043d63043bfed3af8da3adedc062cb13
https://github.com/qemu/qemu/commit/9ca404f0043d63043bfed3af8da3adedc062cb13
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/devel/qapi-domain.rst
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi-domain: add :namespace: override option
Akin to the :module: override option, the :namespace: options allows you
to forcibly override the contextual namespace associatied with a
definition.
We don't necessarily actually need this, but I felt compelled to stick
close to how the Python domain works that offers context overrides.
As of this commit, it is possible to add e.g. ":namespace: QMP" to any
QAPI directive to forcibly associate that definition with a given
namespace.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 7c7247b252dd8b3911b96451c0eaaebbc6ac0af0
https://github.com/qemu/qemu/commit/7c7247b252dd8b3911b96451c0eaaebbc6ac0af0
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/devel/qapi-domain.rst
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi-domain: add qapi:namespace directive
Add a new directive that marks the beginning of a QAPI "namespace", for
example; "QMP", "QGA" or "QSD". This directive will associate all
subsequent QAPI directives in a document with the specified
namespace. This does not change the visual display of any of the
definitions or index entries, but does change the "Fully Qualified Name"
inside the QAPI domain's object table. This allows for two different
"namespaces" to define entities with otherwise identical names -- which
will come in handy for documenting both QEMU QMP and the QEMU Storage
Daemon.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: b1df602ebbd06d56311a77d195284216263b13f8
https://github.com/qemu/qemu/commit/b1df602ebbd06d56311a77d195284216263b13f8
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/sphinx/qapidoc.py
Log Message:
-----------
docs/qapidoc: add :namespace: option to qapi-doc directive
Add a :namespace: option to the qapi-doc directive, which inserts a
qapi:namespace directive into the start of the generated document. This,
in turn, associates all auto-generated definitions by this directive
with the specified namespace.
The source info for these generated lines are credited to the start of
the qapi-doc directive, which isn't precisely correct, but I wasn't sure
how to get it more accurate without some re-parsing shenanigans.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 7127e14f15fc52b436eb63e482a9f117bd4346d2
https://github.com/qemu/qemu/commit/7127e14f15fc52b436eb63e482a9f117bd4346d2
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/devel/qapi-domain.rst
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi_domain: add namespace support to cross-references
This patch does three things:
1. Record the current namespace context in pending_xrefs so it can be
used for link resolution later,
2. Pass that recorded namespace context to find_obj() when resolving a
reference, and
3. Wildly and completely rewrite find_obj().
cross-reference support is expanded to tolerate the presence or absence
of either namespace or module, and to cope with the presence or absence
of contextual information for either.
References now work like this:
1. If the explicit reference target is recorded in the domain's object
registry, we link to that target and stop looking. We do this lookup
regardless of how fully qualified the target is, which allows direct
references to modules (which don't have a module component to their
names) or direct references to definitions that may or may not belong
to a namespace or module.
2. If contextual information is available from qapi:namespace or
qapi:module directives, try using those components to find a direct
match to the implied target name.
3. If both prior lookups fail, generate a series of regular expressions
looking for wildcard matches in order from most to least
specific. Any explicitly provided components (namespace, module)
*must* match exactly, but both contextual and entirely omitted
components are allowed to differ from the search result. Note that if
more than one result is found, Sphinx will emit a warning (a build
error for QEMU) and list all of the candidate references.
The practical upshot is that in the large majority of cases, namespace
and module information is not required when creating simple `references`
to definitions from within the same context -- even when identical
definitions exist in other contexts.
Even when using simple `references` from elsewhere in the QEMU
documentation manual, explicit namespace info is not required if there
is only one definition by that name.
Disambiguation *will* be required from outside of the QAPI documentation
when referencing e.g. block-core definitions, which are shared between
QEMU QMP and the QEMU Storage Daemon. In that case, there are two
options:
A: References can be made partially or fully explicit,
e.g. `QMP:block-dirty-bitmap-add` will link to the QEMU version of
the definition, while `QSD:block-dirty-bitmap-add` would link to the
QSD version.
B: If all of the references in a document are intended to go to the same
place, you can insert a "qapi:namespace:: QMP" directive to influence
the fuzzy-searching for later references.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
[Commit message typo fixed]
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 25d44f57e17b088fdc4e38042e04c4e9da2c1088
https://github.com/qemu/qemu/commit/25d44f57e17b088fdc4e38042e04c4e9da2c1088
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/conf.py
M docs/sphinx/qapi_domain.py
Log Message:
-----------
docs/qapi-domain: add namespaced index support
Generate an index-per-namespace for the QAPI domain. Due to a limitation
with Sphinx's architecture, these indices must be defined during setup
time and cannot be dynamically created on-demand when a namespace
directive is encountered.
Owing to that limitation, add a configuration value to conf.py that
specifies which QAPI namespaces we'll generate indices for.
Indices will be named after their namespace, e.g. the "QMP" namespace
will generate to "qapi-qmp-index.html" and can be referenced using
`qapi-qmp-index`.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: 602c90beaedd9abbbf1535c8630293267e6b29c0
https://github.com/qemu/qemu/commit/602c90beaedd9abbbf1535c8630293267e6b29c0
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/conf.py
M docs/interop/qemu-qmp-ref.rst
M qapi/qapi-schema.json
Log Message:
-----------
docs: add QAPI namespace "QMP" to qemu-qmp-ref
This also creates the qapi-qmp-index.html index and cross-reference
target.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: d85f7efe1f16c51b9c016ebc79f7c4081486642e
https://github.com/qemu/qemu/commit/d85f7efe1f16c51b9c016ebc79f7c4081486642e
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/devel/qapi-domain.rst
Log Message:
-----------
docs: disambiguate references in qapi-domain.rst
Before we enable the QGA and QSD namespaces, we need to disambiguate
some of the references that would become ambiguous as a result!
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: a6af54434400099b8afd59ba036cf9a662006d1e
https://github.com/qemu/qemu/commit/a6af54434400099b8afd59ba036cf9a662006d1e
Author: John Snow <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M docs/conf.py
M docs/interop/qemu-ga-ref.rst
M docs/interop/qemu-storage-daemon-qmp-ref.rst
M qga/qapi-schema.json
M storage-daemon/qapi/qapi-schema.json
Log Message:
-----------
docs: enable transmogrifier for QSD and QGA
This also creates the `qapi-qsd-index` and `qapi-qga-index` QMP indices.
Signed-off-by: John Snow <[email protected]>
Message-ID: <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Signed-off-by: Markus Armbruster <[email protected]>
Commit: eae0c3b659fbad5168c9bb9784b49d255185e35c
https://github.com/qemu/qemu/commit/eae0c3b659fbad5168c9bb9784b49d255185e35c
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.h
Log Message:
-----------
target/arm: Move A32_BANKED_REG_{GET,SET} macros to cpregs.h
The A32_BANKED_REG_{GET,SET} macros are only used inside target/arm;
move their definitions to cpregs.h. There's no need to have them
defined in all the code that includes cpu.h.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 23560ada94bd22cb9e8d27b7e9389f6369f6d74d
https://github.com/qemu/qemu/commit/23560ada94bd22cb9e8d27b7e9389f6369f6d74d
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/hflags.c
Log Message:
-----------
target/arm: Un-inline access_secure_reg()
We would like to move arm_el_is_aa64() to internals.h; however, it is
used by access_secure_reg(). Make that function not be inline, so
that it can stay in cpu.h.
access_secure_reg() is used only in two places:
* in hflags.c
* in the user-mode arm emulators, to decide whether to store
the TLS value in the secure or non-secure banked field
The second of these is not on a super-hot path that would care about
the inlining (and incidentally will always use the NS banked field
because our user-mode CPUs never set ARM_FEATURE_EL3); put the
definition of access_secure_reg() in hflags.c, near its only use
inside target/arm.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: fe0f88ab87632075ae9404685672a8f172a3ae6f
https://github.com/qemu/qemu/commit/fe0f88ab87632075ae9404685672a8f172a3ae6f
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M linux-user/aarch64/cpu_loop.c
Log Message:
-----------
linux-user/aarch64: Remove unused get/put_user macros
At the top of linux-user/aarch64/cpu_loop.c we define a set of
macros for reading and writing data and code words, but we never
use these macros. Delete them.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 63d8b11d0aeb84ba53510cdf66612940a372451f
https://github.com/qemu/qemu/commit/63d8b11d0aeb84ba53510cdf66612940a372451f
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M linux-user/arm/cpu_loop.c
Log Message:
-----------
linux-user/arm: Remove unused get_put_user macros
In linux-user/arm/cpu_loop.c we define a full set of get/put
macros for both code and data (since the endianness handling
is different between the two). However the only one we actually
use is get_user_code_u32(). Remove the rest.
We leave a comment noting how data-side accesses should be handled
for big-endian, because that's a subtle point and we just removed the
macros that were effectively documenting it.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: fefc1220ad68d816627aebc393cbf2cb34ff6924
https://github.com/qemu/qemu/commit/fefc1220ad68d816627aebc393cbf2cb34ff6924
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/internals.h
Log Message:
-----------
target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h
The arm_cpu_data_is_big_endian() and related functions are now used
only in target/arm; they can be moved to internals.h.
The motivation here is that we would like to move arm_current_el()
to internals.h.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 2beb051191b526608e0f269559962f4d2f618850
https://github.com/qemu/qemu/commit/2beb051191b526608e0f269559962f4d2f618850
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M hw/intc/arm_gicv3_cpuif.c
M target/arm/arch_dump.c
M target/arm/cpu.h
M target/arm/internals.h
Log Message:
-----------
target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h
The functions arm_current_el() and arm_el_is_aa64() are used only in
target/arm and in hw/intc/arm_gicv3_cpuif.c. They're functions that
query internal state of the CPU. Move them out of cpu.h and into
internals.h.
This means we need to include internals.h in arm_gicv3_cpuif.c, but
this is justifiable because that file is implementing the GICv3 CPU
interface, which really is part of the CPU proper; we just ended up
implementing it in code in hw/intc/ for historical reasons.
The motivation for this move is that we'd like to change
arm_el_is_aa64() to add a condition that uses cpu_isar_feature();
but we don't want to include cpu-features.h in cpu.h.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 5d71c6820f3b91763b5807311969cc0362d457d9
https://github.com/qemu/qemu/commit/5d71c6820f3b91763b5807311969cc0362d457d9
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32
The definition of SCR_EL3.RW says that its effective value is 1 if:
- EL2 is implemented and does not support AArch32, and SCR_EL3.NS is 1
- the effective value of SCR_EL3.{EEL2,NS} is {1,0} (i.e. we are
Secure and Secure EL2 is disabled)
We implement the second of these in arm_el_is_aa64(), but forgot the
first.
Provide a new function arm_scr_rw_eff() to return the effective
value of SCR_EL3.RW, and use it in arm_el_is_aa64() and the other
places that currently look directly at the bit value.
(scr_write() enforces that the RW bit is RAO/WI if neither EL1 nor
EL2 have AArch32 support, but if EL1 does but EL2 does not then the
bit must still be writeable.)
This will mean that if code at EL3 attempts to perform an exception
return to AArch32 EL2 when EL2 is AArch64-only we will correctly
handle this as an illegal exception return: it will be caught by the
"return to an EL which is configured for a different register width"
check in HELPER(exception_return).
We do already have some CPU types which don't implement AArch32
above EL0, so this is technically a bug; it doesn't seem worth
backporting to stable because no sensible guest code will be
deliberately attempting to set the RW bit to a value corresponding
to an unimplemented execution state and then checking that we
did the right thing.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 1632a2017f682a9dc6ce51756b9765af07977873
https://github.com/qemu/qemu/commit/1632a2017f682a9dc6ce51756b9765af07977873
Author: Steve Sistare <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M include/migration/cpr.h
M migration/cpr.c
Log Message:
-----------
migration: cpr_is_incoming
Define the cpr_is_incoming helper, to be used in several cpr fix patches.
Signed-off-by: Steve Sistare <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Commit: e56ba1878fefe7babff76ff399311ae5e399c5c5
https://github.com/qemu/qemu/commit/e56ba1878fefe7babff76ff399311ae5e399c5c5
Author: Steve Sistare <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M hw/block/block.c
Log Message:
-----------
pflash: fix cpr
During normal migration, new QEMU creates and initializes memory regions,
then loads the preserved contents of the region from vmstate.
During CPR, memory regions are preserved in place, then the realize
method initializes the regions contents, losing the old contents. To
fix, skip the re-init during CPR.
Signed-off-by: Steve Sistare <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Commit: b42f28111e081ab1fd370e92ee78a461027590f0
https://github.com/qemu/qemu/commit/b42f28111e081ab1fd370e92ee78a461027590f0
Author: Steve Sistare <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M hw/core/loader.c
Log Message:
-----------
hw/loader: fix roms during cpr
During normal migration, new QEMU creates and initializes memory regions,
then loads the preserved contents of the region from vmstate.
During CPR, memory regions are preserved in place, then the realize
method initializes the regions contents, losing the old contents. To
fix, skip the re-init during CPR.
Signed-off-by: Steve Sistare <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Commit: 8ffe0623a1f40803feb4280fce13549baa4b0b47
https://github.com/qemu/qemu/commit/8ffe0623a1f40803feb4280fce13549baa4b0b47
Author: Steve Sistare <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M hw/display/qxl.c
Log Message:
-----------
hw/qxl: fix cpr
During normal migration, new QEMU creates and initializes memory regions,
then loads the preserved contents of the region from vmstate.
During CPR, memory regions are preserved in place, then the realize
method initializes the regions contents, losing the old contents. To
fix, skip writes to the qxl memory regions during CPR load.
Reported-by: [email protected]
Tested-by: [email protected]
Signed-off-by: Steve Sistare <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Fabiano Rosas <[email protected]>
Commit: 39ec3fc030166c594a64d1d197e29fa9d100d4c5
https://github.com/qemu/qemu/commit/39ec3fc030166c594a64d1d197e29fa9d100d4c5
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32
When EL1 doesn't support AArch32, the HCR_EL2.RW bit is supposed to
be RAO/WI. Enforce the RAO/WI behaviour.
Note that we handle "reset value should honour RES1 bits" in the same
way that SCR_EL3 does, via a reset function.
We do already have some CPU types which don't implement AArch32
above EL0, so this is technically a bug; it doesn't seem worth
backporting to stable because no sensible guest code will be
deliberately attempting to set the RW bit to a value corresponding
to an unimplemented execution state and then checking that we
did the right thing.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 44ab8c248dee2d899dfe858ce1962fedcd3398a1
https://github.com/qemu/qemu/commit/44ab8c248dee2d899dfe858ce1962fedcd3398a1
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
Log Message:
-----------
target/arm: Add cpu local variable to exception_return helper
We already call env_archcpu() multiple times within the
exception_return helper function, and we're about to want to
add another use of the ARMCPU pointer. Add a local variable
cpu so we can call env_archcpu() just once.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: 097d68ac2fd9bd40d0b6a3b3992c86a1f79d7187
https://github.com/qemu/qemu/commit/097d68ac2fd9bd40d0b6a3b3992c86a1f79d7187
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
Log Message:
-----------
target/arm: Forbid return to AArch32 when CPU is AArch64-only
In the Arm ARM, rule R_TYTWB states that returning to AArch32
is an illegal exception return if:
* AArch32 is not supported at any exception level
* the target EL is configured for AArch64 via SCR_EL3.RW
or HCR_EL2.RW or via CPU state at reset
We check the second of these, but not the first (which can only be
relevant for the case of a return to EL0, because if AArch32 is not
supported at one of the higher ELs then the RW bits will have an
effective value of 1 and the the "configured for AArch64" condition
will hold also).
Add the missing condition. Although this is technically a bug
(because we have one AArch64-only CPU: a64fx) it isn't worth
backporting to stable because no sensible guest code will
deliberately try to return to a nonexistent execution state
to check that it gets an illegal exception return.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Commit: adb478a584dcf9c112fe8a6f9a7369162d3239fb
https://github.com/qemu/qemu/commit/adb478a584dcf9c112fe8a6f9a7369162d3239fb
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Fix status for Arm boards I "maintain"
I'm down as the only listed maintainer for quite a lot of Arm SoC and
board types. In some cases this is only as the "maintainer of last
resort" and I'm not in practice doing anything beyond patch review
and the odd bit of tidyup.
Move these entries in MAINTAINERS from "Maintained" to "Odd Fixes",
to better represent reality. Entries for other boards and SoCs where
I do more actively care (or where there is a listed co-maintainer)
remain as they are.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 9223d688111904f57e5dcbdb80b71ff73a68f8ca
https://github.com/qemu/qemu/commit/9223d688111904f57e5dcbdb80b71ff73a68f8ca
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
Log Message:
-----------
tests/functional: Bump up arm_replay timeout
On my machine the arm_replay test takes over 2 minutes to run
in a config with Rust enabled and debug enabled:
$ time (cd build/rust ; PYTHONPATH=../../python:../../tests/functional
QEMU_TEST_QEMU_BINARY=./qemu-system-arm ./pyvenv/bin/python3
../../tests/functional/test_arm_replay.py)
TAP version 13
ok 1 test_arm_replay.ArmReplay.test_cubieboard
ok 2 test_arm_replay.ArmReplay.test_vexpressa9
ok 3 test_arm_replay.ArmReplay.test_virt
1..3
real 2m16.564s
user 2m13.461s
sys 0m3.523s
Bump up the timeout to 4 minutes.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-id: [email protected]
Commit: 5b14454d37854f5c4227d642133a477a07e49759
https://github.com/qemu/qemu/commit/5b14454d37854f5c4227d642133a477a07e49759
Author: Paolo Bonzini <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M hw/char/pl011.c
Log Message:
-----------
Revert "hw/char/pl011: Warn when using disabled receiver"
The guest does not control whether characters are sent on the UART.
Sending them before the guest happens to boot will now result in a
"guest error" log entry that is only because of timing, even if the
guest _would_ later setup the receiver correctly.
This reverts the bulk of commit abf2b6a028670bd2890bb3aee7e103fe53e4b0df,
and instead adds a comment about why we don't check the enable bits.
Cc: Philippe Mathieu-Daudé <[email protected]>
Cc: Peter Maydell <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Message-id: [email protected]
[PMM: expanded comment]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e6c38d2ab55d66c74ceade5699e22cabe9058d22
https://github.com/qemu/qemu/commit/e6c38d2ab55d66c74ceade5699e22cabe9058d22
Author: Joe Komlodi <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M util/cacheflush.c
Log Message:
-----------
util/cacheflush: Make first DSB unconditional on aarch64
On ARM hosts with CTR_EL0.DIC and CTR_EL0.IDC set, this would only cause
an ISB to be executed during cache maintenance, which could lead to QEMU
executing TBs containing garbage instructions.
This seems to be because the ISB finishes executing instructions and
flushes the pipeline, but the ISB doesn't guarantee that writes from the
executed instructions are committed. If a small enough TB is created, it's
possible that the writes setting up the TB aren't committed by the time the
TB is executed.
This function is intended to be a port of the gcc implementation
(https://github.com/gcc-mirror/gcc/blob/85b46d0795ac76bc192cb8f88b646a647acf98c1/libgcc/config/aarch64/sync-cache.c#L67)
which makes the first DSB unconditional, so we can fix the synchronization
issue by doing that as well.
Cc: [email protected]
Fixes: 664a79735e4deb1 ("util: Specialize flush_idcache_range for aarch64")
Signed-off-by: Joe Komlodi <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 298a04998fa4a6dc977abe9234d98dfcdab98423
https://github.com/qemu/qemu/commit/298a04998fa4a6dc977abe9234d98dfcdab98423
Author: Richard Henderson <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Make DisasContext.{fp, sve}_access_checked tristate
The check for fp_excp_el in assert_fp_access_checked is
incorrect. For SME, with StreamingMode enabled, the access
is really against the streaming mode vectors, and access
to the normal fp registers is allowed to be disabled.
C.f. sme_enabled_check.
Convert sve_access_checked to match, even though we don't
currently check the exception state.
Cc: [email protected]
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: cc7abc35dfa790ba6c20473c03745428c1c626b6
https://github.com/qemu/qemu/commit/cc7abc35dfa790ba6c20473c03745428c1c626b6
Author: Richard Henderson <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Simplify pstate_sm check in sve_access_check
In StreamingMode, fp_access_checked is handled already.
We cannot fall through to fp_access_check lest we fall
foul of the double-check assertion.
Cc: [email protected]
Fixes: 285b1d5fcef ("target/arm: Handle SME in sve_access_check")
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: move declaration of 'ret' to top of block]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a019e15edfd62beae1e2f6adc0fa7415ba20b14c
https://github.com/qemu/qemu/commit/a019e15edfd62beae1e2f6adc0fa7415ba20b14c
Author: Peter Maydell <[email protected]>
Date: 2025-03-14 (Fri, 14 Mar 2025)
Changed paths:
M .gitlab-ci.d/buildtest-template.yml
M meson.build
Log Message:
-----------
meson.build: Set RUST_BACKTRACE for all tests
We want to capture potential Rust backtraces on panics in our test
logs, which isn't Rust's default behaviour. Set RUST_BACKTRACE=1 in
the add_test_setup environments, so that all our tests get run with
this environment variable set.
This makes the setting of that variable in the gitlab CI template
redundant, so we can remove it.
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Commit: 9beccc2df03026dc2979f0f28b8ff952e356164e
https://github.com/qemu/qemu/commit/9beccc2df03026dc2979f0f28b8ff952e356164e
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M docs/conf.py
M docs/devel/qapi-domain.rst
M docs/interop/qemu-ga-ref.rst
M docs/interop/qemu-qmp-ref.rst
M docs/interop/qemu-storage-daemon-qmp-ref.rst
M docs/sphinx/qapi_domain.py
M docs/sphinx/qapidoc.py
M qapi/block-core.json
M qapi/qapi-schema.json
M qga/qapi-schema.json
M storage-daemon/qapi/qapi-schema.json
Log Message:
-----------
Merge tag 'pull-qapi-2025-03-14' of https://repo.or.cz/qemu/armbru into
staging
QAPI patches patches for 2025-03-14
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# gpg: Signature made Fri 14 Mar 2025 05:56:29 EDT
# gpg: using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg: issuer "[email protected]"
# gpg: Good signature from "Markus Armbruster <[email protected]>" [full]
# gpg: aka "Markus Armbruster <[email protected]>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867 4E5F 3870 B400 EB91 8653
* tag 'pull-qapi-2025-03-14' of https://repo.or.cz/qemu/armbru:
docs: enable transmogrifier for QSD and QGA
docs: disambiguate references in qapi-domain.rst
docs: add QAPI namespace "QMP" to qemu-qmp-ref
docs/qapi-domain: add namespaced index support
docs/qapi_domain: add namespace support to cross-references
docs/qapidoc: add :namespace: option to qapi-doc directive
docs/qapi-domain: add qapi:namespace directive
docs/qapi-domain: add :namespace: override option
docs/qapi_domain: add namespace support to FQN
docs/qapi-domain: always store fully qualified name in signode
docs/qapi_domain: isolate TYPE_CHECKING imports
qapi/block-core: Improve x-blockdev-change documentation
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 5719376f17b9ea6420603f7962e644eeb3e62cc1
https://github.com/qemu/qemu/commit/5719376f17b9ea6420603f7962e644eeb3e62cc1
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M .gitlab-ci.d/buildtest-template.yml
M MAINTAINERS
M hw/char/pl011.c
M hw/intc/arm_gicv3_cpuif.c
M linux-user/aarch64/cpu_loop.c
M linux-user/arm/cpu_loop.c
M meson.build
M target/arm/arch_dump.c
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/helper-a64.c
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-a64.h
M target/arm/tcg/translate.h
M util/cacheflush.c
Log Message:
-----------
Merge tag 'pull-target-arm-20250314-1' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* Correctly handle corner cases of guest attempting an exception
return to AArch32 when target EL is AArch64 only
* MAINTAINERS: Fix status for Arm boards I "maintain"
* tests/functional: Bump up arm_replay timeout
* Revert "hw/char/pl011: Warn when using disabled receiver"
* util/cacheflush: Make first DSB unconditional on aarch64
* target/arm: Fix SVE/SME access check logic
* meson.build: Set RUST_BACKTRACE for all tests
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# gpg: Signature made Fri 14 Mar 2025 09:15:49 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250314-1' of
https://git.linaro.org/people/pmaydell/qemu-arm:
meson.build: Set RUST_BACKTRACE for all tests
target/arm: Simplify pstate_sm check in sve_access_check
target/arm: Make DisasContext.{fp, sve}_access_checked tristate
util/cacheflush: Make first DSB unconditional on aarch64
Revert "hw/char/pl011: Warn when using disabled receiver"
tests/functional: Bump up arm_replay timeout
MAINTAINERS: Fix status for Arm boards I "maintain"
target/arm: Forbid return to AArch32 when CPU is AArch64-only
target/arm: Add cpu local variable to exception_return helper
target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32
target/arm: SCR_EL3.RW should be treated as 1 if EL2 doesn't support AArch32
target/arm: Move arm_current_el() and arm_el_is_aa64() to internals.h
target/arm: Move arm_cpu_data_is_big_endian() etc to internals.h
linux-user/arm: Remove unused get_put_user macros
linux-user/aarch64: Remove unused get/put_user macros
target/arm: Un-inline access_secure_reg()
target/arm: Move A32_BANKED_REG_{GET,SET} macros to cpregs.h
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: aa90f1161bb17a4863e16ec2f75104cff0752d4e
https://github.com/qemu/qemu/commit/aa90f1161bb17a4863e16ec2f75104cff0752d4e
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-16 (Sun, 16 Mar 2025)
Changed paths:
M hw/block/block.c
M hw/core/loader.c
M hw/display/qxl.c
M include/migration/cpr.h
M migration/cpr.c
Log Message:
-----------
Merge tag 'migration-20250314-pull-request' of
https://gitlab.com/farosas/qemu into staging
Migration pull request
Fixes for cpr-transfer (live update functionality).
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# gpg: Signature made Fri 14 Mar 2025 10:42:14 EDT
# gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D
# gpg: issuer "[email protected]"
# gpg: Good signature from "Fabiano Rosas <[email protected]>" [unknown]
# gpg: aka "Fabiano Almeida Rosas <[email protected]>"
[unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'migration-20250314-pull-request' of https://gitlab.com/farosas/qemu:
hw/qxl: fix cpr
hw/loader: fix roms during cpr
pflash: fix cpr
migration: cpr_is_incoming
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/0462a32b4f63...aa90f1161bb1
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