Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 672cb29d1e811180bf1aeefbcb0936ecd5bd3853
https://github.com/qemu/qemu/commit/672cb29d1e811180bf1aeefbcb0936ecd5bd3853
Author: Santiago Monserrat Campanello <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M docs/about/emulation.rst
Log Message:
-----------
docs/about/emulation: Fix broken link
semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello <[email protected]>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 17288e38bebf20121c4aa20b264e661a7fa50ed8
https://github.com/qemu/qemu/commit/17288e38bebf20121c4aa20b264e661a7fa50ed8
Author: Paolo Savini <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
optimize the memory probing for vector fault-only-first loads.
Fault-only-first loads in the RISC-V vector extension need to update
the vl with the element index that causes an exception.
In order to ensure this the emulation of this instruction used to probe the
memory covered by the load operation with a loop that iterated over each element
so that when a flag was raised it was possible to set the vl to the
corresponding element index.
This loop was executed every time whether an exception happened or not.
This commit removes the per element memory probing from the main execution path
and adds a broad memory probing first. If this probing raises any flag that is
not a watchpoint flag (that per standard is allowed by this instruction) we
proceed with the per element probing to find the index of the element causing
the exception and set vl to such index.
Signed-off-by: Paolo Savini <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 86c78b280607fcff787866a03374047c65037a90
https://github.com/qemu/qemu/commit/86c78b280607fcff787866a03374047c65037a90
Author: Deepak Gupta <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: fix access permission checks for CSR_SSP
Commit:8205bc1 ("target/riscv: introduce ssp and enabling controls for
zicfiss") introduced CSR_SSP but it mis-interpreted the spec on access
to CSR_SSP in M-mode. Gated to CSR_SSP is not gated via `xSSE`. But
rather rules clearly specified in section "22.2.1. Shadow Stack Pointer
(ssp) CSR access contr" in the priv spec.
Fixes: 8205bc127a83 ("target/riscv: introduce ssp and enabling controls
for zicfiss". Thanks to Adam Zabrocki for bringing this to attention.
Reported-by: Adam Zabrocki <[email protected]>
Signed-off-by: Deepak Gupta <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d2c5759c8dd4c00195d4ebecc7d009e41df6baef
https://github.com/qemu/qemu/commit/d2c5759c8dd4c00195d4ebecc7d009e41df6baef
Author: Deepak Gupta <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
Log Message:
-----------
target/riscv: fixes a bug against `ssamoswap` behavior in M-mode
Commit f06bfe3dc38c ("target/riscv: implement zicfiss instructions") adds
`ssamoswap` instruction. `ssamoswap` takes the code-point from existing
reserved encoding (and not a zimop like other shadow stack instructions).
If shadow stack is not enabled (via xenvcfg.SSE) and effective priv is
less than M then `ssamoswap` must result in an illegal instruction
exception. However if effective priv is M, then `ssamoswap` results in
store/AMO access fault. See Section "22.2.3. Shadow Stack Memory
Protection" of priv spec.
Fixes: f06bfe3dc38c ("target/riscv: implement zicfiss instructions")
Reported-by: Ved Shanbhogue <[email protected]>
Signed-off-by: Deepak Gupta <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 3ea8fb521d6161a64879b6f43fac46b4d80d2e39
https://github.com/qemu/qemu/commit/3ea8fb521d6161a64879b6f43fac46b4d80d2e39
Author: Jason Chien <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu: Fix process directory table walk
The PPN field in a non-leaf PDT entry is positioned differently from that
in a leaf PDT entry. The original implementation incorrectly used the leaf
entry's PPN mask to extract the PPN from a non-leaf entry, leading to an
erroneous page table walk.
This commit introduces new macros to properly define the fields for
non-leaf PDT entries and corrects the page table walk.
Signed-off-by: Jason Chien <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: ec6411a5251de3479d44c6e539d0e9596c68909b
https://github.com/qemu/qemu/commit/ec6411a5251de3479d44c6e539d0e9596c68909b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()
Coverity found the following issue:
>>> CID 1593156: Integer handling issues (OVERFLOW_BEFORE_WIDEN)
>>> Potentially overflowing expression "0x10 << depth" with type
"int" (32 bits, signed) is evaluated using 32-bit arithmetic, and then
used in a context that expects an expression of type "uint64_t" (64
bits, unsigned).
4299 depth = 16 << depth;
Fix it by forcing the expression to be 64 bits wide by using '16ULL'.
Resolves: Coverity CID 1593156
Fixes: c48bd18eae ("target/riscv: Add support for Control Transfer Records
extension CSRs.")
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e83845316abcea9024eb5402a6c5eb8b092c79d5
https://github.com/qemu/qemu/commit/e83845316abcea9024eb5402a6c5eb8b092c79d5
Author: Chao Liu <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/vector_internals.c
M target/riscv/vector_internals.h
Log Message:
-----------
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
Some vector instructions are special, such as the vlm.v instruction,
where setting its vl actually sets evl = (vl + 7) >> 3. To improve
maintainability, we will uniformly use VSTART_CHECK_EARLY_EXIT() to
check for the condition vstart >= vl. This function will also handle
cases involving evl.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID:
<f575979874e323a9e0da7796aa391c7d87e56f88.1741573286.git.lc00...@tecorigin.com>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4e9e2478dfd26480bbf50367a67b9be0edafef2b
https://github.com/qemu/qemu/commit/4e9e2478dfd26480bbf50367a67b9be0edafef2b
Author: Chao Liu <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: fix handling of nop for vstart >= vl in some vector instruction
Recently, when I was writing a RISCV test, I found that when VL is set to 0, the
instruction should be nop, but when I tested it, I found that QEMU will treat
all elements as tail elements, and in the case of VTA=1, write all elements
to 1.
After troubleshooting, it was found that the vext_vx_rm_1 function was called in
the vext_vx_rm_2, and then the vext_set_elems_1s function was called to process
the tail element, but only VSTART >= vl was checked in the vext_vx_rm_1
function, which caused the tail element to still be processed even if it was
returned in advance.
So I've made the following change:
Put VSTART_CHECK_EARLY_EXIT(env) at the beginning of the vext_vx_rm_2 function,
so that the VSTART register is checked correctly.
Fixes: df4252b2ec ("target/riscv/vector_helpers: do early exit when
vstart >= vl")
Signed-off-by: Chao Liu <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID:
<b2649f14915150be4c602d63cd3ea4adf47e9d75.1741573286.git.lc00...@tecorigin.com>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c1a6bff276ca52ffde472532d92bb5bb122dab3f
https://github.com/qemu/qemu/commit/c1a6bff276ca52ffde472532d92bb5bb122dab3f
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M hw/virtio/meson.build
Log Message:
-----------
hw/virtio: Also include md stubs in case CONFIG_VIRTIO_PCI is not set
For the s390x target, it's possible to build the QEMU binary without
CONFIG_VIRTIO_PCI and only have the virtio-mem device via the ccw
transport. In that case, QEMU currently fails to link correctly:
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_device_pre_plug':
../hw/s390x/s390-virtio-ccw.c:579:(.text+0x1e96): undefined reference to
`virtio_md_pci_pre_plug'
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_device_plug':
../hw/s390x/s390-virtio-ccw.c:608:(.text+0x21a4): undefined reference to
`virtio_md_pci_plug'
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_device_unplug_request':
../hw/s390x/s390-virtio-ccw.c:622:(.text+0x2334): undefined reference to
`virtio_md_pci_unplug_request'
/usr/bin/ld: libqemu-s390x-softmmu.a.p/hw_s390x_s390-virtio-ccw.c.o: in
function `s390_machine_device_unplug':
../hw/s390x/s390-virtio-ccw.c:633:(.text+0x2436): undefined reference to
`virtio_md_pci_unplug'
clang: error: linker command failed with exit code 1 (use -v to see invocation)
We also need to include the stubs when CONFIG_VIRTIO_PCI is missing.
Fixes: aa910c20ec5 ("s390x: virtio-mem support")
Message-ID: <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 6d19d095470221684afe065cffd40adebe644d04
https://github.com/qemu/qemu/commit/6d19d095470221684afe065cffd40adebe644d04
Author: Niek Linnenbank <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M tests/functional/test_arm_orangepi.py
Log Message:
-----------
tests/functional/test_arm_orangepi: rename test class to 'OrangePiMachine'
The test class in this file contains all functional test cases
for testing the Orange Pi PC board. It should be given a name
matching the Qemu machine it covers.
This commit sets the test class name to 'OrangePiMachine'.
Signed-off-by: Niek Linnenbank <[email protected]>
Fixes: 380f7268b7b ("tests/functional: Convert the OrangePi tests to the
functional framework")
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 23686dfb763d22d95c05c49382116d77133637b7
https://github.com/qemu/qemu/commit/23686dfb763d22d95c05c49382116d77133637b7
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M tests/functional/qemu_test/testcase.py
M tests/functional/test_acpi_bits.py
Log Message:
-----------
tests/functional: remove all class level fields
A number of fields are set at the class level on QemuBaseTest, even
though the exact same named field is then set at the object level
later in most cases.
The 'self.logger' initialization in ACPI bits test needs to be removed
since 'self.log' won't exist at that point in the flow. It already
initialized 'self.logger' later in the setUp() method, so the __init__
method was redundant.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: cef6da5bc9c63871814f544e0af2be22fa60aec3
https://github.com/qemu/qemu/commit/cef6da5bc9c63871814f544e0af2be22fa60aec3
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M docs/system/arm/bananapi_m2u.rst
M docs/system/arm/orangepi.rst
M docs/system/devices/igb.rst
Log Message:
-----------
docs/system: Use the meson binary from the pyvenv
To avoid problems with the meson installation from the host
system, we should always use the meson from our venv instead.
Thus use this in the documentation, too.
While we're at it, also mention that it has to be run from
the build folder (in the igb.rst file; the other two files
were already fine).
Suggested-by: Niek Linnenbank <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Reviewed-by: Niek Linnenbank <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: a6836b6d49a76b71c43e9571f8bcc6a73b542a77
https://github.com/qemu/qemu/commit/a6836b6d49a76b71c43e9571f8bcc6a73b542a77
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M docs/system/arm/bananapi_m2u.rst
M docs/system/arm/orangepi.rst
Log Message:
-----------
docs/system/arm: Use "functional tests" instead of "integration tests"
We don't use the term "integration tests" for these kind of tests
anymore, it's "functional tests" nowadays.
Suggested-by: Niek Linnenbank <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Niek Linnenbank <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 1a010d22b7adecf0fb1c069e1e535af1aa51e9cf
https://github.com/qemu/qemu/commit/1a010d22b7adecf0fb1c069e1e535af1aa51e9cf
Author: Richard Henderson <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall
The third argument of the syscall contains the size of the
cpu mask in bytes, not bits. Nor is the size rounded up to
a multiple of sizeof(abi_ulong).
Cc: [email protected]
Reported-by: Andreas Schwab <[email protected]>
Fixes: 9e1c7d982d7 ("linux-user/riscv: Add syscall riscv_hwprobe")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: bcbd8c0edf712a7d55d9bf020be4b0f21ce3c35c
https://github.com/qemu/qemu/commit/bcbd8c0edf712a7d55d9bf020be4b0f21ce3c35c
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M docs/devel/testing/functional.rst
Log Message:
-----------
docs/devel/testing/functional: Add a section about logging
We should tell the users where to find the log file.
While we're at it, also rename the "Overview" heading to a
more accurate "Introduction to writing tests" instead.
Reported-by: Aditya Gupta <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 1ddd4d3f6ed39ffd1e0cc03ada36b0766d5be9fb
https://github.com/qemu/qemu/commit/1ddd4d3f6ed39ffd1e0cc03ada36b0766d5be9fb
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M tests/functional/test_x86_64_kvm_xen.py
Log Message:
-----------
tests/functional/test_x86_64_kvm_xen: Remove avocado tags
They have been forgotten to be removed when converting the
test to the functional framework. Since they are of no use
anymore, let's remove them now.
Message-ID: <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: ffe4db11f8aed79c7ec7d3ebd92674a1cfab4fe7
https://github.com/qemu/qemu/commit/ffe4db11f8aed79c7ec7d3ebd92674a1cfab4fe7
Author: Yu-Ming Chang <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/op_helper.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add check for 16-bit aligned PC for different priv versions.
For privilege version 1.12 or newer, C always implies Zca. We can only
check ext_zca to allow 16-bit aligned PC addresses. For older privilege
versions, we only check C.
Signed-off-by: Yu-Ming Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f700abbbeb6ab68a3446d1fb168a934d6f284eb5
https://github.com/qemu/qemu/commit/f700abbbeb6ab68a3446d1fb168a934d6f284eb5
Author: Thomas Huth <[email protected]>
Date: 2025-03-19 (Wed, 19 Mar 2025)
Changed paths:
M tests/functional/test_migration.py
Log Message:
-----------
tests/functional/test_migration: Use "ncat" instead of "nc" in the exec test
"nc" can either be GNU netcat, OpenBSD netcat or NMap ncat. At
least GNU netcat currently does not work with this test anymore,
though the comment in the test says otherwise. GNU netcat seems
to be quite unmaintained nowadays, according to its website
(https://netcat.sourceforge.net/), the last public release is from
2004, so we should rather avoid that binary.
In our CI, we are only using "ncat" in the containers (it's the only
flavor that lcitool supports), thus to avoid silent regressions with
the other netcats, let's limit this test to "ncat" only now.
Reported-by: Matheus Tavares Bernardino <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Matheus Tavares Bernardino <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Fabiano Rosas <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 17e9c9094400afefa0c802b903186a730c148c49
https://github.com/qemu/qemu/commit/17e9c9094400afefa0c802b903186a730c148c49
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M docs/about/emulation.rst
M hw/riscv/riscv-iommu-bits.h
M hw/riscv/riscv-iommu.c
M linux-user/syscall.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvi.c.inc
M target/riscv/insn_trans/trans_rvzicfiss.c.inc
M target/riscv/op_helper.c
M target/riscv/translate.c
M target/riscv/vcrypto_helper.c
M target/riscv/vector_helper.c
M target/riscv/vector_internals.c
M target/riscv/vector_internals.h
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20250319' of
https://github.com/alistair23/qemu into staging
Fourth RISC-V PR for 10.0
* Fix broken emulation link
* Optimize the memory probing for vector fault-only-first loads
* Fix access permission checks for CSR_SSP
* Fixes a bug against `ssamoswap` behavior in M-mode
* Fix IOMMU process directory table walk
* Fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()
* Enhance VSTART and VL checks for vector instructions
* Fix handling of cpu mask in riscv_hwprobe syscall
* Add check for 16-bit aligned PC for different priv versions
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* tag 'pull-riscv-to-apply-20250319' of https://github.com/alistair23/qemu:
target/riscv: Add check for 16-bit aligned PC for different priv versions.
linux-user/riscv: Fix handling of cpu mask in riscv_hwprobe syscall
target/riscv: fix handling of nop for vstart >= vl in some vector instruction
target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter
target/riscv/csr.c: fix OVERFLOW_BEFORE_WIDEN in rmw_sctrdepth()
hw/riscv/riscv-iommu: Fix process directory table walk
target/riscv: fixes a bug against `ssamoswap` behavior in M-mode
target/riscv: fix access permission checks for CSR_SSP
optimize the memory probing for vector fault-only-first loads.
docs/about/emulation: Fix broken link
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 527dede083d3e3e5a13ee996776926e0a0c4e258
https://github.com/qemu/qemu/commit/527dede083d3e3e5a13ee996776926e0a0c4e258
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-03-20 (Thu, 20 Mar 2025)
Changed paths:
M docs/devel/testing/functional.rst
M docs/system/arm/bananapi_m2u.rst
M docs/system/arm/orangepi.rst
M docs/system/devices/igb.rst
M hw/virtio/meson.build
M tests/functional/qemu_test/testcase.py
M tests/functional/test_acpi_bits.py
M tests/functional/test_arm_orangepi.py
M tests/functional/test_migration.py
M tests/functional/test_x86_64_kvm_xen.py
Log Message:
-----------
Merge tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu into
staging
* Fix linking problem when CONFIG_VIRTIO_PCI is not set for s390x
* Update functional tests parts of the documenation
* Some minor fixes for functional tests
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# gpg: Good signature from "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
# gpg: aka "Thomas Huth <[email protected]>" [full]
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* tag 'pull-request-2025-03-19' of https://gitlab.com/thuth/qemu:
tests/functional/test_migration: Use "ncat" instead of "nc" in the exec test
tests/functional/test_x86_64_kvm_xen: Remove avocado tags
docs/devel/testing/functional: Add a section about logging
docs/system/arm: Use "functional tests" instead of "integration tests"
docs/system: Use the meson binary from the pyvenv
tests/functional: remove all class level fields
tests/functional/test_arm_orangepi: rename test class to 'OrangePiMachine'
hw/virtio: Also include md stubs in case CONFIG_VIRTIO_PCI is not set
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/1dae461a913f...527dede083d3
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