Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: a079836005fb92eb1fee19e59654b337a41fd0ff
https://github.com/qemu/qemu/commit/a079836005fb92eb1fee19e59654b337a41fd0ff
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Fix vec_val computation in tcg_target_const_match
Only use vece for a vector constant. This avoids an assertion
failure in sextract64 when vece contains garbage.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 911f7328e9e9de80bf6b1a4697ecf83cc3661f5f
https://github.com/qemu/qemu/commit/911f7328e9e9de80bf6b1a4697ecf83cc3661f5f
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Improve constraints for TCG_CT_CONST_VCMP
Use the TCGCond given to tcg_target_const_match to exactly match
the supported constant. Adjust the code generation to assume this
has been done -- recall that encode_*_insn contain assertions that
the constants are valid.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a3c1c579baf511a2b95f7b233187a981b6ef46ea
https://github.com/qemu/qemu/commit/a3c1c579baf511a2b95f7b233187a981b6ef46ea
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Introduce opt_insert_{before,after}
Consolidate the places we call tcg_op_insert_{before,after}
within the optimization pass.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cf5c9f697f2025880e8555467ddb6debc6349cd8
https://github.com/qemu/qemu/commit/cf5c9f697f2025880e8555467ddb6debc6349cd8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
M tcg/tcg-internal.h
M tcg/tcg.c
Log Message:
-----------
tcg: Add TCGType to tcg_op_insert_{after,before}
We cannot rely on the value copied from TCGOP_TYPE(op), because
the relevant op could be typeless, such as INDEX_op_call.
Fixes: fb744ece3a78 ("tcg: Copy TCGOP_TYPE in tcg_op_insert_{after,before}")
Suggested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5500bd9e2ec5ec85858fcca06c04a57337aa14c7
https://github.com/qemu/qemu/commit/5500bd9e2ec5ec85858fcca06c04a57337aa14c7
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Add all_outop[]
Add infrastructure for more consolidated output of opcodes.
The base structure allows for constraints to be either static
or dynamic, and for the existence of those constraints to
replace TCG_TARGET_HAS_* and the bulk of tcg_op_supported.
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 2225fa242c5d95c5cd83bb6f8566d43dd7a00211
https://github.com/qemu/qemu/commit/2225fa242c5d95c5cd83bb6f8566d43dd7a00211
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Use extract2 for cross-word 64-bit extract on 32-bit host
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 48e8de684aff7ad112aafcf74f776d2a66ef192e
https://github.com/qemu/qemu/commit/48e8de684aff7ad112aafcf74f776d2a66ef192e
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Remove INDEX_op_ext{8,16,32}*
Use the fully general extract opcodes instead.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b5701261da6607e61ef1fe605d85bf31806fcd34
https://github.com/qemu/qemu/commit/b5701261da6607e61ef1fe605d85bf31806fcd34
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_mov_{i32,i64}
Begin to rely on TCGOp.type to discriminate operations,
rather than two different opcodes. Convert mov first.
Introduce TCG_OPF_INT in order to keep opcode dumps the same.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 662cdbcf0073c4de8456f5e573523571e3d9da5b
https://github.com/qemu/qemu/commit/662cdbcf0073c4de8456f5e573523571e3d9da5b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert add to TCGOutOpBinary
Drop all backend support for an immediate as the first operand.
This should never happen in any case, as we swap commutative
operands to place immediates as the second operand.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 79602f632a20228fc963161cd53f7d5f6a3bd953
https://github.com/qemu/qemu/commit/79602f632a20228fc963161cd53f7d5f6a3bd953
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/sh4/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_add_{i32,i64}
Rely on TCGOP_TYPE instead of opcodes specific to each type.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bf40f915fc24b97e27e852f0eae5f59eaf63de59
https://github.com/qemu/qemu/commit/bf40f915fc24b97e27e852f0eae5f59eaf63de59
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert and to TCGOutOpBinary
Drop all backend support for an immediate as the first operand.
This should never happen in any case, as we swap commutative
operands to place immediates as the second operand.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c3b920b3d6a685484904d3060f3eb69401051bf0
https://github.com/qemu/qemu/commit/c3b920b3d6a685484904d3060f3eb69401051bf0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/sh4/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_and_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 899281c8f589cce55951e13307661a7253eb4909
https://github.com/qemu/qemu/commit/899281c8f589cce55951e13307661a7253eb4909
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Fold andc with immediate to and
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 93a9ddb84ae534a04e8d7764caa9e29b8285b2b1
https://github.com/qemu/qemu/commit/93a9ddb84ae534a04e8d7764caa9e29b8285b2b1
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Emit add r,r,-1 in fold_setcond_tst_pow2
We canonicalize subtract with constant to add with constant.
Fix this missed instance.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a341c84e8153b7282b083e871ca534f15fa70898
https://github.com/qemu/qemu/commit/a341c84e8153b7282b083e871ca534f15fa70898
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert andc to TCGOutOpBinary
At the same time, drop all backend support for immediate
operands, as we now transform andc to and during optimize.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 46f96bff163512f9f8f9959de4a18c0799001422
https://github.com/qemu/qemu/commit/46f96bff163512f9f8f9959de4a18c0799001422
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/arm/tcg/translate-a64.c
M target/tricore/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_andc_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6497af5b0d76819475839de9ea1ef9faad6215c0
https://github.com/qemu/qemu/commit/6497af5b0d76819475839de9ea1ef9faad6215c0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert or to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 49bd751497f3b71550b152ef9da0e265a94a64c1
https://github.com/qemu/qemu/commit/49bd751497f3b71550b152ef9da0e265a94a64c1
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/sh4/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_or_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 50e40ecd7a5eb803a67d02aa586b5671968ac58b
https://github.com/qemu/qemu/commit/50e40ecd7a5eb803a67d02aa586b5671968ac58b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Fold orc with immediate to or
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d262ae608115d2e6fc61ba6998d9813a5208b0e5
https://github.com/qemu/qemu/commit/d262ae608115d2e6fc61ba6998d9813a5208b0e5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert orc to TCGOutOpBinary
At the same time, drop all backend support for immediate
operands, as we now transform orc to or during optimize.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6aba25ebb9eb6e1e86398294694aa0ab1f12076f
https://github.com/qemu/qemu/commit/6aba25ebb9eb6e1e86398294694aa0ab1f12076f
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/arm/tcg/translate-sve.c
M target/tricore/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_orc_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d3e56f382493540b3a46a432a7e09261f4f5dbe7
https://github.com/qemu/qemu/commit/d3e56f382493540b3a46a432a7e09261f4f5dbe7
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert xor to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fffd3dc9022efe89b9196d738127c294cf43a4d6
https://github.com/qemu/qemu/commit/fffd3dc9022efe89b9196d738127c294cf43a4d6
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/sh4/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_xor_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 46c68d75063d2d1119d5907e24e64e068ff64ba4
https://github.com/qemu/qemu/commit/46c68d75063d2d1119d5907e24e64e068ff64ba4
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Fold eqv with immediate to xor
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 18bc92091641880121d43584093ff207b0c44cfb
https://github.com/qemu/qemu/commit/18bc92091641880121d43584093ff207b0c44cfb
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert eqv to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5c0968a7e1da73f91f148d563a29af529427c5a5
https://github.com/qemu/qemu/commit/5c0968a7e1da73f91f148d563a29af529427c5a5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_eqv_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e5a3162cb6c1aec4f47c6b51671e989b5975f345
https://github.com/qemu/qemu/commit/e5a3162cb6c1aec4f47c6b51671e989b5975f345
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert nand to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 59379a45af1f4d62fc8c1ae0ddee988f47075787
https://github.com/qemu/qemu/commit/59379a45af1f4d62fc8c1ae0ddee988f47075787
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_nand_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8fb04b8295994e7416a222906939696d496638f3
https://github.com/qemu/qemu/commit/8fb04b8295994e7416a222906939696d496638f3
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Do not accept constant argument to nor
The instruction set does not implement nor with immediate.
There is no reason to pretend that we do.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3f6b223012f62bb3f73552bea4489383f08cdc23
https://github.com/qemu/qemu/commit/3f6b223012f62bb3f73552bea4489383f08cdc23
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert nor to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3a8c4e9e53c6f4aa7c590971950000b174e74fa1
https://github.com/qemu/qemu/commit/3a8c4e9e53c6f4aa7c590971950000b174e74fa1
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_nor_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a3b37bc6faafe5932739c997b2b34a8f6dd57bfd
https://github.com/qemu/qemu/commit/a3b37bc6faafe5932739c997b2b34a8f6dd57bfd
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Fix constraints for sub
In 7536b82d288 we lost the rI constraint that allowed the use of
RSB to perform reg = imm - reg. At the same time, drop support
for reg = reg - imm, which is now transformed generically to
addition, and need not be handled by the backend.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3f057e24006fbc5eaf42278ba9368d383a1c7bed
https://github.com/qemu/qemu/commit/3f057e24006fbc5eaf42278ba9368d383a1c7bed
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert sub to TCGOutOpSubtract
Create a special subclass for sub, because two backends can
support "subtract from immediate". Drop all backend support
for an immediate as the second operand, as we transform sub
to add during optimize.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 60f34f55f1a708c071774bd7f837163d6b686867
https://github.com/qemu/qemu/commit/60f34f55f1a708c071774bd7f837163d6b686867
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_sub_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e126a91c38f85750d84cabf27f44c055e17ef6df
https://github.com/qemu/qemu/commit/e126a91c38f85750d84cabf27f44c055e17ef6df
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert neg to TCGOutOpUnary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6971358747d8998a5770d1bf997495d3061d6c6a
https://github.com/qemu/qemu/commit/6971358747d8998a5770d1bf997495d3061d6c6a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_neg_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 592982bf04cfa92dc4c992056c7330ac46f4882f
https://github.com/qemu/qemu/commit/592982bf04cfa92dc4c992056c7330ac46f4882f
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert not to TCGOutOpUnary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5c62d3779b8b1075782672751165c0e4f716762f
https://github.com/qemu/qemu/commit/5c62d3779b8b1075782672751165c0e4f716762f
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_not_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1e4ac0ea5dc86c54e97bbc4db9638f2febdfde8b
https://github.com/qemu/qemu/commit/1e4ac0ea5dc86c54e97bbc4db9638f2febdfde8b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert mul to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d2c3ecadea89832ab82566e881bc3a288b020473
https://github.com/qemu/qemu/commit/d2c3ecadea89832ab82566e881bc3a288b020473
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_mul_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 937246f2ee87d01062bac7c356c1766b8c5038a8
https://github.com/qemu/qemu/commit/937246f2ee87d01062bac7c356c1766b8c5038a8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert muluh to TCGOutOpBinary
Remove unreachable mul[su]h_i32 leftovers from commit aeb6326ec5e
("tcg/riscv: Require TCG_TARGET_REG_BITS == 64").
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: aa28c9ef8e109db40d4781d82452805486f2a2bf
https://github.com/qemu/qemu/commit/aa28c9ef8e109db40d4781d82452805486f2a2bf
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Merge INDEX_op_muluh_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a9983f81290d41ed614a193a33d03be936f6435c
https://github.com/qemu/qemu/commit/a9983f81290d41ed614a193a33d03be936f6435c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert mulsh to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c742824dd8df3283098d5339291d49e65e515751
https://github.com/qemu/qemu/commit/c742824dd8df3283098d5339291d49e65e515751
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Merge INDEX_op_mulsh_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0cdacacebbe8a5e0d8a68a8c0007bff364c0e79a
https://github.com/qemu/qemu/commit/0cdacacebbe8a5e0d8a68a8c0007bff364c0e79a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert div to TCGOutOpBinary
For TCI, we're losing type information in the interpreter.
Introduce a tci-specific opcode to handle the difference.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b2c514f9d5cab89814dc8a6b7c98c653ca8523d3
https://github.com/qemu/qemu/commit/b2c514f9d5cab89814dc8a6b7c98c653ca8523d3
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_div_{i32,i64}
Rename to INDEX_op_divs to emphasize signed inputs,
and mirroring INDEX_op_divu_*.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6d1a2365eaee0603347fd2fabd89a8dc935c8ac7
https://github.com/qemu/qemu/commit/6d1a2365eaee0603347fd2fabd89a8dc935c8ac7
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert divu to TCGOutOpBinary
For TCI, we're losing type information in the interpreter.
Introduce a tci-specific opcode to handle the difference.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 961b80aecd1a503eedb885c309a1d5267d89c98c
https://github.com/qemu/qemu/commit/961b80aecd1a503eedb885c309a1d5267d89c98c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_divu_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d6cad9c9278566deb7f646f027c056ba24f7988d
https://github.com/qemu/qemu/commit/d6cad9c9278566deb7f646f027c056ba24f7988d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert div2 to TCGOutOpDivRem
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ee1805b9e66d6b6229270a339586058bbf275412
https://github.com/qemu/qemu/commit/ee1805b9e66d6b6229270a339586058bbf275412
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Merge INDEX_op_div2_{i32,i64}
Rename to INDEX_op_divs2 to emphasize signed inputs,
and mirroring INDEX_op_divu2_*. Document the opcode.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9bf558ed17c274b172549894e8e343e6a1a1508c
https://github.com/qemu/qemu/commit/9bf558ed17c274b172549894e8e343e6a1a1508c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert divu2 to TCGOutOpDivRem
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8109598b683ad2b6b02cd9c79dc15b7fc0b685aa
https://github.com/qemu/qemu/commit/8109598b683ad2b6b02cd9c79dc15b7fc0b685aa
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Merge INDEX_op_divu2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 646f36fead167e924e83d23d0e1dc59c37b5cca5
https://github.com/qemu/qemu/commit/646f36fead167e924e83d23d0e1dc59c37b5cca5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert rem to TCGOutOpBinary
For TCI, we're losing type information in the interpreter.
Introduce a tci-specific opcode to handle the difference.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9a6bc1840ec105902bda1a59c42e9e0c56a9ed05
https://github.com/qemu/qemu/commit/9a6bc1840ec105902bda1a59c42e9e0c56a9ed05
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_rem_{i32,i64}
Rename to INDEX_op_rems to emphasize signed inputs,
and mirroring INDEX_op_remu_*.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 967e7ccd9c5c6a5a2cc5d7a101cd24acced22749
https://github.com/qemu/qemu/commit/967e7ccd9c5c6a5a2cc5d7a101cd24acced22749
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert remu to TCGOutOpBinary
For TCI, we're losing type information in the interpreter.
Introduce a tci-specific opcode to handle the difference.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cd9acd2049a385e54314d58f35b4bfce7c031d55
https://github.com/qemu/qemu/commit/cd9acd2049a385e54314d58f35b4bfce7c031d55
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_remu_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 27d21ee7c79133e5dfdab8f160f547e833dc5dd0
https://github.com/qemu/qemu/commit/27d21ee7c79133e5dfdab8f160f547e833dc5dd0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert shl to TCGOutOpBinary
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6ca594517ab389f3095c4aab745e168cdd8e8ff5
https://github.com/qemu/qemu/commit/6ca594517ab389f3095c4aab745e168cdd8e8ff5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_shl_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: edd6ba8a6bc804153a8fe643a7e2dae0802db98c
https://github.com/qemu/qemu/commit/edd6ba8a6bc804153a8fe643a7e2dae0802db98c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert shr to TCGOutOpBinary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 74dbd36f1f87bd7fc4705644d63c5561a23b0567
https://github.com/qemu/qemu/commit/74dbd36f1f87bd7fc4705644d63c5561a23b0567
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_shr_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b5aafbaa834653abd4c208794bacbc53a4c1bc16
https://github.com/qemu/qemu/commit/b5aafbaa834653abd4c208794bacbc53a4c1bc16
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert sar to TCGOutOpBinary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3949f365eb6e7c934831c65c67b729562846ede9
https://github.com/qemu/qemu/commit/3949f365eb6e7c934831c65c67b729562846ede9
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_sar_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8726c7d79967c740f7d5a963ac2d855354805cd2
https://github.com/qemu/qemu/commit/8726c7d79967c740f7d5a963ac2d855354805cd2
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Do not require both rotr and rotl from the backend
Many host architectures do not implement both rotate right
and rotate left and require the compiler to negate the
shift count to rotate the opposite direction. We have been
requiring the backend to perform this transformation.
Do this during opcode expansion so that the next patch
can drop support where possible in the backend.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 03568c0d539581c6e86263d2fd7396f5a1e25a6b
https://github.com/qemu/qemu/commit/03568c0d539581c6e86263d2fd7396f5a1e25a6b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert rotl, rotr to TCGOutOpBinary
For aarch64, arm, loongarch64, mips, we can drop rotl.
For ppc, s390x we can drop rotr.
Only x86, riscv, tci have both rotl and rotr.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 005a87e148dc20f59835b328336240759703d63d
https://github.com/qemu/qemu/commit/005a87e148dc20f59835b328336240759703d63d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_rot{l,r}_{i32,i64}
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8b915879b0fdd05afab41f0ca156113811ebac38
https://github.com/qemu/qemu/commit/8b915879b0fdd05afab41f0ca156113811ebac38
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert clz to TCGOutOpBinary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5a5bb0a5a0b879c8f110c6a9bde9146181ef840c
https://github.com/qemu/qemu/commit/5a5bb0a5a0b879c8f110c6a9bde9146181ef840c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_clz_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e3fcde59c92fb421789890c145d5fffdd3d1672d
https://github.com/qemu/qemu/commit/e3fcde59c92fb421789890c145d5fffdd3d1672d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert ctz to TCGOutOpBinary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c96447d838d67db509cde1a190132e14b8672055
https://github.com/qemu/qemu/commit/c96447d838d67db509cde1a190132e14b8672055
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_ctz_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f8fa1dae3db5493617ff42e8ccfd797058df243e
https://github.com/qemu/qemu/commit/f8fa1dae3db5493617ff42e8ccfd797058df243e
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert ctpop to TCGOutOpUnary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 97218ae918b1504a63623130f3dc8f4b423b5f1b
https://github.com/qemu/qemu/commit/97218ae918b1504a63623130f3dc8f4b423b5f1b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_ctpop_{i32,i64}
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5641afdf9b496933596fd0bd5fa9cad0033405d4
https://github.com/qemu/qemu/commit/5641afdf9b496933596fd0bd5fa9cad0033405d4
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert muls2 to TCGOutOpMul2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bfe964809bf6ce951b2e674929d7b730c754e298
https://github.com/qemu/qemu/commit/bfe964809bf6ce951b2e674929d7b730c754e298
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_muls2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d37bc370fcad08698e4b6de99184361a2cf71ac0
https://github.com/qemu/qemu/commit/d37bc370fcad08698e4b6de99184361a2cf71ac0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert mulu2 to TCGOutOpMul2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d776198cd31d1578c4b0239dc80cb2841e86f2f8
https://github.com/qemu/qemu/commit/d776198cd31d1578c4b0239dc80cb2841e86f2f8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_mulu2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 84f57d50ac25a24870de6d19f5b588083a4899e2
https://github.com/qemu/qemu/commit/84f57d50ac25a24870de6d19f5b588083a4899e2
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
Log Message:
-----------
tcg/loongarch64: Support negsetcond
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ce27066de1bf9e44486834bfeb0aa44022f98ab9
https://github.com/qemu/qemu/commit/ce27066de1bf9e44486834bfeb0aa44022f98ab9
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Support negsetcond
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9204be8dec1a52e943185df392377d8853decf93
https://github.com/qemu/qemu/commit/9204be8dec1a52e943185df392377d8853decf93
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Support negsetcond
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f791458932a21f8d99694af412304abfbce83765
https://github.com/qemu/qemu/commit/f791458932a21f8d99694af412304abfbce83765
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/arm/tcg-target-has.h
M tcg/i386/tcg-target-has.h
M tcg/loongarch64/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
M tcg/s390x/tcg-target-has.h
M tcg/sparc64/tcg-target-has.h
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg: Remove TCG_TARGET_HAS_negsetcond_{i32,i64}
All targets now provide negsetcond, so remove the conditional.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5a7b38c8ca056f1ffbb488c1b7c97636b1f3b22b
https://github.com/qemu/qemu/commit/5a7b38c8ca056f1ffbb488c1b7c97636b1f3b22b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert setcond, negsetcond to TCGOutOpSetcond
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a363e1e179445102d7940e92d394d6c00c126f13
https://github.com/qemu/qemu/commit/a363e1e179445102d7940e92d394d6c00c126f13
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/sh4/translate.c
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_{neg}setcond_{i32,i64}`
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 99ac4706b35a2c16e2bf4437e966fc39c41ed67d
https://github.com/qemu/qemu/commit/99ac4706b35a2c16e2bf4437e966fc39c41ed67d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert brcond to TCGOutOpBrcond
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b6d69fcefbd45ca33b896abfbc8e27e0f713bdf0
https://github.com/qemu/qemu/commit/b6d69fcefbd45ca33b896abfbc8e27e0f713bdf0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_brcond_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1f406e46785e60e274a9c581d6fd07e05a6ff4e0
https://github.com/qemu/qemu/commit/1f406e46785e60e274a9c581d6fd07e05a6ff4e0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert movcond to TCGOutOpMovcond
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ea46c4bce8c8a8285e6715c1bac29f5b73f5062b
https://github.com/qemu/qemu/commit/ea46c4bce8c8a8285e6715c1bac29f5b73f5062b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_movcond_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 298b3b548656ea89ff6fd4251bc7319986b79c67
https://github.com/qemu/qemu/commit/298b3b548656ea89ff6fd4251bc7319986b79c67
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Drop fallback constant loading in tcg_out_cmp
Use U and C constraints for brcond2 and setcond2, so that tcg_out_cmp2
automatically passes in-range constants to tcg_out_cmp.
Tested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cd2d9b181a67517fb7bbe8f0c8a81e2284207241
https://github.com/qemu/qemu/commit/cd2d9b181a67517fb7bbe8f0c8a81e2284207241
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Expand arguments to tcg_out_cmp2
Pass explicit arguments instead of arrays.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c1e84acb7a87c23494f706c7045956ffaff5435a
https://github.com/qemu/qemu/commit/c1e84acb7a87c23494f706c7045956ffaff5435a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Expand arguments to tcg_out_cmp2
Tested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f408df587a0459c0e44414d1c0c72a7926ce8f3c
https://github.com/qemu/qemu/commit/f408df587a0459c0e44414d1c0c72a7926ce8f3c
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert brcond2_i32 to TCGOutOpBrcond2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e579c717cb1176d2cd8bd24d9b0e9c6a4b1a0d71
https://github.com/qemu/qemu/commit/e579c717cb1176d2cd8bd24d9b0e9c6a4b1a0d71
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert setcond2_i32 to TCGOutOpSetcond2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5fa8e13872b0ecab7e1bc1f75c65281983df52e5
https://github.com/qemu/qemu/commit/5fa8e13872b0ecab7e1bc1f75c65281983df52e5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert bswap16 to TCGOutOpBswap
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0dd07ee1122abaf1adb4f1e00a8e0b89937f53bd
https://github.com/qemu/qemu/commit/0dd07ee1122abaf1adb4f1e00a8e0b89937f53bd
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_bswap16_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: d7b15a25a707f977e39af20c9f14a5ac4971c762
https://github.com/qemu/qemu/commit/d7b15a25a707f977e39af20c9f14a5ac4971c762
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert bswap32 to TCGOutOpBswap
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7498d882cbe39ae7df4315ea006830e640f0d47b
https://github.com/qemu/qemu/commit/7498d882cbe39ae7df4315ea006830e640f0d47b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_bswap32_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 613b571c93db4cec7d0023b857c1b857af7a3324
https://github.com/qemu/qemu/commit/613b571c93db4cec7d0023b857c1b857af7a3324
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert bswap64 to TCGOutOpUnary
Use TCGOutOpUnary instead of TCGOutOpBswap because the
flags are not used with this opcode; they are merely
present for uniformity with the smaller bswaps.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3ad5d4ccb4bdebdff4e90957bb2b8a93e5e418e2
https://github.com/qemu/qemu/commit/3ad5d4ccb4bdebdff4e90957bb2b8a93e5e418e2
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Rename INDEX_op_bswap64_i64 to INDEX_op_bswap64
Even though bswap64 can only be used with TCG_TYPE_I64,
rename the opcode to maintain uniformity.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 5a4d034f3cbc6d3bffc983b24a2746e9fe9b91cd
https://github.com/qemu/qemu/commit/5a4d034f3cbc6d3bffc983b24a2746e9fe9b91cd
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert extract to TCGOutOpExtract
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 07d5d502f2b4a8eedda3c6bdfcab31dc36d1d1d5
https://github.com/qemu/qemu/commit/07d5d502f2b4a8eedda3c6bdfcab31dc36d1d1d5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_extract_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 05a1129e23bfed1fe799a169e0eca0f676fa5016
https://github.com/qemu/qemu/commit/05a1129e23bfed1fe799a169e0eca0f676fa5016
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert sextract to TCGOutOpExtract
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fa361eefac24dcaa1d6dfbc433fce0652fdd8ba8
https://github.com/qemu/qemu/commit/fa361eefac24dcaa1d6dfbc433fce0652fdd8ba8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_sextract_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b7b7347fe391f134c7ea616c0593d3ea835d5eea
https://github.com/qemu/qemu/commit/b7b7347fe391f134c7ea616c0593d3ea835d5eea
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert ext_i32_i64 to TCGOutOpUnary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c1ad25de11ccf47a650c860f490864dcf7fe7675
https://github.com/qemu/qemu/commit/c1ad25de11ccf47a650c860f490864dcf7fe7675
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert extu_i32_i64 to TCGOutOpUnary
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1e6fec9dd90756b22331a3c4c6859c51ad3a2c3e
https://github.com/qemu/qemu/commit/1e6fec9dd90756b22331a3c4c6859c51ad3a2c3e
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert extrl_i64_i32 to TCGOutOpUnary
Drop the cast from TCGv_i64 to TCGv_i32 in tcg_gen_extrl_i64_i32
an emit extrl_i64_i32 unconditionally. Move that special case
to tcg_gen_code when we find out if the output is live or dead.
In this way even hosts that canonicalize truncations can make
use of a store directly from the 64-bit host register.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b3b139766424d022dc3455b711837dc6acf0724b
https://github.com/qemu/qemu/commit/b3b139766424d022dc3455b711837dc6acf0724b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert extrh_i64_i32 to TCGOutOpUnary
At the same time, make extrh_i64_i32 mandatory. This closes a hole
in which move arguments could be cast between TCGv_i32 and TCGv_i64.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cf4905c03135f1181e86c618426f8d6c703b38c0
https://github.com/qemu/qemu/commit/cf4905c03135f1181e86c618426f8d6c703b38c0
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert deposit to TCGOutOpDeposit
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a5a8dd33aad1ada9b05968e8b93033bdbdfdbca2
https://github.com/qemu/qemu/commit/a5a8dd33aad1ada9b05968e8b93033bdbdfdbca2
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Improve deposit
Use ANDI for deposit 0 into a register.
Use UBFIZ, aka UBFM, for deposit register into 0.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4d137ff819bae33d045f13bb9186e3a2c71cb7e4
https://github.com/qemu/qemu/commit/4d137ff819bae33d045f13bb9186e3a2c71cb7e4
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_deposit_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c8f9f70047e17ce70e016bc59fe7857123f3cbd5
https://github.com/qemu/qemu/commit/c8f9f70047e17ce70e016bc59fe7857123f3cbd5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert extract2 to TCGOutOpExtract2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 61d6a8767a5d4cd4fe5086ef98b53614ae099104
https://github.com/qemu/qemu/commit/61d6a8767a5d4cd4fe5086ef98b53614ae099104
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M target/i386/tcg/emit.c.inc
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
Log Message:
-----------
tcg: Merge INDEX_op_extract2_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3ff7e44ef35924f76dbe36510c54c27e72af9121
https://github.com/qemu/qemu/commit/3ff7e44ef35924f76dbe36510c54c27e72af9121
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Expand fallback add2 with 32-bit operations
No need to expand to i64 to perform the add.
This is smaller on a loongarch64 host, e.g.
bstrpick_d r28, r27, 31, 0
bstrpick_d r29, r24, 31, 0
add_d r28, r28, r29
addi_w r29, r28, 0
srai_d r28, r28, 32
---
add_w r28, r27, r24
sltu r29, r28, r24
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3db22914ced9bb3683bffa03729608be0c42f666
https://github.com/qemu/qemu/commit/3db22914ced9bb3683bffa03729608be0c42f666
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Expand fallback sub2 with 32-bit operations
No need to expand to i64 to perform the subtract.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 8dc1bdf79553594287b6c3f9185fe028307aedcb
https://github.com/qemu/qemu/commit/8dc1bdf79553594287b6c3f9185fe028307aedcb
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/ppc/tcg-target-has.h
M tcg/tcg-has.h
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg: Do not default add2/sub2_i32 for 32-bit hosts
Require TCG_TARGET_HAS_{add2,sub2}_i32 be defined,
one way or another.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 52c49c79b820ceeff10c7c414f747f9bbb39f6c9
https://github.com/qemu/qemu/commit/52c49c79b820ceeff10c7c414f747f9bbb39f6c9
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
Log Message:
-----------
tcg/mips: Drop support for add2/sub2
We now produce exactly the same code via generic expansion.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0e08be0f5482af78f7ed703f665287964d1650f5
https://github.com/qemu/qemu/commit/0e08be0f5482af78f7ed703f665287964d1650f5
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
Log Message:
-----------
tcg/riscv: Drop support for add2/sub2
We now produce exactly the same code via generic expansion.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7d10d8e076201e968d57f1c2f5ffd8c88ae1eec9
https://github.com/qemu/qemu/commit/7d10d8e076201e968d57f1c2f5ffd8c88ae1eec9
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Move i into each for loop in liveness_pass_1
Use per-loop variables instead of one 'i' for the function.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3e3689df4e05eb76b64a9e45247d87f9dad03177
https://github.com/qemu/qemu/commit/3e3689df4e05eb76b64a9e45247d87f9dad03177
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Sink def, nb_iargs, nb_oargs loads in liveness_pass_1
Sink the sets of the def, nb_iargs, nb_oargs variables to
the default and do_not_remove labels. They're not really
needed beforehand, and it avoids preceding code from having
to keep them up-to-date. Note that def had *not* been kept
up-to-date; thankfully only def->flags had been used and
those bits were constant between opcode changes.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 76f42780292c16a0d2f36cbbfbaf57495cd4d5e8
https://github.com/qemu/qemu/commit/76f42780292c16a0d2f36cbbfbaf57495cd4d5e8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M tcg/optimize.c
M tcg/tcg.c
Log Message:
-----------
tcg: Add add/sub with carry opcodes and infrastructure
Liveness needs to track carry-live state in order to
determine if the (hidden) output of the opcode is used.
Code generation needs to track carry-live state in order
to avoid clobbering cpu flags when loading constants.
So far, output routines and backends are unchanged.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: ee60315210058c9b3d0869b2046eeb254ba33f3a
https://github.com/qemu/qemu/commit/ee60315210058c9b3d0869b2046eeb254ba33f3a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Add TCGOutOp structures for add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: aeb3514bd06b278dd026c90e8f71ca5b32762ab9
https://github.com/qemu/qemu/commit/aeb3514bd06b278dd026c90e8f71ca5b32762ab9
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: Handle add/sub with carry opcodes
Propagate known carry when possible, and simplify the opcodes
to not require carry-in when known. The result will be cleaned
up further by the subsequent liveness analysis pass.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e2f5ee36afb3b5306c99f40044534ae7d2580114
https://github.com/qemu/qemu/commit/e2f5ee36afb3b5306c99f40044534ae7d2580114
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/optimize.c
Log Message:
-----------
tcg/optimize: With two const operands, prefer 0 in arg1
For most binary operands, two const operands fold.
However, the add/sub carry opcodes have a third input.
Prefer "reg, zero, const" since many risc hosts have a
zero register that can fit a "reg, reg, const" insn format.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: c4d2e3d736197bb2d82bd37de0de1819222d9768
https://github.com/qemu/qemu/commit/c4d2e3d736197bb2d82bd37de0de1819222d9768
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Use add carry opcodes to expand add2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7a89deae635ceaf687973dd95e4714af27a3f9d2
https://github.com/qemu/qemu/commit/7a89deae635ceaf687973dd95e4714af27a3f9d2
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op.c
Log Message:
-----------
tcg: Use sub carry opcodes to expand sub2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1f049cc5fda405c46de94f9328f0e3f84c0c993b
https://github.com/qemu/qemu/commit/1f049cc5fda405c46de94f9328f0e3f84c0c993b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Honor carry_live in tcg_out_movi
Do not clobber flags if they're live. Required in order
to perform register allocation on add/sub carry opcodes.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e37e98b711975752d592e7b2daf11d320d0a8daf
https://github.com/qemu/qemu/commit/e37e98b711975752d592e7b2daf11d320d0a8daf
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0ad6d64b7be6287f8c07c72f8462ef5635b1e2da
https://github.com/qemu/qemu/commit/0ad6d64b7be6287f8c07c72f8462ef5635b1e2da
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target.c.inc
Log Message:
-----------
tcg/i386: Special case addci r, 0, 0
Using addci with two zeros as input in order to capture the value
of the carry-in bit is common. Special case this with sbb+neg so
that we do not have to load 0 into a register first.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: db3feb02b82d388d85a0c0a14d62f1a625f626a4
https://github.com/qemu/qemu/commit/db3feb02b82d388d85a0c0a14d62f1a625f626a4
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M include/tcg/tcg-op-common.h
M include/tcg/tcg-op.h
M tcg/tcg-op.c
Log Message:
-----------
tcg: Add tcg_gen_addcio_{i32,i64,tl}
Create a function for performing an add with carry-in
and producing carry out. The carry-out result is boolean.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: eea0f7ea5170b47aa2cd6f6ad077e48702aad6f3
https://github.com/qemu/qemu/commit/eea0f7ea5170b47aa2cd6f6ad077e48702aad6f3
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Use tcg_gen_addcio_* for ADCS
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 14e9ff8514bcae95d45dc8603f1ef33ad2f1dce1
https://github.com/qemu/qemu/commit/14e9ff8514bcae95d45dc8603f1ef33ad2f1dce1
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Use tcg_gen_addcio_i64
Use this in do_add, do_sub, and do_ds, all of which need
add with carry-in and carry-out.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fcfbd8f4a9c3cbc09376230093d28e14acf7854b
https://github.com/qemu/qemu/commit/fcfbd8f4a9c3cbc09376230093d28e14acf7854b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Use tcg_gen_addcio_i32
Use this in gen_addc and gen_rsubc, both of which need
add with carry-in and carry-out.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 02b9d791be10ea9e4c8fdfe4cfdc2a6a0de7e810
https://github.com/qemu/qemu/commit/02b9d791be10ea9e4c8fdfe4cfdc2a6a0de7e810
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Use tcg_gen_addcio_* for ADDC
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3a6ec7d71a4e268a6be319cf2efa780091d42d30
https://github.com/qemu/qemu/commit/3a6ec7d71a4e268a6be319cf2efa780091d42d30
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Use tcg_gen_addcio_tl for ADD and SUBF
Tested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 206c23e4720cd2b7668197887d1694bd346e979e
https://github.com/qemu/qemu/commit/206c23e4720cd2b7668197887d1694bd346e979e
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/s390x/tcg/translate.c
Log Message:
-----------
target/s390x: Use tcg_gen_addcio_i64 for op_addc64
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 68188214d5b5dc80acc9143f6bdca25fc06f6e2b
https://github.com/qemu/qemu/commit/68188214d5b5dc80acc9143f6bdca25fc06f6e2b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Use tcg_gen_addcio_i32 for addc
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 6ed4d97ff7fbd2ef3d0d3f1f06d89560955873b8
https://github.com/qemu/qemu/commit/6ed4d97ff7fbd2ef3d0d3f1f06d89560955873b8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/sparc/translate.c
Log Message:
-----------
target/sparc: Use tcg_gen_addcio_tl for gen_op_addcc_int
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 867878c112a0c8bbf7590a948ea291f1f1d61209
https://github.com/qemu/qemu/commit/867878c112a0c8bbf7590a948ea291f1f1d61209
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Use tcg_gen_addcio_i32 for gen_addc_CC
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 75351891b85f5fe4bd3c1e281d0d9d2dae097e6a
https://github.com/qemu/qemu/commit/75351891b85f5fe4bd3c1e281d0d9d2dae097e6a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
Log Message:
-----------
tcg/aarch64: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: b15c0d11a28e6be7156b6920a7a5b2179112b1fa
https://github.com/qemu/qemu/commit/b15c0d11a28e6be7156b6920a7a5b2179112b1fa
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
Log Message:
-----------
tcg/arm: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 2329da9605b0f1b7bd59f58afb5ab2154d0af137
https://github.com/qemu/qemu/commit/2329da9605b0f1b7bd59f58afb5ab2154d0af137
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target-con-str.h
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
Log Message:
-----------
tcg/ppc: Implement add/sub carry opcodes
Tested-by: Nicholas Piggin <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 1b6e25e300e78cf8d8581245c2f8339c5b423d30
https://github.com/qemu/qemu/commit/1b6e25e300e78cf8d8581245c2f8339c5b423d30
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Honor carry_live in tcg_out_movi
Do not clobber flags if they're live. Required in order
to perform register allocation on add/sub carry opcodes.
LA and AGHI are the same size, so use LA unconditionally.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 19b9fc2a39c733f585388918e4e093f08e2c33eb
https://github.com/qemu/qemu/commit/19b9fc2a39c733f585388918e4e093f08e2c33eb
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Add TCG_CT_CONST_N32
We were using S32 | U32 for add2/sub2. But the ALGFI and SLGFI
insns that implement this both have uint32_t immediates.
This makes the composite range balanced and
enables use of -0xffffffff ... -0x80000001.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: cda7f93fa2fbf52e0fc70e4078caf8e7f7d3bd6f
https://github.com/qemu/qemu/commit/cda7f93fa2fbf52e0fc70e4078caf8e7f7d3bd6f
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 41dd55c79c0a1b1a4bf573821b81d97e6d4c159a
https://github.com/qemu/qemu/commit/41dd55c79c0a1b1a4bf573821b81d97e6d4c159a
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/s390x/tcg-target.c.inc
Log Message:
-----------
tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 809069eaa3d803092adaa06cec770d78db44211d
https://github.com/qemu/qemu/commit/809069eaa3d803092adaa06cec770d78db44211d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
Pass the sparc COND_* value not the tcg TCG_COND_* value.
This makes the usage within add2/sub2 clearer.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 9dd1ea33b238d8b661b7541ebdb122b7cae6fd19
https://github.com/qemu/qemu/commit/9dd1ea33b238d8b661b7541ebdb122b7cae6fd19
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4b0ee858be252ed272a758e5b6f894717e911d51
https://github.com/qemu/qemu/commit/4b0ee858be252ed272a758e5b6f894717e911d51
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg/tci: Implement add/sub carry opcodes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: f2b1708e8080ab1beb0a2bf52a79a51e8de335cb
https://github.com/qemu/qemu/commit/f2b1708e8080ab1beb0a2bf52a79a51e8de335cb
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target-has.h
M tcg/arm/tcg-target-has.h
M tcg/i386/tcg-target-has.h
M tcg/loongarch64/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
M tcg/s390x/tcg-target-has.h
M tcg/sparc64/tcg-target-has.h
M tcg/tcg-has.h
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg: Remove add2/sub2 opcodes
All uses have been replaced by add/sub carry opcodes.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e038696c9293f34dc7ccd4adac2c2f221a65a8e3
https://github.com/qemu/qemu/commit/e038696c9293f34dc7ccd4adac2c2f221a65a8e3
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Formalize tcg_out_mb
Most tcg backends already have a function for this;
the rest can split one out from tcg_out_op.
Call it directly from tcg_gen_code.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3752a5a5ba33448fe40556d781e8096b5b9dd916
https://github.com/qemu/qemu/commit/3752a5a5ba33448fe40556d781e8096b5b9dd916
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Formalize tcg_out_br
Split these functions out from tcg_out_op.
Call it directly from tcg_gen_code.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: fee03fdde32c3d5b26429b7e691f78d1ee03d631
https://github.com/qemu/qemu/commit/fee03fdde32c3d5b26429b7e691f78d1ee03d631
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Formalize tcg_out_goto_ptr
Split these functions out from tcg_out_op.
Define outop_goto_ptr generically.
Call tcg_out_goto_ptr from tcg_reg_alloc_op.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 0de5c9d1f56332554c48152f535b47a1a0c2af7b
https://github.com/qemu/qemu/commit/0de5c9d1f56332554c48152f535b47a1a0c2af7b
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert ld to TCGOutOpLoad
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: e996804d40c10572550a1d3ca936a5dfb29ca0fc
https://github.com/qemu/qemu/commit/e996804d40c10572550a1d3ca936a5dfb29ca0fc
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_ld*_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 4a686aa9d9dcf8805de654ae09788c4e264c1439
https://github.com/qemu/qemu/commit/4a686aa9d9dcf8805de654ae09788c4e264c1439
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert st to TCGOutOpStore
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: a28f151d61604feae1d6c75b79e67d1c6c6a8b18
https://github.com/qemu/qemu/commit/a28f151d61604feae1d6c75b79e67d1c6c6a8b18
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/optimize.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_st*_{i32,i64}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: bf7ca5fb3032b95fd83dbb9883e904ee28baa229
https://github.com/qemu/qemu/commit/bf7ca5fb3032b95fd83dbb9883e904ee28baa229
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/tcg-op-ldst.c
Log Message:
-----------
tcg: Stash MemOp size in TCGOP_FLAGS
This will enable removing INDEX_op_qemu_st8_*_i32,
by exposing the operand size to constraint selection.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 33aba058c8fcc9b1581b03a1fbac45d8d91baac6
https://github.com/qemu/qemu/commit/33aba058c8fcc9b1581b03a1fbac45d8d91baac6
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target-has.h
M tcg/arm/tcg-target-has.h
M tcg/i386/tcg-target-con-str.h
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-has.h
M tcg/mips/tcg-target-has.h
M tcg/optimize.c
M tcg/ppc/tcg-target-has.h
M tcg/riscv/tcg-target-has.h
M tcg/s390x/tcg-target-has.h
M tcg/sparc64/tcg-target-has.h
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci/tcg-target-has.h
Log Message:
-----------
tcg: Remove INDEX_op_qemu_st8_*
The i386 backend can now check TCGOP_FLAGS to select
the correct set of constraints.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: aae2456ac0b4eb91da7ee8a4b31052f2e8a77af8
https://github.com/qemu/qemu/commit/aae2456ac0b4eb91da7ee8a4b31052f2e8a77af8
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M include/tcg/tcg-opc.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-op-ldst.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
Merge into INDEX_op_{ld,st,ld2,st2}, where "2" indicates that two
inputs or outputs are required. This simplifies the processing of
i64/i128 depending on host word size.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 3bedb9d3e2855606f2b4982ce07f8ae399957c3d
https://github.com/qemu/qemu/commit/3bedb9d3e2855606f2b4982ce07f8ae399957c3d
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 86fe5c2597ca165228ee9cd082886846de4c9ece
https://github.com/qemu/qemu/commit/86fe5c2597ca165228ee9cd082886846de4c9ece
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: eafecf08059953a2d1d06b6a6ded3c56916cbdd4
https://github.com/qemu/qemu/commit/eafecf08059953a2d1d06b6a6ded3c56916cbdd4
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target.c.inc
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg.c
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
tcg: Remove tcg_out_op
All integer opcodes are now converted to TCGOutOp.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 33b6c61cce2403193f9fc3a221f8a8656ba9cc37
https://github.com/qemu/qemu/commit/33b6c61cce2403193f9fc3a221f8a8656ba9cc37
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Unexport use_vis3_instructions
This variable is no longer used outside tcg-target.c.inc.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 70ab4f4ed9bbe9bcfdb105681291b4695f151522
https://github.com/qemu/qemu/commit/70ab4f4ed9bbe9bcfdb105681291b4695f151522
Author: Richard Henderson <[email protected]>
Date: 2025-04-28 (Mon, 28 Apr 2025)
Changed paths:
M tcg/sparc64/tcg-target.c.inc
Log Message:
-----------
tcg/sparc64: Implement CTPOP
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Commit: 71a30d54e6ab1d5c102a8bee2c263414697402ea
https://github.com/qemu/qemu/commit/71a30d54e6ab1d5c102a8bee2c263414697402ea
Author: Kevin Wolf <[email protected]>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M block/file-posix.c
Log Message:
-----------
file-posix: Fix crash on discard_granularity == 0
Block devices that don't support discard have a discard_granularity of
0. Currently, this results in a division by zero when we try to make
sure that it's a multiple of request_alignment. Only try to update
bs->bl.pdiscard_alignment when we got a non-zero discard_granularity
from sysfs.
Fixes: f605796aae4 ('file-posix: probe discard alignment on Linux block
devices')
Signed-off-by: Kevin Wolf <[email protected]>
Reviewed-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Eric Blake <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: ffd642cb2ca25262342311a3bf2e8a77a00e6dfd
https://github.com/qemu/qemu/commit/ffd642cb2ca25262342311a3bf2e8a77a00e6dfd
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M docs/devel/tcg-ops.rst
M include/tcg/tcg-op-common.h
M include/tcg/tcg-op.h
M include/tcg/tcg-opc.h
M include/tcg/tcg.h
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate-sve.c
M target/arm/tcg/translate.c
M target/hppa/translate.c
M target/i386/tcg/emit.c.inc
M target/microblaze/translate.c
M target/openrisc/translate.c
M target/ppc/translate.c
M target/s390x/tcg/translate.c
M target/sh4/translate.c
M target/sparc/translate.c
M target/tricore/translate.c
M tcg/aarch64/tcg-target-con-set.h
M tcg/aarch64/tcg-target-has.h
M tcg/aarch64/tcg-target.c.inc
M tcg/arm/tcg-target-con-set.h
M tcg/arm/tcg-target-has.h
M tcg/arm/tcg-target.c.inc
M tcg/i386/tcg-target-con-set.h
M tcg/i386/tcg-target-con-str.h
M tcg/i386/tcg-target-has.h
M tcg/i386/tcg-target.c.inc
M tcg/loongarch64/tcg-target-con-set.h
M tcg/loongarch64/tcg-target-con-str.h
M tcg/loongarch64/tcg-target-has.h
M tcg/loongarch64/tcg-target.c.inc
M tcg/mips/tcg-target-con-set.h
M tcg/mips/tcg-target-con-str.h
M tcg/mips/tcg-target-has.h
M tcg/mips/tcg-target.c.inc
M tcg/optimize.c
M tcg/ppc/tcg-target-con-set.h
M tcg/ppc/tcg-target-con-str.h
M tcg/ppc/tcg-target-has.h
M tcg/ppc/tcg-target.c.inc
M tcg/riscv/tcg-target-con-set.h
M tcg/riscv/tcg-target-con-str.h
M tcg/riscv/tcg-target-has.h
M tcg/riscv/tcg-target.c.inc
M tcg/s390x/tcg-target-con-set.h
M tcg/s390x/tcg-target-con-str.h
M tcg/s390x/tcg-target-has.h
M tcg/s390x/tcg-target.c.inc
M tcg/sparc64/tcg-target-con-set.h
M tcg/sparc64/tcg-target-has.h
M tcg/sparc64/tcg-target.c.inc
M tcg/tcg-has.h
M tcg/tcg-internal.h
M tcg/tcg-op-ldst.c
M tcg/tcg-op.c
M tcg/tcg.c
M tcg/tci.c
M tcg/tci/tcg-target-has.h
M tcg/tci/tcg-target-opc.h.inc
M tcg/tci/tcg-target.c.inc
Log Message:
-----------
Merge tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu into staging
Convert TCG backend code generators to TCGOutOp structures,
decomposing the monolithic tcg_out_op functions.
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# gpg: Signature made Tue 29 Apr 2025 13:36:07 EDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[full]
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* tag 'pull-tcg-20250429' of https://gitlab.com/rth7680/qemu: (161 commits)
tcg/sparc64: Implement CTPOP
tcg/sparc64: Unexport use_vis3_instructions
tcg: Remove tcg_out_op
tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}
tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}
tcg: Merge INDEX_op_{ld,st}_{i32,i64,i128}
tcg: Remove INDEX_op_qemu_st8_*
tcg: Stash MemOp size in TCGOP_FLAGS
tcg: Merge INDEX_op_st*_{i32,i64}
tcg: Convert st to TCGOutOpStore
tcg: Merge INDEX_op_ld*_{i32,i64}
tcg: Convert ld to TCGOutOpLoad
tcg: Formalize tcg_out_goto_ptr
tcg: Formalize tcg_out_br
tcg: Formalize tcg_out_mb
tcg: Remove add2/sub2 opcodes
tcg/tci: Implement add/sub carry opcodes
tcg/sparc64: Implement add/sub carry opcodes
tcg/sparc64: Hoist tcg_cond_to_bcond lookup out of tcg_out_movcc
tcg/s390x: Use ADD LOGICAL WITH SIGNED IMMEDIATE
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 5134cf9b5d3aee4475fe7e1c1c11b093731073cf
https://github.com/qemu/qemu/commit/5134cf9b5d3aee4475fe7e1c1c11b093731073cf
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-04-30 (Wed, 30 Apr 2025)
Changed paths:
M block/file-posix.c
Log Message:
-----------
Merge tag 'block-pull-request' of https://gitlab.com/stefanha/qemu into
staging
Pull request
Kevin's fix for the divide-by-zero in my recent discard commit, triggered when
a host block device does not support discard.
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# gpg: Signature made Wed 30 Apr 2025 11:47:07 EDT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <[email protected]>" [ultimate]
# gpg: aka "Stefan Hajnoczi <[email protected]>" [ultimate]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'block-pull-request' of https://gitlab.com/stefanha/qemu:
file-posix: Fix crash on discard_granularity == 0
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/73d29ea2417b...5134cf9b5d3a
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