Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: d2a88aca766697e8490504313d23002c3315ee93
https://github.com/qemu/qemu/commit/d2a88aca766697e8490504313d23002c3315ee93
Author: Sunil V L <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
M include/hw/riscv/virt.h
Log Message:
-----------
hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure
When the IOMMU is implemented as a PCI device, its BDF is created
locally in virt.c. However, the same BDF is also required in
virt-acpi-build.c to support ACPI. Therefore, make this information part
of the global RISCVVirtState structure so that it can be accessed
outside of virt.c as well.
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cd18dbbf9d23f309f3e46c38b99213dbe3d48d17
https://github.com/qemu/qemu/commit/cd18dbbf9d23f309f3e46c38b99213dbe3d48d17
Author: Sunil V L <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt-acpi-build.c
Log Message:
-----------
hw/riscv/virt-acpi-build: Add support for RIMT
RISC-V IO Mapping Table (RIMT) is a new static ACPI table used to
communicate IOMMU information to the OS. Add support for creating this
table when the IOMMU is present. The specification is frozen and
available at [1].
[1] -
https://github.com/riscv-non-isa/riscv-acpi-rimt/releases/download/v0.99/rimt-spec.pdf
Signed-off-by: Sunil V L <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4541d205f03cf1529439f68d2ec5056685189399
https://github.com/qemu/qemu/commit/4541d205f03cf1529439f68d2ec5056685189399
Author: Loïc Lefort <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: don't allow RLB to bypass rule privileges
When Smepmp is supported, mseccfg.RLB allows bypassing locks when writing CSRs
but should not affect interpretation of actual PMP rules.
This is not the case with the current implementation where pmp_hart_has_privs
calls pmp_is_locked which implements mseccfg.RLB bypass.
This commit implements the correct behavior by removing mseccfg.RLB bypass from
pmp_is_locked.
RLB bypass when writing CSRs is implemented by adding a new pmp_is_readonly
function that calls pmp_is_locked and check mseccfg.RLB. pmp_write_cfg and
pmpaddr_csr_write are changed to use this new function.
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 915b203745540e908943758f78f5da49e0a15e45
https://github.com/qemu/qemu/commit/915b203745540e908943758f78f5da49e0a15e45
Author: Loïc Lefort <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: move Smepmp operation conversion into a function
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 19cf1a7d9e59b71bf8d6571d4747e5c82667c3d1
https://github.com/qemu/qemu/commit/19cf1a7d9e59b71bf8d6571d4747e5c82667c3d1
Author: Loïc Lefort <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: fix checks on writes to pmpcfg in Smepmp MML mode
With Machine Mode Lockdown (mseccfg.MML) set and RLB not set, checks on pmpcfg
writes would match the wrong cases of Smepmp truth table.
The existing code allows writes for the following cases:
- L=1, X=0: cases 8, 10, 12, 14
- L=0, RWX!=WX: cases 0-2, 4-6
This leaves cases 3, 7, 9, 11, 13, 15 for which writes are ignored.
>From the Smepmp specification: "Adding a rule with executable privileges that
either is M-mode-only or a locked Shared-Region is not possible (...)" This
description matches cases 9-11, 13 of the truth table.
This commit implements an explicit check for these cases by using
pmp_get_epmp_operation to convert between PMP configuration and Smepmp truth
table cases.
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 0c60c531f53544117f96d508fd9918f78ecf0df5
https://github.com/qemu/qemu/commit/0c60c531f53544117f96d508fd9918f78ecf0df5
Author: Loïc Lefort <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: exit csr writes early if value was not changed
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 986222f0f994671190a94836a373fd64992cd271
https://github.com/qemu/qemu/commit/986222f0f994671190a94836a373fd64992cd271
Author: Loïc Lefort <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: remove redundant check in pmp_is_locked
Remove useless check in pmp_is_locked, the function will return 0 in either
case.
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 28c12c1f2f50d7f7f1ebfc587c4777ecd50aac5b
https://github.com/qemu/qemu/commit/28c12c1f2f50d7f7f1ebfc587c4777ecd50aac5b
Author: Paolo Savini <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
Generate strided vector loads/stores with tcg nodes.
This commit improves the performance of QEMU when emulating strided vector
loads and stores by substituting the call for the helper function with the
generation of equivalent TCG operations.
Signed-off-by: Paolo Savini <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4c1a39eebc6a9f1db816ff6c23e3d42ba52e2601
https://github.com/qemu/qemu/commit/4c1a39eebc6a9f1db816ff6c23e3d42ba52e2601
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/misc/mchp_pfsoc_sysreg.c
Log Message:
-----------
hw/misc: Add MPFS system reset support
Signed-off-by: Sebastian Huber <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cae44a92ab23811deeefa0a44b1bdec6cfa8e4b9
https://github.com/qemu/qemu/commit/cae44a92ab23811deeefa0a44b1bdec6cfa8e4b9
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: More flexible FDT placement for MPFS
If the kernel entry is in the high DRAM area, place the FDT into this
area.
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0c2ca9e4d139acc762325d994614a42dba31be6a
https://github.com/qemu/qemu/commit/0c2ca9e4d139acc762325d994614a42dba31be6a
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: Make FDT optional for MPFS
Real-time kernels such as RTEMS or Zephyr may use a static device tree
built into the kernel image. Do not require to use the -dtb option if
-kernel is used for the microchip-icicle-kit machine. Issue a warning
if no device tree is provided by the user since the machine does not
generate one.
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6dd6f11710c713bd21ac67ab93f6db33169c6b4d
https://github.com/qemu/qemu/commit/6dd6f11710c713bd21ac67ab93f6db33169c6b4d
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
Log Message:
-----------
hw/riscv: Allow direct start of kernel for MPFS
Further customize the -bios and -kernel options behaviour for the
microchip-icicle-kit machine. If "-bios none -kernel filename" is
specified, then do not load a firmware and instead only load and start
the kernel image.
For test runs, use an approach similar to
riscv_find_and_load_firmware().
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e40b75fe5c94c6656e8ffcb0b9559b09882fa01b
https://github.com/qemu/qemu/commit/e40b75fe5c94c6656e8ffcb0b9559b09882fa01b
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/microchip_pfsoc.c
M include/hw/riscv/microchip_pfsoc.h
Log Message:
-----------
hw/riscv: Configurable MPFS CLINT timebase freq
This property enables the setting of the CLINT timebase frequency
through the command line, for example:
-machine microchip-icicle-kit,clint-timebase-frequency=10000000
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dd07ab1121ffd7003ae2cffde3046acd3123bbbd
https://github.com/qemu/qemu/commit/dd07ab1121ffd7003ae2cffde3046acd3123bbbd
Author: Sebastian Huber <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M docs/system/riscv/microchip-icicle-kit.rst
Log Message:
-----------
hw/riscv: microchip_pfsoc: Rework documentation
Mention that running the HSS no longer works. Document the changed boot
options. Reorder documentation blocks. Update URLs.
Signed-off-by: Sebastian Huber <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 9425790aceffc09b730a072cc3fc174d1b084f62
https://github.com/qemu/qemu/commit/9425790aceffc09b730a072cc3fc174d1b084f62
Author: Paolo Savini <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: use tcg ops generation to emulate whole reg rvv loads/stores.
This patch replaces the use of a helper function with direct tcg ops generation
in order to emulate whole register loads and stores. This is done in order to
improve the performance of QEMU.
We still use the helper function when vstart is not 0 at the beginning of the
emulation of the whole register load or store or when we would end up generating
partial loads or stores of vector elements (e.g. emulating 64 bits element loads
with pairs of 32 bits loads on hosts with 32 bits registers).
The latter condition ensures that we are not surprised by a trap in mid-element
and consecutively that we can update vstart correctly.
We also use the helper function when it performs better than tcg for specific
combinations of vector length, number of fields and element size.
Signed-off-by: Paolo Savini <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Richard Handerson <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Reviewed-by: "Alex Bennée" <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d887736225984fcb3926e3f32f3cdc332c03ba8f
https://github.com/qemu/qemu/commit/d887736225984fcb3926e3f32f3cdc332c03ba8f
Author: Paolo Savini <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
Expand the probe_pages helper function to handle probe flags.
This commit expands the probe_pages helper function in
target/riscv/vector_helper.c to handle also the cases in which we need access to
the flags raised while probing the memory and the host address.
This is done in order to provide a unified interface to probe_access and
probe_access_flags.
The new version of probe_pages can now act as a regular call to probe_access as
before and as a call to probe_access_flags. In the latter case the user need to
pass pointers to flags and host address and a boolean value for nonfault.
The flags and host address will be set and made available as for a direct call
to probe_access_flags.
Signed-off-by: Paolo Savini <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 56cde18d048e1e1f889e31f7553e1f39f03eeec5
https://github.com/qemu/qemu/commit/56cde18d048e1e1f889e31f7553e1f39f03eeec5
Author: Paolo Bonzini <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/riscv_hart.c
Log Message:
-----------
hw/riscv: Fix type conflict of GLib function pointers
qtest_set_command_cb passed to g_once should match GThreadFunc,
which it does not. But using g_once is actually unnecessary,
because the function is called by riscv_harts_realize() under
the Big QEMU Lock.
Reported-by: Kohei Tokunaga <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Kohei Tokunaga <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: ad63158bdb33dab5704ea1cf740d2ea0387175df
https://github.com/qemu/qemu/commit/ad63158bdb33dab5704ea1cf740d2ea0387175df
Author: Ziqiao Kong <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: fix endless translation loop on big endian systems
On big endian systems, pte and updated_pte hold big endian host data
while pte_pa points to little endian target data. This means the branch
at cpu_helper.c:1669 will be always satisfied and restart translation,
causing an endless translation loop.
The correctness of this patch can be deduced by:
old_pte will hold value either from cpu_to_le32/64(pte) or
cpu_to_le32/64(updated_pte), both of wich is litte endian. After that,
an in-place conversion by le32/64_to_cpu(old_pte) ensures that old_pte
now is in native endian, same with pte. Therefore, the endianness of the
both side of if (old_pte != pte) is correct.
Signed-off-by: Ziqiao Kong <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 22b448ccc6611a59d4aa54419f4d88c1f343cb35
https://github.com/qemu/qemu/commit/22b448ccc6611a59d4aa54419f4d88c1f343cb35
Author: Icenowy Zheng <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M common-user/host/riscv/safe-syscall.inc.S
Log Message:
-----------
common-user/host/riscv: use tail pseudoinstruction for calling tail
The j pseudoinstruction maps to a JAL instruction, which can only handle
a jump to somewhere with a signed 20-bit destination. In case of static
linking and LTO'ing this easily leads to "relocation truncated to fit"
error.
Switch to use tail pseudoinstruction, which is the standard way to
tail-call a function in medium code model (emits AUIPC+JALR).
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 3e8d1e4a628bb234c0b5d1ccd510900047181dbd
https://github.com/qemu/qemu/commit/3e8d1e4a628bb234c0b5d1ccd510900047181dbd
Author: Anton Blanchard <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Source vector registers cannot overlap mask register
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: b0450a101d6c88789d0e8df2bcbef61bc7cd159a
https://github.com/qemu/qemu/commit/b0450a101d6c88789d0e8df2bcbef61bc7cd159a
Author: Anton Blanchard <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 629c2a8dd7506e1cb9b6b7127604641632ac453f
https://github.com/qemu/qemu/commit/629c2a8dd7506e1cb9b6b7127604641632ac453f
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to
check mismatched input EEWs encoding constraint
According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.
The vs1 EEW of vrgatherei16.vv is 16.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: fbeaf35838768086b435833cb4dc5182c73ec2bc
https://github.com/qemu/qemu/commit/fbeaf35838768086b435833cb4dc5182c73ec2bc
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to
OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: fda68acb7761af40df78db18e44ca1ff20195fe0
https://github.com/qemu/qemu/commit/fda68acb7761af40df78db18e44ca1ff20195fe0
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss)
instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: b5480a693e3e657108746721ffe434b3bb6e7a72
https://github.com/qemu/qemu/commit/b5480a693e3e657108746721ffe434b3bb6e7a72
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector slide
instructions(OPIVI/OPIVX)
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 411eefd56a3921ddbfdbadca596e1a8593ce834c
https://github.com/qemu/qemu/commit/411eefd56a3921ddbfdbadca596e1a8593ce834c
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector integer extension
instructions(OPMVV)
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 1f090a229f85e662394267680408bd31fd0a99c9
https://github.com/qemu/qemu/commit/1f090a229f85e662394267680408bd31fd0a99c9
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen
instructions
Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: db21c3eb05504c4cedaad4f7b19e588361b02385
https://github.com/qemu/qemu/commit/db21c3eb05504c4cedaad4f7b19e588361b02385
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store
instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 8539a1244bf240d28917effb88a140eb58e45e88
https://github.com/qemu/qemu/commit/8539a1244bf240d28917effb88a140eb58e45e88
Author: Max Chou <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/insn32.decode
Log Message:
-----------
target/riscv: Fix the rvv reserved encoding of unmasked instructions
According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 2669b696e243b64f8ea1a6468dcee255de99f08d
https://github.com/qemu/qemu/commit/2669b696e243b64f8ea1a6468dcee255de99f08d
Author: Anton Blanchard <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix vslidedown with rvv_ta_all_1s
vslidedown always zeroes elements past vl, where it should use the
tail policy.
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 355cdac7d86ca2bc1b3729a6dda0b98deb23a92b
https://github.com/qemu/qemu/commit/355cdac7d86ca2bc1b3729a6dda0b98deb23a92b
Author: Alistair Francis <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add common-user/host/riscv to RISC-V section
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6c8954cb35b1898f94d0d1e60f1abc8d47ae9f02
https://github.com/qemu/qemu/commit/6c8954cb35b1898f94d0d1e60f1abc8d47ae9f02
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Pass ra to riscv_csr_write_fn
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: bfc7936f42bac551bd859b8f32fb1f24dfcfc611
https://github.com/qemu/qemu/commit/bfc7936f42bac551bd859b8f32fb1f24dfcfc611
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Pass ra to riscv_csrrw_do64
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c26c4afd0ffde4f79216975ac34f419d0fcf6795
https://github.com/qemu/qemu/commit/c26c4afd0ffde4f79216975ac34f419d0fcf6795
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Pass ra to riscv_csrrw_do128
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f1304836ea9399253c67b09513fca30f9f4b223e
https://github.com/qemu/qemu/commit/f1304836ea9399253c67b09513fca30f9f4b223e
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/riscv_hart.c
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Pass ra to riscv_csrrw
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 9ef792a78db6b89619c3ccc77ceb3e9d6271dd02
https://github.com/qemu/qemu/commit/9ef792a78db6b89619c3ccc77ceb3e9d6271dd02
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: Pass ra to riscv_csrrw_i128
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dd9953a5541441d283d0e5c53dffaf3938d6e097
https://github.com/qemu/qemu/commit/dd9953a5541441d283d0e5c53dffaf3938d6e097
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/internals.h
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Move insn_len to internals.h
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 7b069906b6ac47dc905d187c72f07ef82b400501
https://github.com/qemu/qemu/commit/7b069906b6ac47dc905d187c72f07ef82b400501
Author: Richard Henderson <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix write_misa vs aligned next_pc
Do not examine a random host return address, but
properly compute the next pc for the guest cpu.
Fixes: f18637cd611 ("RISC-V: Add misa runtime write support")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
[ Changes by AF:
- Change `& ~3` to `& 3`
]
Signed-off-by: Alistair Francis <[email protected]>
Commit: 73f81da0a3628180409a0ae90ece19534bcdf09b
https://github.com/qemu/qemu/commit/73f81da0a3628180409a0ae90ece19534bcdf09b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: minor fixes/tweaks
Remove an unused 'KVMScratchCPU' pointer argument in
kvm_riscv_check_sbi_dbcn_support().
Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will
make a future patch diff easier to read, when changes in
kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made.
Fixes: a6b53378f5 ("target/riscv/kvm: implement SBI debug console (DBCN) calls")
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 906af6de9462c5192547cca0beac2c134659a437
https://github.com/qemu/qemu/commit/906af6de9462c5192547cca0beac2c134659a437
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
'reglist' is being g-malloc'ed but never freed.
Reported-by: Andrew Jones <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: b6096103494506514d9bfa442f62fef36ffc8fba
https://github.com/qemu/qemu/commit/b6096103494506514d9bfa442f62fef36ffc8fba
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: turn u32/u64 reg functions into macros
This change is motivated by a future change w.r.t CSRs management. We
want to handle them the same way as KVM extensions, i.e. a static array
with KVMCPUConfig objs that will be read/write during init and so on.
But to do that properly we must be able to declare a static array that
hold KVM regs.
C does not allow to init static arrays and use functions as
initializers, e.g. we can't do:
.kvm_reg_id = kvm_riscv_reg_id_ulong(...)
When instantiating the array. We can do that with macros though, so our
goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn
every other reg_id_*() function in macros, and ulong will end up using
the macros for u32 and u64, so we'll start with them.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 11766e17616a5a4181d4a63f88adf67ac52c553b
https://github.com/qemu/qemu/commit/11766e17616a5a4181d4a63f88adf67ac52c553b
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_ID_ULONG";
- RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and
RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded
'env' variables when applicable.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: d3b6f1742c36e3a3c1e74cb60646ee98a4e39ea3
https://github.com/qemu/qemu/commit/d3b6f1742c36e3a3c1e74cb60646ee98a4e39ea3
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add kvm_csr_cfgs[]
At this moment we're not checking if the host has support for any
specific CSR before doing get/put regs. This will cause problems if the
host KVM doesn't support it (see [1] as an example).
We'll use the same approach done with the CPU extensions: read all known
KVM CSRs during init() to check for availability, then read/write them
if they are present. This will be made by either using get-reglist or by
directly reading the CSRs.
For now we'll just convert the CSRs to use a kvm_csr_cfg[] array,
reusing the same KVMCPUConfig abstraction we use for extensions, and use
the array in (get|put)_csr_regs() instead of manually listing them. A
lot of boilerplate will be added but at least we'll automate the get/put
procedure for CSRs, i.e. adding a new CSR in the future will be a matter
of adding it in kvm_csr_regs[] and everything else will be taken care
of.
Despite all the code changes no behavioral change is made.
[1]
https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBLbLKhfv=+jb0s...@mail.gmail.com/
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: f396c217a53d9b7960dd002fbb07cfe1d46b27aa
https://github.com/qemu/qemu/commit/f396c217a53d9b7960dd002fbb07cfe1d46b27aa
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: do not read unavailable CSRs
[1] reports that commit 4db19d5b21 broke a KVM guest running kernel 6.6.
This happens because the kernel does not know 'senvcfg', making it
unable to boot because QEMU is reading/wriiting it without any checks.
After converting the CSRs to do "automated" get/put reg procedures in
the previous patch we can now scan for availability. Two functions are
created:
- kvm_riscv_read_csr_cfg_legacy() will check if the CSR exists by brute
forcing KVM_GET_ONE_REG in each one of them, interpreting an EINVAL
return as indication that the CSR isn't available. This will be use in
absence of KVM_GET_REG_LIST;
- kvm_riscv_read_csr_cfg() will use the existing result of get_reg_list
to check if the CSRs ids are present.
kvm_riscv_init_multiext_cfg() is now kvm_riscv_init_cfg() to reflect that
the function is also dealing with CSRs.
[1]
https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBLbLKhfv=+jb0s...@mail.gmail.com/
Fixes: 4db19d5b21 ("target/riscv/kvm: add missing KVM CSRs")
Reported-by: Andrea Bolognani <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
Commit: 86b8c3821496898cd3bd8eaa1bac71f5c784a2db
https://github.com/qemu/qemu/commit/86b8c3821496898cd3bd8eaa1bac71f5c784a2db
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add senvcfg CSR
We're missing the senvcfg CSRs which is already present in the
KVM UAPI.
Reported-by: Andrew Jones <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 775ac57e0a54b9127bd2ad005675772870cd1932
https://github.com/qemu/qemu/commit/775ac57e0a54b9127bd2ad005675772870cd1932
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: read/write KVM regs via env size
We're going to add support for scounteren in the next patch. KVM defines
as a target_ulong CSR, while QEMU defines env->scounteren as a 32 bit
field. This will cause the current code to read/write a 64 bit CSR in a
32 bit field when running in a 64 bit CPU.
To prevent that, change the current logic to honor the size of the QEMU
storage instead of the KVM CSR reg.
Suggested-by: Andrew Jones <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 8ab99a05f34bab3f9fae49299ee407ead78f0470
https://github.com/qemu/qemu/commit/8ab99a05f34bab3f9fae49299ee407ead78f0470
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add scounteren CSR
Add support for the scounteren KVM CSR. Note that env->scounteren is a
32 bit and all KVM CSRs are target_ulong, so scounteren will be capped
to 32 bits read/writes.
Reported-by: Andrew Jones <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 221e96cb7ae4535bcef7d54d1620a44be88b655e
https://github.com/qemu/qemu/commit/221e96cb7ae4535bcef7d54d1620a44be88b655e
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: enforce s->memmap use in machine_init()
Throughout the code we're accessing the board memmap, most of the time,
by accessing it statically via 'virt_memmap'. This static map is also
assigned in the machine state in s->memmap.
We're also passing it as a variable to some fdt functions, which is
unorthodox since we can spare a function argument by accessing it
statically or via the machine state.
All the current forms are valid but not all of the are scalable. In the
future we will version this board, and then all this code will need
rework because it should point to the updated memmap. In this case,
we'll want to assign the adequate versioned memmap once during init,
in s->memmap like it is being done today, and the rest of the code
will access the updated map via s->memmap.
We're also enforcing the pattern of using s->memmap instead of assigning
it to a temp variable 'memmap'. Code is copy/pasted around all the time
and being consistent is important.
We'll start these rather mechanical changes with virt_machine_init().
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Joel Stanley <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: fb8cf3fd98d7640d2ea3feca65fb40fba09a0235
https://github.com/qemu/qemu/commit/fb8cf3fd98d7640d2ea3feca65fb40fba09a0235
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: remove trivial virt_memmap references
We should use s->memmap instead of virt_memmap to be able to use an
updated memmap when we start versioning the board.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 47e51e5d12740ebdcd797e4771b467ba8c2aba82
https://github.com/qemu/qemu/commit/47e51e5d12740ebdcd797e4771b467ba8c2aba82
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use s->memmap in virt_machine_done()
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6418ff383d53e5872f2746d490885f0a551385a4
https://github.com/qemu/qemu/commit/6418ff383d53e5872f2746d490885f0a551385a4
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
The function can receive the value via s->memmap[VIRT_FW_CFG].base from
the caller, avoiding the use of virt_memmap.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 658e501969d948735669fcf82206a0ef92755f97
https://github.com/qemu/qemu/commit/658e501969d948735669fcf82206a0ef92755f97
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use s->memmap in create_fdt() path
create_fdt(), create_fdt_flash() and create_fdt_fw_cfg() can access the
memmap via their RISCVVirtState pointers.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 04c4f8d1ee373b9b8c413619f5600caa3e7b006c
https://github.com/qemu/qemu/commit/04c4f8d1ee373b9b8c413619f5600caa3e7b006c
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
create_fdt_sockets() and all its fdt helpers (create_fdt_socket_aplic(),
create_fdt_imsic(), create_fdt_socket_plic(), create_fdt_socket_aclint()
and create_fdt_socket_memory()) can use s->memmap from their
RISCVVirtState pointer instead of having an extra memmap argument.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a51a88fd5d2784c8f6eaaa386dbb5d621949f3e5
https://github.com/qemu/qemu/commit/a51a88fd5d2784c8f6eaaa386dbb5d621949f3e5
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
create_fdt_virtio() can use s->memmap instead of having an extra
argument for it.
While we're at it rewrite it a little bit to avoid the clunky line in
'name' and code repetition:
- declare 'virtio_base' out of the loop since it never changes;
- declare a 'size' variable. Use it to calculate the address of the
virtio device in an 'addr' variable;
- use 'addr' in the 'name' g_strdup_printf();
- use 'addr' and 'size' when creating the 'reg' property.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 621e45271f53d09789155ea89e16cdee34988654
https://github.com/qemu/qemu/commit/621e45271f53d09789155ea89e16cdee34988654
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
Change create_fdt_pcie(), create_fdt_reset(), create_fdt_uart() and
create_fdt_rtc() to use s->memmap in their logic.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e7cb99bfd1afc5cf2265a122bcfeab36eff7489a
https://github.com/qemu/qemu/commit/e7cb99bfd1afc5cf2265a122bcfeab36eff7489a
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M hw/riscv/virt.c
Log Message:
-----------
hw/riscv/virt.c: remove 'long' casts in fmt strings
We can avoid the 'long' casts by using PRIx64 and HWADDR_PRIx on the fmt
strings for uint64_t and hwaddr types.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2af4a82ab2cce3412ffc92cd4c96bd870e33bc8e
https://github.com/qemu/qemu/commit/2af4a82ab2cce3412ffc92cd4c96bd870e33bc8e
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-05-19 (Mon, 19 May 2025)
Changed paths:
M MAINTAINERS
M common-user/host/riscv/safe-syscall.inc.S
M docs/system/riscv/microchip-icicle-kit.rst
M hw/misc/mchp_pfsoc_sysreg.c
M hw/riscv/microchip_pfsoc.c
M hw/riscv/riscv_hart.c
M hw/riscv/virt-acpi-build.c
M hw/riscv/virt.c
M include/hw/riscv/microchip_pfsoc.h
M include/hw/riscv/virt.h
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/csr.c
M target/riscv/insn32.decode
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/internals.h
M target/riscv/kvm/kvm-cpu.c
M target/riscv/op_helper.c
M target/riscv/pmp.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20250519' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for 10.1
* Add support for RIMT to virt machine ACPI
* Don't allow PMP RLB to bypass rule privileges
* Fix checks on writes to pmpcfg in Smepmp MML mode
* Generate strided vector loads/stores with tcg nodes
* Improve Microchip Polarfire SoC customization
* Use tcg ops generation to emulate whole reg rvv loads/stores
* Expand the probe_pages helper function to handle probe flags
* Fix type conflict of GLib function pointers
* Fix endless translation loop on big endian systems
* Use tail pseudoinstruction for calling tail
* Fix some RISC-V vector instruction corner cases
* MAINTAINERS: Add common-user/host/riscv to RISC-V section
* Fix write_misa vs aligned next_pc
* KVM CSR fixes
* Virt machine memmap usage cleanup
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# gpg: Signature made Mon 19 May 2025 00:04:53 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
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* tag 'pull-riscv-to-apply-20250519' of https://github.com/alistair23/qemu: (56
commits)
hw/riscv/virt.c: remove 'long' casts in fmt strings
hw/riscv/virt.c: use s->memmap in finalize_fdt() functions
hw/riscv/virt.c: use s->memmap in create_fdt_virtio()
hw/riscv/virt.c: use s->memmap in create_fdt_sockets() path
hw/riscv/virt.c: use s->memmap in create_fdt() path
hw/riscv/virt.c: add 'base' arg in create_fw_cfg()
hw/riscv/virt.c: use s->memmap in virt_machine_done()
hw/riscv/virt.c: remove trivial virt_memmap references
hw/riscv/virt.c: enforce s->memmap use in machine_init()
target/riscv/kvm: add scounteren CSR
target/riscv/kvm: read/write KVM regs via env size
target/riscv/kvm: add senvcfg CSR
target/riscv/kvm: do not read unavailable CSRs
target/riscv/kvm: add kvm_csr_cfgs[]
target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
target/riscv/kvm: turn u32/u64 reg functions into macros
target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
target/riscv/kvm: minor fixes/tweaks
target/riscv: Fix write_misa vs aligned next_pc
target/riscv: Move insn_len to internals.h
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/757a34115e74...2af4a82ab2cc
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