Branch: refs/heads/staging-9.2
Home: https://github.com/qemu/qemu
Commit: dc5208769a0f29ea47d38e614f2f6612f3f15f50
https://github.com/qemu/qemu/commit/dc5208769a0f29ea47d38e614f2f6612f3f15f50
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-05-08 (Thu, 08 May 2025)
Changed paths:
M .gitlab-ci.d/check-dco.py
M .gitlab-ci.d/check-patch.py
Log Message:
-----------
gitlab: use --refetch in check-patch/check-dco jobs
When gitlab initializes the repo checkout for a CI job, it will have
done a shallow clone with only partial history. Periodically the objects
that are omitted cause trouble with the check-patch/check-dco jobs. This
is exhibited as reporting strange errors being unable to fetch certain
objects that are known to exist.
Passing the --refetch flag to 'git fetch' causes it to not assume the
local checkout has all common objects and thus re-fetch everything that
is needed. This appears to solve the check-patch/check-dco job failures.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
(cherry picked from commit d5d028eee38d4107821c0d2cfdb0dd04b9ba5ca3)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 93e5ecd78031555426a8c74aad87ac1a308ccbb8
https://github.com/qemu/qemu/commit/93e5ecd78031555426a8c74aad87ac1a308ccbb8
Author: Bernhard Beschow <[email protected]>
Date: 2025-05-11 (Sun, 11 May 2025)
Changed paths:
M hw/i2c/imx_i2c.c
Log Message:
-----------
hw/i2c/imx: Always set interrupt status bit if interrupt condition occurs
According to the i.MX 8M Plus reference manual, the status flag
I2C_I2SR[IIF] continues to be set when an interrupt condition
occurs even when I2C interrupts are disabled (I2C_I2CR[IIEN] is
clear). However, the device model only sets the flag when I2C
interrupts are enabled which causes U-Boot to loop forever. Fix
the device model by always setting the flag and let I2C_I2CR[IIEN]
guard I2C interrupts only.
Also remove the comment in the code since it merely stated the
obvious and would be outdated now.
Cc: [email protected]
Fixes: 20d0f9cf6a41 ("i.MX: Add I2C controller emulator")
Signed-off-by: Bernhard Beschow <[email protected]>
Acked-by: Corey Minyard <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
(cherry picked from commit 54e54e594bc8273d210f7ff4448c165a989cbbe8)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 649ef0c6f15a49e5af065935ebfde15262682929
https://github.com/qemu/qemu/commit/649ef0c6f15a49e5af065935ebfde15262682929
Author: Christian Schoenebeck <[email protected]>
Date: 2025-05-12 (Mon, 12 May 2025)
Changed paths:
M hw/9pfs/9p.c
M hw/9pfs/9p.h
Log Message:
-----------
9pfs: fix concurrent v9fs_reclaim_fd() calls
Even though this function is serialized to be always called from main
thread, v9fs_reclaim_fd() is dispatching the coroutine to a worker thread
in between via its v9fs_co_*() calls, hence leading to the situation where
v9fs_reclaim_fd() is effectively executed multiple times simultaniously,
which renders its LRU algorithm useless and causes high latency.
Fix this by adding a simple boolean variable to ensure this function is
only called once at a time. No synchronization needed for this boolean
variable as this function is only entered and returned on main thread.
Fixes: 7a46274529c ('hw/9pfs: Add file descriptor reclaim support')
Signed-off-by: Christian Schoenebeck <[email protected]>
Reviewed-by: Greg Kurz <[email protected]>
Message-Id:
<5c622067efd66dd4ee5eca740dcf263f41db20b2.1741339452.git.qemu_...@crudebyte.com>
(cherry picked from commit 61da38db70affd925226ce1e8a61d761c20d045b)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 3d2e7e1428abea7ed0956c99e4944e596755a207
https://github.com/qemu/qemu/commit/3d2e7e1428abea7ed0956c99e4944e596755a207
Author: Christian Schoenebeck <[email protected]>
Date: 2025-05-12 (Mon, 12 May 2025)
Changed paths:
M hw/9pfs/9p.c
Log Message:
-----------
9pfs: fix FD leak and reduce latency of v9fs_reclaim_fd()
This patch fixes two different bugs in v9fs_reclaim_fd():
1. Reduce latency:
This function calls v9fs_co_close() and v9fs_co_closedir() in a loop. Each
one of the calls adds two thread hops (between main thread and a fs driver
background thread). Each thread hop adds latency, which sums up in
function's loop to a significant duration.
Reduce overall latency by open coding what v9fs_co_close() and
v9fs_co_closedir() do, executing those and the loop itself altogether in
only one background thread block, hence reducing the total amount of
thread hops to only two.
2. Fix file descriptor leak:
The existing code called v9fs_co_close() and v9fs_co_closedir() to close
file descriptors. Both functions check right at the beginning if the 9p
request was cancelled:
if (v9fs_request_cancelled(pdu)) {
return -EINTR;
}
So if client sent a 'Tflush' message, v9fs_co_close() / v9fs_co_closedir()
returned without having closed the file descriptor and v9fs_reclaim_fd()
subsequently freed the FID without its file descriptor being closed, hence
leaking those file descriptors.
This 2nd bug is fixed by this patch as well by open coding v9fs_co_close()
and v9fs_co_closedir() inside of v9fs_reclaim_fd() and not performing the
v9fs_request_cancelled(pdu) check there.
Fixes: 7a46274529c ('hw/9pfs: Add file descriptor reclaim support')
Fixes: bccacf6c792 ('hw/9pfs: Implement TFLUSH operation')
Signed-off-by: Christian Schoenebeck <[email protected]>
Reviewed-by: Greg Kurz <[email protected]>
Message-Id:
<5747469d3f039c53147e850b456943a1d4b5485c.1741339452.git.qemu_...@crudebyte.com>
(cherry picked from commit 89f7b4da7662ecc6840ffb0846045f03f9714bc6)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 0883bdd92e6ec2ee99e6dd6da95b45e9696744fd
https://github.com/qemu/qemu/commit/0883bdd92e6ec2ee99e6dd6da95b45e9696744fd
Author: Fabiano Rosas <[email protected]>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M hw/s390x/s390-virtio-ccw.c
Log Message:
-----------
s390x: Fix leak in machine_set_loadparm
ASAN spotted a leaking string in machine_set_loadparm():
Direct leak of 9 byte(s) in 1 object(s) allocated from:
#0 0x560ffb5bb379 in malloc
../projects/compiler-rt/lib/asan/asan_malloc_linux.cpp:69:3
#1 0x7f1aca926518 in g_malloc ../glib/gmem.c:106
#2 0x7f1aca94113e in g_strdup ../glib/gstrfuncs.c:364
#3 0x560ffc8afbf9 in qobject_input_type_str
../qapi/qobject-input-visitor.c:542:12
#4 0x560ffc8a80ff in visit_type_str ../qapi/qapi-visit-core.c:349:10
#5 0x560ffbe6053a in machine_set_loadparm
../hw/s390x/s390-virtio-ccw.c:802:10
#6 0x560ffc0c5e52 in object_property_set ../qom/object.c:1450:5
#7 0x560ffc0d4175 in object_property_set_qobject ../qom/qom-qobject.c:28:10
#8 0x560ffc0c6004 in object_property_set_str ../qom/object.c:1458:15
#9 0x560ffbe2ae60 in update_machine_ipl_properties ../hw/s390x/ipl.c:569:9
#10 0x560ffbe2aa65 in s390_ipl_update_diag308 ../hw/s390x/ipl.c:594:5
#11 0x560ffbdee132 in handle_diag_308 ../target/s390x/diag.c:147:9
#12 0x560ffbebb956 in helper_diag ../target/s390x/tcg/misc_helper.c:137:9
#13 0x7f1a3c51c730 (/memfd:tcg-jit (deleted)+0x39730)
Cc: [email protected]
Signed-off-by: Fabiano Rosas <[email protected]>
Message-ID: <[email protected]>
Fixes: 1fd396e3228 ("s390x: Register TYPE_S390_CCW_MACHINE properties as class
properties")
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
(cherry picked from commit bdf12f2a56bf3f13c52eb51f0a994bbfe40706b2)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 0b8c7cdeff6523dfb30aabd0c112ea3211a96159
https://github.com/qemu/qemu/commit/0b8c7cdeff6523dfb30aabd0c112ea3211a96159
Author: Akihiko Odaki <[email protected]>
Date: 2025-05-16 (Fri, 16 May 2025)
Changed paths:
M hw/virtio/virtio.c
Log Message:
-----------
virtio: Call set_features during reset
virtio-net expects set_features() will be called when the feature set
used by the guest changes to update the number of virtqueues but it is
not called during reset, which will clear all features, leaving the
queues added for VIRTIO_NET_F_MQ or VIRTIO_NET_F_RSS. Not only these
extra queues are visible to the guest, they will cause segmentation
fault during migration.
Call set_features() during reset to remove those queues for virtio-net
as we call set_status(). It will also prevent similar bugs for
virtio-net and other devices in the future.
Fixes: f9d6dbf0bf6e ("virtio-net: remove virtio queues if the guest doesn't
support multiqueue")
Buglink: https://issues.redhat.com/browse/RHEL-73842
Cc: [email protected]
Signed-off-by: Akihiko Odaki <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Michael S. Tsirkin <[email protected]>
Signed-off-by: Michael S. Tsirkin <[email protected]>
(cherry picked from commit 0caed25cd171c611781589b5402161d27d57229c)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: d6258d62cf445db3cdbdee8ca63d798afc4e6c82
https://github.com/qemu/qemu/commit/d6258d62cf445db3cdbdee8ca63d798afc4e6c82
Author: Loïc Lefort <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: pmp: move Smepmp operation conversion into a function
Signed-off-by: Loïc Lefort <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: LIU Zhiwei <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 915b203745540e908943758f78f5da49e0a15e45)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 82c0f4946a2b88dcbe976e673e826bab7d94f6a3
https://github.com/qemu/qemu/commit/82c0f4946a2b88dcbe976e673e826bab7d94f6a3
Author: Ziqiao Kong <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu_helper.c
Log Message:
-----------
target/riscv: fix endless translation loop on big endian systems
On big endian systems, pte and updated_pte hold big endian host data
while pte_pa points to little endian target data. This means the branch
at cpu_helper.c:1669 will be always satisfied and restart translation,
causing an endless translation loop.
The correctness of this patch can be deduced by:
old_pte will hold value either from cpu_to_le32/64(pte) or
cpu_to_le32/64(updated_pte), both of wich is litte endian. After that,
an in-place conversion by le32/64_to_cpu(old_pte) ensures that old_pte
now is in native endian, same with pte. Therefore, the endianness of the
both side of if (old_pte != pte) is correct.
Signed-off-by: Ziqiao Kong <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit ad63158bdb33dab5704ea1cf740d2ea0387175df)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: fb1f88ee29fedf649d4422db241d03986d1f1df8
https://github.com/qemu/qemu/commit/fb1f88ee29fedf649d4422db241d03986d1f1df8
Author: Icenowy Zheng <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M common-user/host/riscv/safe-syscall.inc.S
Log Message:
-----------
common-user/host/riscv: use tail pseudoinstruction for calling tail
The j pseudoinstruction maps to a JAL instruction, which can only handle
a jump to somewhere with a signed 20-bit destination. In case of static
linking and LTO'ing this easily leads to "relocation truncated to fit"
error.
Switch to use tail pseudoinstruction, which is the standard way to
tail-call a function in medium code model (emits AUIPC+JALR).
Signed-off-by: Icenowy Zheng <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 22b448ccc6611a59d4aa54419f4d88c1f343cb35)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 10bfc8d45e8a48fea3802fc0849c5080a444029d
https://github.com/qemu/qemu/commit/10bfc8d45e8a48fea3802fc0849c5080a444029d
Author: Anton Blanchard <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Source vector registers cannot overlap mask register
Add the relevant ISA paragraphs explaining why source (and destination)
registers cannot overlap the mask register.
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 3e8d1e4a628bb234c0b5d1ccd510900047181dbd)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 6c4ddafa0daedf88aca19a8bd872519b7bc2da19
https://github.com/qemu/qemu/commit/6c4ddafa0daedf88aca19a8bd872519b7bc2da19
Author: Anton Blanchard <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Add CHECK arg to GEN_OPFVF_WIDEN_TRANS
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Max Chou <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit b0450a101d6c88789d0e8df2bcbef61bc7cd159a)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 28ee50bbe9c73f531b52485b017d040c03819cd4
https://github.com/qemu/qemu/commit/28ee50bbe9c73f531b52485b017d040c03819cd4
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vrgather instructions to
check mismatched input EEWs encoding constraint
According to the v spec, a vector register cannot be used to provide source
operands with more than one EEW for a single instruction.
The vs1 EEW of vrgatherei16.vv is 16.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 629c2a8dd7506e1cb9b6b7127604641632ac453f)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: fd0fc3eb48650a8c7ce49e252b529aaa5c11093c
https://github.com/qemu/qemu/commit/fd0fc3eb48650a8c7ce49e252b529aaa5c11093c
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to
OPIVI/OPIVX/OPFVF(vext_check_ss) instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit fbeaf35838768086b435833cb4dc5182c73ec2bc)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 80eebc00f93c2cf2a35da4a86fb5d998ce162ab6
https://github.com/qemu/qemu/commit/80eebc00f93c2cf2a35da4a86fb5d998ce162ab6
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss)
instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit fda68acb7761af40df78db18e44ca1ff20195fe0)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: d5166dad5519a5df508531fa11ca95a7b80ac529
https://github.com/qemu/qemu/commit/d5166dad5519a5df508531fa11ca95a7b80ac529
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector slide
instructions(OPIVI/OPIVX)
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit b5480a693e3e657108746721ffe434b3bb6e7a72)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 32f8a2b4292d78409da7845ae095a173102b02b7
https://github.com/qemu/qemu/commit/32f8a2b4292d78409da7845ae095a173102b02b7
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector integer extension
instructions(OPMVV)
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 411eefd56a3921ddbfdbadca596e1a8593ce834c)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: dec1f0b924f80d83453003f671fa83a6d8f65519
https://github.com/qemu/qemu/commit/dec1f0b924f80d83453003f671fa83a6d8f65519
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvbf16.c.inc
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen
instructions
Handle the overlap of source registers with different EEWs.
The vd of vector widening mul-add instructions is one of the input
operands.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 1f090a229f85e662394267680408bd31fd0a99c9)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 84dd432553c48aecaf3d2020eb7bfd3496ab5cb6
https://github.com/qemu/qemu/commit/84dd432553c48aecaf3d2020eb7bfd3496ab5cb6
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store
instructions
Handle the overlap of source registers with different EEWs.
Co-authored-by: Anton Blanchard <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit db21c3eb05504c4cedaad4f7b19e588361b02385)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 41c984df66ac85c81893add1ba497f2092503c39
https://github.com/qemu/qemu/commit/41c984df66ac85c81893add1ba497f2092503c39
Author: Max Chou <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/insn32.decode
Log Message:
-----------
target/riscv: Fix the rvv reserved encoding of unmasked instructions
According to the v spec, the encodings of vcomoress.vm and vector
mask-register logical instructions with vm=0 are reserved.
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Signed-off-by: Max Chou <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 8539a1244bf240d28917effb88a140eb58e45e88)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: ac053657f040ef2f55f25cc3b75c1411f7fd161c
https://github.com/qemu/qemu/commit/ac053657f040ef2f55f25cc3b75c1411f7fd161c
Author: Anton Blanchard <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Fix vslidedown with rvv_ta_all_1s
vslidedown always zeroes elements past vl, where it should use the
tail policy.
Signed-off-by: Anton Blanchard <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 2669b696e243b64f8ea1a6468dcee255de99f08d)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 0f23cdfd9966bc40907fdd8f0abfcbda4558c35d
https://github.com/qemu/qemu/commit/0f23cdfd9966bc40907fdd8f0abfcbda4558c35d
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: minor fixes/tweaks
Remove an unused 'KVMScratchCPU' pointer argument in
kvm_riscv_check_sbi_dbcn_support().
Put kvm_riscv_reset_regs_csr() after kvm_riscv_put_regs_csr(). This will
make a future patch diff easier to read, when changes in
kvm_riscv_reset_regs_csr() and kvm_riscv_get_regs_csr() will be made.
Fixes: a6b53378f5 ("target/riscv/kvm: implement SBI debug console (DBCN) calls")
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 73f81da0a3628180409a0ae90ece19534bcdf09b)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 2c28f83e6f217bca603f9a7b06cabd4f987ce1af
https://github.com/qemu/qemu/commit/2c28f83e6f217bca603f9a7b06cabd4f987ce1af
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg()
'reglist' is being g-malloc'ed but never freed.
Reported-by: Andrew Jones <[email protected]>
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 906af6de9462c5192547cca0beac2c134659a437)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 622aa7f3bf92d4802ce550303f76436786ae8958
https://github.com/qemu/qemu/commit/622aa7f3bf92d4802ce550303f76436786ae8958
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: turn u32/u64 reg functions into macros
This change is motivated by a future change w.r.t CSRs management. We
want to handle them the same way as KVM extensions, i.e. a static array
with KVMCPUConfig objs that will be read/write during init and so on.
But to do that properly we must be able to declare a static array that
hold KVM regs.
C does not allow to init static arrays and use functions as
initializers, e.g. we can't do:
.kvm_reg_id = kvm_riscv_reg_id_ulong(...)
When instantiating the array. We can do that with macros though, so our
goal is turn kvm_riscv_reg_ulong() in a macro. It is cleaner to turn
every other reg_id_*() function in macros, and ulong will end up using
the macros for u32 and u64, so we'll start with them.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit b6096103494506514d9bfa442f62fef36ffc8fba)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: ca9148aa522ab6c14b325cb7ef467194dee32e06
https://github.com/qemu/qemu/commit/ca9148aa522ab6c14b325cb7ef467194dee32e06
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro
We need the reg_id_ulong() helper to be a macro to be able to create a
static array of KVMCPUConfig that will hold CSR information.
Despite the amount of changes all of them are tedious/trivial:
- replace instances of "kvm_riscv_reg_id_ulong" with
"KVM_RISCV_REG_ID_ULONG";
- RISCV_CORE_REG(), RISCV_CSR_REG(), RISCV_CONFIG_REG() and
RISCV_VECTOR_CSR_REG() only receives one 'name' arg. Remove unneeded
'env' variables when applicable.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit 11766e17616a5a4181d4a63f88adf67ac52c553b)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: da2c47c196644485815c5e5a5a428c4fdf98ee48
https://github.com/qemu/qemu/commit/da2c47c196644485815c5e5a5a428c4fdf98ee48
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-05-20 (Tue, 20 May 2025)
Changed paths:
M target/riscv/cpu.h
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: add kvm_csr_cfgs[]
At this moment we're not checking if the host has support for any
specific CSR before doing get/put regs. This will cause problems if the
host KVM doesn't support it (see [1] as an example).
We'll use the same approach done with the CPU extensions: read all known
KVM CSRs during init() to check for availability, then read/write them
if they are present. This will be made by either using get-reglist or by
directly reading the CSRs.
For now we'll just convert the CSRs to use a kvm_csr_cfg[] array,
reusing the same KVMCPUConfig abstraction we use for extensions, and use
the array in (get|put)_csr_regs() instead of manually listing them. A
lot of boilerplate will be added but at least we'll automate the get/put
procedure for CSRs, i.e. adding a new CSR in the future will be a matter
of adding it in kvm_csr_regs[] and everything else will be taken care
of.
Despite all the code changes no behavioral change is made.
[1]
https://lore.kernel.org/qemu-riscv/CABJz62OfUDHYkQ0T3rGHStQprf1c7_E0qBLbLKhfv=+jb0s...@mail.gmail.com/
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Andrew Jones <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Cc: [email protected]
(cherry picked from commit d3b6f1742c36e3a3c1e74cb60646ee98a4e39ea3)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 8f9d3fe9c86049abd4cadd14afb348c8e03aa80e
https://github.com/qemu/qemu/commit/8f9d3fe9c86049abd4cadd14afb348c8e03aa80e
Author: Rakesh Jeyasingh <[email protected]>
Date: 2025-05-22 (Thu, 22 May 2025)
Changed paths:
M hw/pci-host/gt64120.c
Log Message:
-----------
hw/pci-host/gt64120: Fix endianness handling
The GT-64120 PCI controller requires special handling where:
1. Host bridge(bus 0 ,device 0) must never be byte-swapped
2. Other devices follow MByteSwap bit in GT_PCI0_CMD
The previous implementation incorrectly swapped all accesses, breaking
host bridge detection (lspci -d 11ab:4620).
Changes made:
1. Removed gt64120_update_pci_cfgdata_mapping() and moved data_mem
initialization
to gt64120_realize() for cleaner setup
2. Implemented custom read/write handlers that:
- Preserve host bridge accesses (extract32(config_reg,11,13)==0)
- apply swapping only for non-bridge devices in big-endian mode
Fixes: 145e2198 ("hw/mips/gt64xxx_pci: Endian-swap using PCI_HOST_BRIDGE
MemoryRegionOps")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2826
Signed-off-by: Rakesh Jeyasingh <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
(cherry picked from commit e5894fd6f411c113e2b5f62811e96eeb5b084381)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 0fbad0922b4aa075b2b8c63d7fbfde9211692338
https://github.com/qemu/qemu/commit/0fbad0922b4aa075b2b8c63d7fbfde9211692338
Author: Rakesh Jeyasingh <[email protected]>
Date: 2025-05-22 (Thu, 22 May 2025)
Changed paths:
M hw/pci/pci_host.c
M include/hw/pci-host/dino.h
M include/hw/pci/pci_host.h
Log Message:
-----------
hw/pci-host: Remove unused pci_host_data_be_ops
pci_host_data_be_ops became unused after endianness fixes
Suggested-by: Paolo Bonzini <[email protected]>
Signed-off-by: Rakesh Jeyasingh <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
(cherry picked from commit 560375cff3ccedabf1fe5ca1bc7a31b13fdc68e5)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 7f600c42b5bbfb8895291844972fdb540d46355a
https://github.com/qemu/qemu/commit/7f600c42b5bbfb8895291844972fdb540d46355a
Author: Zhao Liu <[email protected]>
Date: 2025-05-22 (Thu, 22 May 2025)
Changed paths:
M qapi/misc-target.json
Log Message:
-----------
qapi/misc-target: Fix the doc to distinguish query-sgx and
query-sgx-capabilities
There're 2 QMP commands: query-sgx and query-sgx-capabilities, but
their outputs are very similar and the documentation lacks clear
differentiation.
>From the codes, query-sgx is used to gather guest's SGX capabilities
(including SGX related CPUIDs and EPC sections' size, in SGXInfo), and
if guest doesn't have SGX, then QEMU will report the error message.
On the other hand, query-sgx-capabilities is used to gather host's SGX
capabilities (descripted by SGXInfo as well). And if host doesn't
support SGX, then QEMU will also report the error message.
Considering that SGXInfo is already documented and both these 2 commands
have enough error messages (for the exception case in their codes).
Therefore the QAPI documentation for these two commands only needs to
emphasize that one of them applies to the guest and the other to the
host.
Fix their documentation to reflect this difference.
Reported-by: Markus Armbruster <[email protected]>
Suggested-by: Paolo Bonzini <[email protected]>
Signed-off-by: Zhao Liu <[email protected]>
Acked-by: Markus Armbruster <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
(cherry picked from commit 7f2131c35c1781ca41c62dc26fd93282e1351323)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 9b9907695da99a0ee1dbb5ae93f868ea596a9478
https://github.com/qemu/qemu/commit/9b9907695da99a0ee1dbb5ae93f868ea596a9478
Author: Peter Xu <[email protected]>
Date: 2025-05-22 (Thu, 22 May 2025)
Changed paths:
M migration/options.c
Log Message:
-----------
migration: Allow caps to be set when preempt or multifd cap enabled
With commit 82137e6c8c ("migration: enforce multifd and postcopy preempt to
be set before incoming"), and if postcopy preempt / multifd is enabled, one
cannot setup any capability because these checks would always fail.
(qemu) migrate_set_capability xbzrle off
Error: Postcopy preempt must be set before incoming starts
To fix it, check existing cap and only raise an error if the specific cap
changed.
Fixes: 82137e6c8c ("migration: enforce multifd and postcopy preempt to be set
before incoming")
Reviewed-by: Dr. David Alan Gilbert <[email protected]>
Reviewed-by: Juraj Marcin <[email protected]>
Signed-off-by: Peter Xu <[email protected]>
(cherry picked from commit 17bec9235bb0775cf8dec4103c167757ee8898f3)
Signed-off-by: Michael Tokarev <[email protected]>
Compare: https://github.com/qemu/qemu/compare/5dd4660f5f4d...9b9907695da9
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