Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: f5ec751ee70d7960a97c6c675f69e924d82dc60d
https://github.com/qemu/qemu/commit/f5ec751ee70d7960a97c6c675f69e924d82dc60d
Author: Shameer Kolothum <[email protected]>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
default_bus_bypass_iommu tells us whether the bypass_iommu is set
for the default PCIe root bus. Make sure we check that before adding
the "iommu-map" DT property.
Cc: [email protected]
Fixes: 6d7a85483a06 ("hw/arm/virt: Add default_bus_bypass_iommu machine option")
Suggested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Donald Dutile <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 16a9b55021519fb1d4a4585952e03eafd4ed1947
https://github.com/qemu/qemu/commit/16a9b55021519fb1d4a4585952e03eafd4ed1947
Author: Thomas Huth <[email protected]>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M MAINTAINERS
M tests/functional/meson.build
A tests/functional/test_arm_realview.py
Log Message:
-----------
tests/functional: Add a test for the realview-eb-mpcore machine
Check that we can boot a Linux kernel here and that we can at
least send one ping network packet.
Signed-off-by: Thomas Huth <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e372214e663a4370fe064f7867f402eade37357e
https://github.com/qemu/qemu/commit/e372214e663a4370fe064f7867f402eade37357e
Author: Ethan Chen <[email protected]>
Date: 2025-06-13 (Fri, 13 Jun 2025)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Fix reversed description of icount sleep behavior
The documentation for the -icount option incorrectly describes the behavior
of the sleep suboption. Based on the actual implementation and system
behavior, the effects of sleep=on and sleep=off were inadvertently reversed.
This commit updates the description to reflect their intended functionality.
Cc: [email protected]
Fixes: fa647905e6ba ("qemu-options.hx: Fix minor issues in icount
documentation")
Signed-off-by: Ethan Chen <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: bedcc7465db867841a4c76e5a3aab8a7d51f22aa
https://github.com/qemu/qemu/commit/bedcc7465db867841a4c76e5a3aab8a7d51f22aa
Author: Akihiko Odaki <[email protected]>
Date: 2025-06-13 (Fri, 13 Jun 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Define raw write for PMU CLR registers
Raw writes to PMCNTENCLR and PMCNTENCLR_EL0 incorrectly used their
default write function, which clears written bits instead of writes the
raw value.
PMINTENCLR and PMINTENCLR_EL1 are similar registers, but they instead
had ARM_CP_NO_RAW. Commit 7a0e58fa6487 ("target-arm: Split NO_MIGRATE
into ALIAS and NO_RAW") sugguests ARM_CP_ALIAS should be used instead of
ARM_CP_NO_RAW in such a case:
> We currently mark ARM coprocessor/system register definitions with
> the flag ARM_CP_NO_MIGRATE for two different reasons:
> 1) register is an alias on to state that's also visible via
> some other register, and that other register is the one
> responsible for migrating the state
> 2) register is not actually state at all (for instance the TLB
> or cache maintenance operation "registers") and it makes no
> sense to attempt to migrate it or otherwise access the raw state
>
> This works fine for identifying which registers should be ignored
> when performing migration, but we also use the same functions for
> synchronizing system register state between QEMU and the kernel
> when using KVM. In this case we don't want to try to sync state
> into registers in category 2, but we do want to sync into registers
> in category 1, because the kernel might have picked a different
> one of the aliases as its choice for which one to expose for
> migration.
These registers fall in category 1 (ARM_CP_ALIAS), not category 2
(ARM_CP_NO_RAW).
ARM_CP_NO_RAW also has another undesired side effect that hides
registers from GDB.
Properly set raw write functions and drop the ARM_CP_NO_RAW flag from
PMINTENCLR and PMINTENCLR_EL1; this fixes GDB/KVM state synchronization
of PMCNTENCLR and PMCNTENCLR_EL0, and exposes all these four registers
to GDB.
It is not necessary to add ARM_CP_ALIAS to these registers because the
flag is already set.
Signed-off-by: Akihiko Odaki <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 73cdd846adb80060fbdb2f2557aeafb41cb39064
https://github.com/qemu/qemu/commit/73cdd846adb80060fbdb2f2557aeafb41cb39064
Author: Souleymane Conte <[email protected]>
Date: 2025-06-13 (Fri, 13 Jun 2025)
Changed paths:
M MAINTAINERS
M docs/interop/index.rst
A docs/interop/qed_spec.rst
R docs/interop/qed_spec.txt
Log Message:
-----------
docs/interop: convert qed_spec.txt to reStructuredText format
Convert the qed_spec.txt file to reStructuredText and
include it in the manual.
buglink: https://gitlab.com/qemu-project/qemu/-/issues/527
Signed-off-by: Souleymane Conte <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: adjusted position of doc in the table of contents;
bulked up commit message; added file to MAINTAINERS section
for QED; made 'Consistency checking' a higher level section;
fixed one preexisting grammar nit (s/by from/from/)]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5dc8e4e892ba10e040d12afece0d36b8b6a269d6
https://github.com/qemu/qemu/commit/5dc8e4e892ba10e040d12afece0d36b8b6a269d6
Author: Clément Chigot <[email protected]>
Date: 2025-06-13 (Fri, 13 Jun 2025)
Changed paths:
M hw/arm/boot.c
M include/hw/arm/boot.h
Log Message:
-----------
hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
Currently, arm booting processus assumes that the first_cpu is the CPU
that will boot: `arm_load_kernel` is powering off all but the `first_cpu`;
`do_cpu_reset` is setting the loader address only for this `first_cpu`.
For most of the boards, this isn't an issue as the kernel is loaded and
booted on the first CPU anyway. However, for zynqmp, the option
"boot-cpu" allows to choose any CPUs.
Create a new arm_boot_info entry `primary_cpu` recording which CPU will
be boot first. This one is set when `arm_boot_kernel` is called.
Signed-off-by: Clément Chigot <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6559e7ad8e535b70e34c79076e6cb6c09d626d0d
https://github.com/qemu/qemu/commit/6559e7ad8e535b70e34c79076e6cb6c09d626d0d
Author: Frederic Konrad <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M include/hw/intc/arm_gic.h
M include/hw/intc/arm_gic_common.h
Log Message:
-----------
hw/intc/arm_gic: introduce a first-cpu-index property
This introduces a first-cpu-index property to the arm-gic, as some SOCs
could have two separate GIC (ie: the zynqmp).
Signed-off-by: Clément Chigot <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
[PMM: slightly expanded comment documenting GIC property]
Signed-off-by: Peter Maydell <[email protected]>
Commit: cd38e638c43e4d5d3fd65dd4529c2e6153c9c408
https://github.com/qemu/qemu/commit/cd38e638c43e4d5d3fd65dd4529c2e6153c9c408
Author: Peter Maydell <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
The AN500 application note documents that it configures the Cortex-M7
CPU to have 16 MPU regions. We weren't doing this in our emulation,
so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions
property to 16 for this board.
This bug doesn't affect any of the other board types we model in
this source file, because they all use either the Cortex-M3 or
Cortex-M4. Those CPUs do not have an RTL configurable number of
MPU regions, and always provide 8 regions if the MPU is built in.
Cc: [email protected]
Reported-by: Corentin GENDRE <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
Commit: 5ad2b1f443a96444cf3e7a2fbe17aae696201012
https://github.com/qemu/qemu/commit/5ad2b1f443a96444cf3e7a2fbe17aae696201012
Author: J. Neuschäfer <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M linux-user/arm/cpu_loop.c
Log Message:
-----------
linux-user/arm: Fix return value of SYS_cacheflush
Although the emulated cacheflush syscall does nothing, it still needs to
return zero to indicate success.
Cc: [email protected]
Signed-off-by: J. Neuschäfer <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0bc0e92be50058bc3b881b0d5051206b015a3fa7
https://github.com/qemu/qemu/commit/0bc0e92be50058bc3b881b0d5051206b015a3fa7
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M MAINTAINERS
M docs/interop/index.rst
A docs/interop/qed_spec.rst
R docs/interop/qed_spec.txt
M hw/arm/boot.c
M hw/arm/mps2.c
M hw/arm/virt.c
M hw/intc/arm_gic.c
M hw/intc/arm_gic_common.c
M include/hw/arm/boot.h
M include/hw/intc/arm_gic.h
M include/hw/intc/arm_gic_common.h
M linux-user/arm/cpu_loop.c
M qemu-options.hx
M target/arm/helper.c
M tests/functional/meson.build
A tests/functional/test_arm_realview.py
Log Message:
-----------
Merge tag 'pull-target-arm-20250616' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging
target-arm queue:
* hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
* tests/functional: Add a test for the realview-eb-mpcore machine
* qemu-options.hx: Fix reversed description of icount sleep behavior
* target/arm: Define raw write for PMU CLR registers
* docs/interop: convert qed_spec.txt to reStructuredText format
* hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
* hw/intc/arm_gic: introduce a first-cpu-index property
* hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
* linux-user/arm: Fix return value of SYS_cacheflush
# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmhQJLgZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3k+8EACPyIt6Tie/0kuTXG85r06P
# Iqlp59ENb4HNB43bOBlLqNNJydx1GplKnDeDVsz4MyjhtFTZ3xvY+52IbDOgb3YL
# 66uJfu1VgdnYoKOpfi3hEr9PM9QxNkENF/3+Fokn+X5tHzhNY4eo/RREQfz2tKJ5
# aKKvzmcZNYwqFLn8TKCNaAfjmqrdwVpuF+rt//4hGULZGwatt8qmlsXWLstozTAz
# SPx0utJfvblHj6a+49e0lXaL+xU5yho2J01OiNHrIGtED5Oq2Wmj/q0SV3qPiLDH
# hchuDXT71shE2JYoVeINaQpjRWzQNSPXvnEl9SyJ3Ghzop3sOZqE2iPVslvO0l5R
# rfrbR2rLnGcRPOwgntGnSMHiW+DH9ldhMUp7UvhlU3/5MJmWX2jpDfZJPsmmdyFH
# Evrf64yMO7JlLMQSMkTISZampz8aUgdlgrmQDJ4kGpdkp3GWqLE93eQGHCU16k2j
# PzjGxCIeOED4HEeGG3GrPTf0P1dy8WKla2z8ou2ANLqofrKpwFHTuGRl77ETn/bD
# 8c11hdS+uJ4Sx/efVPXWQhjCPNwLJL+DlCW0kKbGfTmiBdlcPPzPbrzmPNinVzJs
# luSGFzNit7Invfn0KZhy3l0iucMWGPdMDqN0B15RA5fFssdkuxZga5H2kOqCswOe
# 3hHo1s5PUbg+x1JAvQvi5g==
# =9lWk
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 16 Jun 2025 10:05:44 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250616' of
https://git.linaro.org/people/pmaydell/qemu-arm:
linux-user/arm: Fix return value of SYS_cacheflush
hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
hw/intc/arm_gic: introduce a first-cpu-index property
hw/arm: make cpu targeted by arm_load_kernel the primary CPU.
docs/interop: convert qed_spec.txt to reStructuredText format
target/arm: Define raw write for PMU CLR registers
qemu-options.hx: Fix reversed description of icount sleep behavior
tests/functional: Add a test for the realview-eb-mpcore machine
hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 9761ad5f65d23f080b5a3479e52196fbce2e1506
https://github.com/qemu/qemu/commit/9761ad5f65d23f080b5a3479e52196fbce2e1506
Author: oltolm <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M contrib/plugins/meson.build
M plugins/meson.build
M scripts/tracetool/__init__.py
M scripts/tracetool/backend/ftrace.py
M scripts/tracetool/backend/log.py
M scripts/tracetool/backend/syslog.py
M tests/functional/meson.build
M tests/include/meson.build
M tests/tcg/plugins/meson.build
M trace/meson.build
Log Message:
-----------
meson: fix Windows build
The build fails on Windows. Replace calls to Unix programs like ´cat´,
´sed´ and ´true´ with calls to ´python´ and wrap calls to
´os.path.relpath´ in try-except because it can fail when the two paths
are on different drives. Make sure to convert the Windows paths to Unix
paths to prevent warnings in generated files.
Signed-off-by: oltolm <[email protected]>
Message-id: [email protected]
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: 6e1571533fd92bec67e5ab9b1dd1e15032925757
https://github.com/qemu/qemu/commit/6e1571533fd92bec67e5ab9b1dd1e15032925757
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-06-16 (Mon, 16 Jun 2025)
Changed paths:
M contrib/plugins/meson.build
M plugins/meson.build
M scripts/tracetool/__init__.py
M scripts/tracetool/backend/ftrace.py
M scripts/tracetool/backend/log.py
M scripts/tracetool/backend/syslog.py
M tests/functional/meson.build
M tests/include/meson.build
M tests/tcg/plugins/meson.build
M trace/meson.build
Log Message:
-----------
Merge tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu into
staging
Pull request
Oleg's v4 Windows build fix.
# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEhpWov9P5fNqsNXdanKSrs4Grc8gFAmhQUoMACgkQnKSrs4Gr
# c8hqAwf9G6aXBWUcF5U1ZGHmoSr4dzR3FrJLR8f693PcqQSzA9qD1JJniQiPMUXN
# LpwbhvzZ5gHdheYTWuwdRbuVaynn8agQO5nTXtZqFX2MY7ym7waDbIOv0F3vD3u/
# Y7otRfT6DJMopkxlzf/UZ3qDVkoJlZEWVbhxuVYTBQukO8rAJt6cQNpNvfp68KYP
# XB6S4vvrzr931eG9ccyaRLRqm16PD9qhdrslvbJTqfMXR4YJxBiheQjrgatOqN/U
# brG01ObXt3o7nsLt0bTttQnGacXryXCr5B86FGhbWy2XCbpb27gwkj7WvcTtD8UN
# M10mm7zDraCBSUYsPApu/y80R/BazA==
# =y2IV
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 16 Jun 2025 13:21:07 EDT
# gpg: using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <[email protected]>" [ultimate]
# gpg: aka "Stefan Hajnoczi <[email protected]>" [ultimate]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* tag 'tracing-pull-request' of https://gitlab.com/stefanha/qemu:
meson: fix Windows build
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/a6f022775951...6e1571533fd9
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