Branch: refs/heads/staging-10.0
Home: https://github.com/qemu/qemu
Commit: 6276ce6d702bd9a7390942bbc29acaaf03b53c4e
https://github.com/qemu/qemu/commit/6276ce6d702bd9a7390942bbc29acaaf03b53c4e
Author: Bibo Mao <[email protected]>
Date: 2025-06-12 (Thu, 12 Jun 2025)
Changed paths:
M hw/loongarch/virt-acpi-build.c
Log Message:
-----------
hw/loongarch/virt: Fix big endian support with MCFG table
With API build_mcfg(), it is not necessary with parameter structure
AcpiMcfgInfo to convert to little endian since it is directly used
with host native endian.
Here remove endian conversion before calling function build_mcfg().
With this patch, bios-tables-test passes to run on big endian host
machine S390.
Fixes: 735143f10d3e ("hw/loongarch: Add acpi ged support")
Cc: [email protected]
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
(cherry picked from commit 9c55c03c05c1899521ff0c991b9296633d759890)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: c902fc66c9508c6fa2ec17510f5ae9241c0859fb
https://github.com/qemu/qemu/commit/c902fc66c9508c6fa2ec17510f5ae9241c0859fb
Author: Shameer Kolothum <[email protected]>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M hw/arm/virt.c
Log Message:
-----------
hw/arm/virt: Check bypass iommu is not set for iommu-map DT property
default_bus_bypass_iommu tells us whether the bypass_iommu is set
for the default PCIe root bus. Make sure we check that before adding
the "iommu-map" DT property.
Cc: [email protected]
Fixes: 6d7a85483a06 ("hw/arm/virt: Add default_bus_bypass_iommu machine option")
Suggested-by: Eric Auger <[email protected]>
Signed-off-by: Shameer Kolothum <[email protected]>
Reviewed-by: Donald Dutile <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit f5ec751ee70d7960a97c6c675f69e924d82dc60d)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 436b3dd8cc8e8fe67d52716c51781fb0149dd0b2
https://github.com/qemu/qemu/commit/436b3dd8cc8e8fe67d52716c51781fb0149dd0b2
Author: Ethan Chen <[email protected]>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M qemu-options.hx
Log Message:
-----------
qemu-options.hx: Fix reversed description of icount sleep behavior
The documentation for the -icount option incorrectly describes the behavior
of the sleep suboption. Based on the actual implementation and system
behavior, the effects of sleep=on and sleep=off were inadvertently reversed.
This commit updates the description to reflect their intended functionality.
Cc: [email protected]
Fixes: fa647905e6ba ("qemu-options.hx: Fix minor issues in icount
documentation")
Signed-off-by: Ethan Chen <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit e372214e663a4370fe064f7867f402eade37357e)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: b7da1f5f5ddd196c7e992b6b7b746c5b54ae1d5a
https://github.com/qemu/qemu/commit/b7da1f5f5ddd196c7e992b6b7b746c5b54ae1d5a
Author: Peter Maydell <[email protected]>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M hw/arm/mps2.c
Log Message:
-----------
hw/arm/mps2: Configure the AN500 CPU with 16 MPU regions
The AN500 application note documents that it configures the Cortex-M7
CPU to have 16 MPU regions. We weren't doing this in our emulation,
so the CPU had only the default 8 MPU regions. Set the mpu-ns-regions
property to 16 for this board.
This bug doesn't affect any of the other board types we model in
this source file, because they all use either the Cortex-M3 or
Cortex-M4. Those CPUs do not have an RTL configurable number of
MPU regions, and always provide 8 regions if the MPU is built in.
Cc: [email protected]
Reported-by: Corentin GENDRE <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Message-id: [email protected]
(cherry picked from commit cd38e638c43e4d5d3fd65dd4529c2e6153c9c408)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 3cf25f4c71086ec96df7e3b0db7f093a684e6fda
https://github.com/qemu/qemu/commit/3cf25f4c71086ec96df7e3b0db7f093a684e6fda
Author: J. Neuschäfer <[email protected]>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M linux-user/arm/cpu_loop.c
Log Message:
-----------
linux-user/arm: Fix return value of SYS_cacheflush
Although the emulated cacheflush syscall does nothing, it still needs to
return zero to indicate success.
Cc: [email protected]
Signed-off-by: J. Neuschäfer <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit 5ad2b1f443a96444cf3e7a2fbe17aae696201012)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: fdd20285ae19cf26c0d8d561684fb8126fa48f22
https://github.com/qemu/qemu/commit/fdd20285ae19cf26c0d8d561684fb8126fa48f22
Author: Song Gao <[email protected]>
Date: 2025-06-17 (Tue, 17 Jun 2025)
Changed paths:
M target/loongarch/tcg/insn_trans/trans_fcmp.c.inc
M target/loongarch/tcg/insn_trans/trans_vec.c.inc
Log Message:
-----------
target/loongarch: add check for fcond
fcond only has 22 types, add a check for fcond.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2972
Signed-off-by: Song Gao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
(cherry picked from commit e7788da9860c97920c19fa1150806186513ef256)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 46cdfdfe9202c4e58aed99bfbf7e20f514c671cd
https://github.com/qemu/qemu/commit/46cdfdfe9202c4e58aed99bfbf7e20f514c671cd
Author: Song Gao <[email protected]>
Date: 2025-06-24 (Tue, 24 Jun 2025)
Changed paths:
M target/loongarch/tcg/insn_trans/trans_vec.c.inc
Log Message:
-----------
target/loongarch: fix vldi/xvldi raise wrong error
on qemu we got an aborted error
**
ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value:
code should not be reached
Bail out!
ERROR:../target/loongarch/tcg/insn_trans/trans_vec.c.inc:3574:vldi_get_value:
code should not be reached
Aborted (core dumped)
but on 3A600/3A5000 we got a "Illegal instruction" error.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2971
Fixes: 29bb5d727ff ("target/loongarch: Implement vldi")
Cc: [email protected]
Reviewed-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Song Gao <[email protected]>
(cherry picked from commit c2a2e1ad2a749caa864281b1d4dc3f16c3f344f6)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 22909a1397ad9679f0ffaba3016a3420ace2da21
https://github.com/qemu/qemu/commit/22909a1397ad9679f0ffaba3016a3420ace2da21
Author: Richard Henderson <[email protected]>
Date: 2025-07-01 (Tue, 01 Jul 2025)
Changed paths:
M tcg/tcg.c
Log Message:
-----------
tcg: Fix constant propagation in tcg_reg_alloc_dup
The scalar constant must be replicated for dup.
Cc: [email protected]
Fixes: bab1671f0fa ("tcg: Manually expand INDEX_op_dup_vec")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3002
Signed-off-by: Richard Henderson <[email protected]>
(cherry picked from commit 0d0fc3f4658937fb81fcc16a89738e83bd8d4795)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: ed4bad29e7dd437f7a8168dbe04b15909d945de9
https://github.com/qemu/qemu/commit/ed4bad29e7dd437f7a8168dbe04b15909d945de9
Author: Solomon Tan <[email protected]>
Date: 2025-07-02 (Wed, 02 Jul 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Make RETA[AB] UNDEF when pauth is not implemented
According to the Arm A-profile A64 Instruction Set Architecture,
RETA[AB] should be decoded as UNDEF if the pauth feature is not
implemented.
We got this right in the initial implementation, but accidentally
dropped the feature-check when we converted these insns to
decodetree.
Cc: [email protected]
Fixes: 0ebbe9021254f ("target/arm: Convert BRA[AB]Z, BLR[AB]Z, RETA[AB] to
decodetree")
Signed-off-by: Solomon Tan <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit 9a3bf0e0ab628de7051b41a88c4628aa9e4d311b)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 5df7910a237ccb8ebd31f45d4216f3765c6010ed
https://github.com/qemu/qemu/commit/5df7910a237ccb8ebd31f45d4216f3765c6010ed
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-07-02 (Wed, 02 Jul 2025)
Changed paths:
M target/arm/hvf/hvf.c
M target/arm/kvm.c
Log Message:
-----------
target/arm: Correct KVM & HVF dtb_compatible value
Linux kernel knows how to parse "arm,armv8", not "arm,arm-v8".
See arch/arm64/boot/dts/foundation-v8.dts:
https://github.com/torvalds/linux/commit/90556ca1ebdd
Cc: [email protected]
Fixes: 26861c7ce06 ("target-arm: Add minimal KVM AArch64 support")
Fixes: 585df85efea ("hvf: arm: Implement -cpu host")
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit a412575837b6a46584fba891e3706e87bd09a3e6)
(Mjt: context fix in target/arm/kvm.c)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: fb9bad329cadba1f09642bb20a5ed2ce709b9dc3
https://github.com/qemu/qemu/commit/fb9bad329cadba1f09642bb20a5ed2ce709b9dc3
Author: Yiwei Zhang <[email protected]>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/display/virtio-gpu-virgl.c
Log Message:
-----------
virtio-gpu: support context init multiple timeline
Venus and later native contexts have their own fence context along with
multiple timelines within. Fences wtih VIRTIO_GPU_FLAG_INFO_RING_IDX in
the flags must be dispatched to be created on the target context. Fence
signaling also has to be handled on the specific timeline within that
target context.
Before this change, venus fencing is completely broken if the host
driver doesn't support implicit fencing with external memory objects.
Frames can go backwards along with random artifacts on screen if the
host driver doesn't attach an implicit fence to the render target. The
symptom could be hidden by certain guest wsi backend that waits on a
venus native VkFence object for the actual payload with limited present
modes or under special configs. e.g. x11 mailbox or xwayland.
After this change, everything related to venus fencing starts making
sense. Confirmed this via guest and host side perfetto tracing.
Cc: [email protected]
Fixes: 94d0ea1c1928 ("virtio-gpu: Support Venus context")
Signed-off-by: Yiwei Zhang <[email protected]>
Reviewed-by: Dmitry Osipenko <[email protected]>
Message-Id: <[email protected]>
[AJB: remove version history from commit message]
Tested-by: Dmitry Osipenko <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Message-ID: <[email protected]>
(cherry picked from commit 1fa2ffdbec55d84326e22f046bc3e26322836f5a)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: b8f48f40334cb54df36e796b1e825a9061e0fbce
https://github.com/qemu/qemu/commit/b8f48f40334cb54df36e796b1e825a9061e0fbce
Author: Kevin Wolf <[email protected]>
Date: 2025-07-03 (Thu, 03 Jul 2025)
Changed paths:
M hw/s390x/ccw-device.c
Log Message:
-----------
hw/s390x/ccw-device: Fix memory leak in loadparm setter
Commit bdf12f2a fixed the setter for the "loadparm" machine property,
which gets a string from a visitor, passes it to s390_ipl_fmt_loadparm()
and then forgot to free it. It left another instance of the same problem
unfixed in the "loadparm" device property. Fix it.
Signed-off-by: Kevin Wolf <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Reviewed-by: Halil Pasic <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
(cherry picked from commit 78e3781541209b3dcd6f4bb66adf3a3e504b88a4)
(Mjt: bdf12f2a is 8efe1592 in stable-10.0 branch)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 83b48a500f2f96f9403f7d255d9c58c623342542
https://github.com/qemu/qemu/commit/83b48a500f2f96f9403f7d255d9c58c623342542
Author: Richard Henderson <[email protected]>
Date: 2025-07-08 (Tue, 08 Jul 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Fix SME vs AdvSIMD exception priority
We failed to raise an exception when
sme_excp_el == 0 and fp_excp_el == 1.
Cc: [email protected]
Fixes: 3d74825f4d6 ("target/arm: Add SME enablement checks")
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit f9b0f69304071384b12912bf9dd78e9ffd261cec)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 0e5f0d87f8e07d72688537282e19881cb9a323e6
https://github.com/qemu/qemu/commit/0e5f0d87f8e07d72688537282e19881cb9a323e6
Author: Richard Henderson <[email protected]>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Fix sve_access_check for SME
Do not assume SME implies SVE. Ensure that the non-streaming
check is present along the SME path, since it is not implied
by sme_*_enabled_check.
Cc: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit b4b2e070f41dd8774a70c6186141678558d79a38)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: c76ec8d575fb8194a59908d25828286702390903
https://github.com/qemu/qemu/commit/c76ec8d575fb8194a59908d25828286702390903
Author: Richard Henderson <[email protected]>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Fix 128-bit element ZIP, UZP, TRN
We missed the instructions UDEF when the vector size is too small.
We missed marking the instructions non-streaming with SME.
Cc: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit e6ffd009c7710a8cc98094897fa0af609c114683)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 9af1de0c4be21a37188af0a27b1b5c250004281c
https://github.com/qemu/qemu/commit/9af1de0c4be21a37188af0a27b1b5c250004281c
Author: Richard Henderson <[email protected]>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M target/arm/tcg/translate-sve.c
Log Message:
-----------
target/arm: Fix PSEL size operands to tcg_gen_gvec_ands
Gvec only operates on size 8 and multiples of 16.
Predicates may be any multiple of 2.
Round up the size using the appropriate function.
Cc: [email protected]
Fixes: 598ab0b24c0 ("target/arm: Implement PSEL")
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit 3801c5b75ffc60957265513338e8fd5f8b6ce8a1)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 9a98db505f20d2e221ef086423483e028ed11937
https://github.com/qemu/qemu/commit/9a98db505f20d2e221ef086423483e028ed11937
Author: Richard Henderson <[email protected]>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M target/arm/tcg/sme_helper.c
Log Message:
-----------
target/arm: Fix f16_dotadd vs nan selection
Implement FPProcessNaNs4 within f16_dotadd, rather than
simply letting NaNs propagate through the function.
Cc: [email protected]
Fixes: 3916841ac75 ("target/arm: Implement FMOPA, FMOPS (widening)")
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit cfc688c00ade84f6b32c7814b52c217f1d3b5eb1)
Signed-off-by: Michael Tokarev <[email protected]>
Commit: 005184da9d95f81ea6022e3f2e1dd95a881948be
https://github.com/qemu/qemu/commit/005184da9d95f81ea6022e3f2e1dd95a881948be
Author: Richard Henderson <[email protected]>
Date: 2025-07-09 (Wed, 09 Jul 2025)
Changed paths:
M target/arm/tcg/vec_helper.c
Log Message:
-----------
target/arm: Fix bfdotadd_ebf vs nan selection
Implement FPProcessNaNs4 within bfdotadd_ebf, rather than
simply letting NaNs propagate through the function.
Cc: [email protected]
Fixes: 0e1850182a1 ("target/arm: Implement FPCR.EBF=1 semantics for bfdotadd()")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
(cherry picked from commit bf020eaa6741711902a425016e2c7585f222562d)
Signed-off-by: Michael Tokarev <[email protected]>
Compare: https://github.com/qemu/qemu/compare/ab96ea4b4d25...005184da9d95
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