Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 301fbbaf03fb114a1e45833987ddfd7bbb403963
https://github.com/qemu/qemu/commit/301fbbaf03fb114a1e45833987ddfd7bbb403963
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/trace-events
Log Message:
-----------
ppc/xive: Fix xive trace event output
Typo, IBP should be IPB.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f0aab779418ed883ea2b5ffcc3985ef26f6e3545
https://github.com/qemu/qemu/commit/f0aab779418ed883ea2b5ffcc3985ef26f6e3545
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Report access size in XIVE TM operation error logs
Report access size in XIVE TM operation error logs.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f16697292add6c3c15014a20fd5fce70b8c56734
https://github.com/qemu/qemu/commit/f16697292add6c3c15014a20fd5fce70b8c56734
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: Fix calculation of END queue sizes
The queue size of an Event Notification Descriptor (END)
is determined by the 'cl' and QsZ fields of the END.
If the cl field is 1, then the queue size (in bytes) will
be the size of a cache line 128B * 2^QsZ and QsZ is limited
to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited
to 12.
Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework")
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: e8cf73b849879cd93b1d1b5fd3bde79fb42064dc
https://github.com/qemu/qemu/commit/e8cf73b849879cd93b1d1b5fd3bde79fb42064dc
Author: Michael Kowal <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
ppc/xive2: Remote VSDs need to match on forwarding address
In a multi chip environment there will be remote/forwarded VSDs. The check
to find a matching INT controller (XIVE) of the remote block number was
checking the INTs chip number. Block numbers are not tied to a chip number.
The matching remote INT is the one that matches the forwarded VSD address
with VSD types associated MMIO BAR.
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
[ clg: Fixed log format in pnv_xive2_get_remote() ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d1023a296c8297454fc4b207d58707c0a5e62e0a
https://github.com/qemu/qemu/commit/d1023a296c8297454fc4b207d58707c0a5e62e0a
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: fix context push calculation of IPB priority
Pushing a context and loading IPB from NVP is defined to merge ('or')
that IPB into the TIMA IPB register. PIPR should therefore be calculated
based on the final IPB value, not just the NVP value.
Fixes: 9d2b6058c5b ("ppc/xive2: Add grouping level to notification")
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: bde8c148bb22b99cb84cda800fa555851b8cb358
https://github.com/qemu/qemu/commit/bde8c148bb22b99cb84cda800fa555851b8cb358
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Fix PHYS NSR ring matching
Test that the NSR exception bit field is equal to the pool ring value,
rather than any common bits set, which is more correct (although there
is no practical bug because the LSI NSR type is not implemented and
POOL/PHYS NSR are encoded with exclusive bits).
Fixes: 4c3ccac636 ("pnv/xive: Add special handling for pool targets")
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 576830428eea6ebfc85792851a343214b834e401
https://github.com/qemu/qemu/commit/576830428eea6ebfc85792851a343214b834e401
Author: Michael Kowal <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Reset Generation Flipped bit on END Cache Watch
When the END Event Queue wraps the END EQ Generation bit is flipped and the
Generation Flipped bit is set to one. On a END cache Watch read operation,
the Generation Flipped bit needs to be reset.
While debugging an error modified END not valid error messages to include
the method since all were the same.
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a1577527e212efd27a8ceefbd95321c306abf739
https://github.com/qemu/qemu/commit/a1577527e212efd27a8ceefbd95321c306abf739
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
ppc/xive2: Use fair irq target search algorithm
The current xive algorithm for finding a matching group vCPU
target always uses the first vCPU found. And, since it always
starts the search with thread 0 of a core, thread 0 is almost
always used to handle group interrupts. This can lead to additional
interrupt latency and poor performance for interrupt intensive
work loads.
Changing this to use a simple round-robin algorithm for deciding which
thread number to use when starting a search, which leads to a more
distributed use of threads for handling group interrupts.
[npiggin: Also round-robin among threads, not just cores]
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8d373176181fbc11f8d8eae2b4532b867f083ea6
https://github.com/qemu/qemu/commit/8d373176181fbc11f8d8eae2b4532b867f083ea6
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Fix irq preempted by lower priority group irq
A problem was seen where uart interrupts would be lost resulting in the
console hanging. Traces showed that a lower priority interrupt was
preempting a higher priority interrupt, which would result in the higher
priority interrupt never being handled.
The new interrupt's priority was being compared against the CPPR
(Current Processor Priority Register) instead of the PIPR (Post
Interrupt Priority Register), as was required by the XIVE spec.
This allowed for a window between raising an interrupt and ACK'ing
the interrupt where a lower priority interrupt could slip in.
Fixes: 26c55b99418 ("ppc/xive2: Process group backlog when updating the CPPR")
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d4720a7faf4bb415f3fe7f10e5c888212b81316a
https://github.com/qemu/qemu/commit/d4720a7faf4bb415f3fe7f10e5c888212b81316a
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Fix treatment of PIPR in CPPR update
According to the XIVE spec, updating the CPPR should also update the
PIPR. The final value of the PIPR depends on other factors, but it
should never be set to a value that is above the CPPR.
Also added support for redistributing an active group interrupt when it
is precluded as a result of changing the CPPR value.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3abbec04e627396c32f2b7b7461961fb68c5c122
https://github.com/qemu/qemu/commit/3abbec04e627396c32f2b7b7461961fb68c5c122
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Do not present group interrupt on OS-push if precluded by CPPR
Group interrupts should not be taken from the backlog and presented
if they are precluded by CPPR.
Fixes: 855434b3b8 ("ppc/xive2: Process group backlog when pushing an OS
context")
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ad9175f8a2d7b4ef7d63e9663a42e7f7a44bc3f5
https://github.com/qemu/qemu/commit/ad9175f8a2d7b4ef7d63e9663a42e7f7a44bc3f5
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Set CPPR delivery should account for group priority
The group interrupt delivery flow selects the group backlog scan if
LSMFB < IPB, but that scan may find an interrupt with a priority >=
IPB. In that case, the VP-direct interrupt should be chosen. This
extends to selecting the lowest prio between POOL and PHYS rings.
Implement this just by re-starting the selection logic if the
backlog irq was not found or priority did not match LSMFB (LSMFB
is updated so next time around it would see the right value and
not loop infinitely).
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 14bcc5239f4d4780ec52881779161c62c46e7243
https://github.com/qemu/qemu/commit/14bcc5239f4d4780ec52881779161c62c46e7243
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: tctx_notify should clear the precluded interrupt
If CPPR is lowered to preclude the pending interrupt, NSR should be
cleared and the qemu_irq should be lowered. This avoids some cases
of supurious interrupts.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda
https://github.com/qemu/qemu/commit/9d466ab9b6f27a5d5b7a0ec5a7ad6f60e82fafda
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Explicitly zero NSR after accepting
Have xive_tctx_accept clear NSR in one shot rather than masking out bits
as they are tested, which makes it clear it's reset to 0, and does not
have a partial NSR value in the register.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 261626dce11311ba4e866272c9a2c0990c53d85c
https://github.com/qemu/qemu/commit/261626dce11311ba4e866272c9a2c0990c53d85c
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Move NSR decoding into helper functions
Rather than functions to return masks to test NSR bits, have functions
to test those bits directly. This should be no functional change, it
just makes the code more readable.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 279031bc03e6f59d58f4de37b06bddaa03e4f209
https://github.com/qemu/qemu/commit/279031bc03e6f59d58f4de37b06bddaa03e4f209
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Fix pulling pool and phys contexts
This improves the implementation of pulling pool and phys contexts in
XIVE1, by following closer the OS pulling code.
In particular, the old ring data is returned rather than the modified,
and irq signals are reset on pull.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c2cee7477f4af8cdfc33c5bb5928a3a1862655ee
https://github.com/qemu/qemu/commit/c2cee7477f4af8cdfc33c5bb5928a3a1862655ee
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
pnv/xive2: Support ESB Escalation
Add support for XIVE ESB Interrupt Escalation.
Suggested-by: Michael Kowal <[email protected]>
[This change was taken from a patch provided by Michael Kowal.]
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 14cbb7bf1245c2d9166be0309c9407845783b281
https://github.com/qemu/qemu/commit/14cbb7bf1245c2d9166be0309c9407845783b281
Author: Michael Kowal <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Print value in invalid register write logging
This can make it easier to see what the target system is trying to
do.
[npiggin: split from larger patch]
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d273abbfba47ef47e331dc22731c7d2a15e95c9a
https://github.com/qemu/qemu/commit/d273abbfba47ef47e331dc22731c7d2a15e95c9a
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: VC_ENDC_WATCH_SPEC regs should read back WATCH_FULL
Firmware expects to read back the WATCH_FULL bit from the VC_ENDC_WATCH_SPEC
register, so don't clear it on read.
Don't bother clearing the reads-as-zero CONFLICT bit because it's masked
at write already.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9898cc80306588eb6a1c44b7ba38f207ca8bdcfa
https://github.com/qemu/qemu/commit/9898cc80306588eb6a1c44b7ba38f207ca8bdcfa
Author: Michael Kowal <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
Log Message:
-----------
pnv/xive2: Permit valid writes to VC/PC Flush Control registers
Writes to the Flush Control registers were logged as invalid
when they are allowed. Clearing the unsupported want_cache_disable
feature is supported, so don't log an error in that case.
Signed-off-by: Michael Kowal <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Reviewed-by: Caleb Schlossin <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b22ffb42999504614a1bef3a52c5b2e6549e8de6
https://github.com/qemu/qemu/commit/b22ffb42999504614a1bef3a52c5b2e6549e8de6
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
M include/hw/ppc/xive2.h
Log Message:
-----------
ppc/xive2: add interrupt priority configuration flags
Adds support for extracting additional configuration flags from
the XIVE configuration register that are needed for redistribution
of group interrupts.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 555e446019f58e488ccf9fc416667be450e3f32f
https://github.com/qemu/qemu/commit/555e446019f58e488ccf9fc416667be450e3f32f
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: Support redistribution of group interrupts
When an XIVE context is pulled while it has an active, unacknowledged
group interrupt, XIVE will check to see if a context on another thread
can handle the interrupt and, if so, notify that context. If there
are no contexts that can handle the interrupt, then the interrupt is
added to a backlog and XIVE will attempt to escalate the interrupt,
if configured to do so, allowing the higher privileged handler to
activate a context that can handle the original interrupt.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 701ab1857a9175a86e3ad6f18958df631af86a62
https://github.com/qemu/qemu/commit/701ab1857a9175a86e3ad6f18958df631af86a62
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/trace-events
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive: Add more interrupt notification tracing
Add more tracing around notification, redistribution, and escalation.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 1a0cd94252bf111b0ace7b9cd88258e837d95ea4
https://github.com/qemu/qemu/commit/1a0cd94252bf111b0ace7b9cd88258e837d95ea4
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Improve pool regs variable name
Change pregs to pool_regs, for clarity.
[npiggin: split from larger patch]
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 97cd373e6ca0024132e78496b8a585c00531f7a4
https://github.com/qemu/qemu/commit/97cd373e6ca0024132e78496b8a585c00531f7a4
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
M include/hw/ppc/xive2.h
Log Message:
-----------
ppc/xive2: Implement "Ack OS IRQ to even report line" TIMA op
Booting AIX in a PowerVM partition requires the use of the "Acknowledge
O/S Interrupt to even O/S reporting line" special operation provided by
the IBM XIVE interrupt controller. This operation is invoked by writing
a byte (data is irrelevant) to offset 0xC10 of the Thread Interrupt
Management Area (TIMA). It can be used by software to notify the XIVE
logic that the interrupt was received.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9ad30401ce9aefa319364cb8efdc6893a5bc20ad
https://github.com/qemu/qemu/commit/9ad30401ce9aefa319364cb8efdc6893a5bc20ad
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Redistribute group interrupt precluded by CPPR update
Add support for redistributing a presented group interrupt if it
is precluded as a result of changing the CPPR value. Without this,
group interrupts can be lost.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Nicholas Piggin <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 64c772ca16fcb539380a777ff273278c42f5dfef
https://github.com/qemu/qemu/commit/64c772ca16fcb539380a777ff273278c42f5dfef
Author: Glenn Miles <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: redistribute irqs for pool and phys ctx pull
When disabling (pulling) an xive interrupt context, we need
to redistribute any active group interrupts to other threads
that can handle the interrupt if possible. This support had
already been added for the OS context but had not yet been
added to the pool or physical context.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 1319cb8997b9d0fdaae04a79398a2ed06d4cb5e1
https://github.com/qemu/qemu/commit/1319cb8997b9d0fdaae04a79398a2ed06d4cb5e1
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/pnv_xive2.c
M hw/intc/spapr_xive.c
M hw/intc/xive.c
M hw/intc/xive2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Change presenter .match_nvt to match not present
Have the match_nvt method only perform a TCTX match but don't present
the interrupt, the caller presents. This has no functional change, but
allows for more complicated presentation logic after matching.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cc15d50b6e8a4090d667755259ea36144b79d22f
https://github.com/qemu/qemu/commit/cc15d50b6e8a4090d667755259ea36144b79d22f
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Redistribute group interrupt preempted by higher priority interrupt
A group interrupt that gets preempted by a higher priority interrupt
delivery must be redistributed otherwise it would get lost.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d16214ed2c57a31b5de7e2c115c65b831170a60e
https://github.com/qemu/qemu/commit/d16214ed2c57a31b5de7e2c115c65b831170a60e
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Add xive_tctx_pipr_present() to present new interrupt
xive_tctx_pipr_update() is used for multiple things. In an effort
to make things simpler and less overloaded, split out the function
that is used to present a new interrupt to the tctx.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 46f5ee8885a521c56e60820bf35aba4e94e16cf7
https://github.com/qemu/qemu/commit/46f5ee8885a521c56e60820bf35aba4e94e16cf7
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Fix high prio group interrupt being preempted by low prio VP
xive_tctx_pipr_present() as implemented with xive_tctx_pipr_update()
causes VP-directed (group==0) interrupt to be presented in PIPR and NSR
despite being a lower priority than the currently presented group
interrupt.
This must not happen. The IPB bit should record the low priority VP
interrupt, but PIPR and NSR must not present the lower priority
interrupt.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3516b9b6739714068d83bb5ed9ce25cc1b20be8d
https://github.com/qemu/qemu/commit/3516b9b6739714068d83bb5ed9ce25cc1b20be8d
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: Split xive recompute from IPB function
Further split xive_tctx_pipr_update() by splitting out a new function
that is used to re-compute the PIPR from IPB. This is generally only
used with XIVE1, because group interrputs require more logic.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 581bec5a04c5c27a86cfae93ca531c101f2df2ec
https://github.com/qemu/qemu/commit/581bec5a04c5c27a86cfae93ca531c101f2df2ec
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: tctx signaling registers rework
The tctx "signaling" registers (PIPR, CPPR, NSR) raise an interrupt on
the target CPU thread. The POOL and PHYS rings both raise hypervisor
interrupts, so they both share one set of signaling registers in the
PHYS ring. The PHYS NSR register contains a field that indicates which
ring has presented the interrupt being signaled to the CPU.
This sharing results in all the "alt_regs" throughout the code. alt_regs
is not very descriptive, and worse is that the name is used for
conversions in both directions, i.e., to find the presenting ring from
the signaling ring, and the signaling ring from the presenting ring.
Instead of alt_regs, use the names sig_regs and sig_ring, and regs and
ring for the presenting ring being worked on. Add a helper function to
get the sign_regs, and add some asserts to ensure the POOL regs are
never used to signal interrupts.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf
https://github.com/qemu/qemu/commit/cf454eaa96e8a0c3c1de63b0f7b85542d7c5ecbf
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive: tctx_accept only lower irq line if an interrupt was presented
The relationship between an interrupt signaled in the TIMA and the QEMU
irq line to the processor to be 1:1, so they should be raised and
lowered together and "just in case" lowering should be avoided (it could
mask
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 64a18e0c37a6b5c3d94541ff0599ea84fec998c0
https://github.com/qemu/qemu/commit/64a18e0c37a6b5c3d94541ff0599ea84fec998c0
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Add xive_tctx_pipr_set() helper function
Have xive_tctx_notify() also set the new PIPR value and rename it to
xive_tctx_pipr_set(). This can replace the last xive_tctx_pipr_update()
caller because it does not need to update IPB (it already sets it).
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 384f0365abae49b3d6a1cd46e8ae3cf4b9d4013e
https://github.com/qemu/qemu/commit/384f0365abae49b3d6a1cd46e8ae3cf4b9d4013e
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: split tctx presentation processing from set CPPR
The second part of the set CPPR operation is to process (or re-present)
any pending interrupts after CPPR is adjusted.
Split this presentation processing out into a standalone function that
can be used in other places.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 04627e2206dce95ecda486abf70d0ef7dd9f39f4
https://github.com/qemu/qemu/commit/04627e2206dce95ecda486abf70d0ef7dd9f39f4
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Consolidate presentation processing in context push
OS-push operation must re-present pending interrupts. Use the
newly created xive2_tctx_process_pending() function instead of
duplicating the logic.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 370ea4a4b6fffc30324fc8f8134483e5a749114d
https://github.com/qemu/qemu/commit/370ea4a4b6fffc30324fc8f8134483e5a749114d
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Avoid needless interrupt re-check on CPPR set
When CPPR priority is decreased, pending interrupts do not need to be
re-checked if one is already presented because by definition that will
be the highest priority.
This prevents a presented group interrupt from being lost.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 203181cebdb96283520b496d6eaa49634eb51579
https://github.com/qemu/qemu/commit/203181cebdb96283520b496d6eaa49634eb51579
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive: Assert group interrupts were redistributed
Add some assertions to try to ensure presented group interrupts do
not get lost without being redistributed, if they become precluded
by CPPR or preempted by a higher priority interrupt.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 365e322cfb86b2e7131c3290c3a61f8d2bb224d3
https://github.com/qemu/qemu/commit/365e322cfb86b2e7131c3290c3a61f8d2bb224d3
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
ppc/xive2: implement NVP context save restore for POOL ring
In preparation to implement POOL context push, add support for POOL
NVP context save/restore.
The NVP p bit is defined in the spec as follows:
If TRUE, the CPPR of a Pool VP in the NVP is updated during store of
the context with the CPPR of the Hard context it was running under.
It's not clear whether non-pool VPs always or never get CPPR updated.
Before this patch, OS contexts always save CPPR, so we will assume that
is the behaviour.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 7a40b50757b55c2d4233c304f32df5afdd1bd63a
https://github.com/qemu/qemu/commit/7a40b50757b55c2d4233c304f32df5afdd1bd63a
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Prevent pulling of pool context losing phys interrupt
When the pool context is pulled, the shared pool/phys signal is
reset, which loses the qemu irq if a phys interrupt was presented.
Only reset the signal if a poll irq was presented.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 565e6d4d2151e856026ee60d16c12a61e667cd15
https://github.com/qemu/qemu/commit/565e6d4d2151e856026ee60d16c12a61e667cd15
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive: Redistribute phys after pulling of pool context
After pulling the pool context, if a pool irq had been presented and
was cleared in the process, there could be a pending irq in phys that
should be presented. Process the phys irq ring after pulling pool ring
to catch this case and avoid losing irqs.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ca0081ef7ece566e877e9f4ceab9e9988d08fb78
https://github.com/qemu/qemu/commit/ca0081ef7ece566e877e9f4ceab9e9988d08fb78
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M include/hw/ppc/xive.h
Log Message:
-----------
ppc/xive: Check TIMA operations validity
Certain TIMA operations should only be performed when a ring is valid,
others when the ring is invalid, and they are considered undefined if
used incorrectly. Add checks for this condition.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ba127a1e48d34f6c805000dc881e240fc4f2bd1d
https://github.com/qemu/qemu/commit/ba127a1e48d34f6c805000dc881e240fc4f2bd1d
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
Log Message:
-----------
ppc/xive2: Implement pool context push TIMA op
Implement pool context push TIMA op.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6936d2f561759c00993217a424ddeb1554c5f1ff
https://github.com/qemu/qemu/commit/6936d2f561759c00993217a424ddeb1554c5f1ff
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: redistribute group interrupts on context push
When pushing a context, any presented group interrupt should be
redistributed before processing pending interrupts to present
highest priority.
This can occur when pushing the POOL ring when the valid PHYS
ring has a group interrupt presented, because they share signal
registers.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6ef77843603b89b1e48a06ca0644e74e45297839
https://github.com/qemu/qemu/commit/6ef77843603b89b1e48a06ca0644e74e45297839
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
Log Message:
-----------
ppc/xive2: Implement set_os_pending TIMA op
xive2 must take into account redistribution of group interrupts if
the VP directed priority exceeds the group interrupt priority after
this operation. The xive1 code is not group aware so implement this
for xive2.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f030f35109062a3cf815e12939a66c9df8354714
https://github.com/qemu/qemu/commit/f030f35109062a3cf815e12939a66c9df8354714
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
Log Message:
-----------
ppc/xive2: Implement POOL LGS push TIMA op
Implement set LGS for the POOL ring.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 714bae7351d9c85643d6b48109f59f20f05c8466
https://github.com/qemu/qemu/commit/714bae7351d9c85643d6b48109f59f20f05c8466
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
M include/hw/ppc/xive2.h
Log Message:
-----------
ppc/xive2: Implement PHYS ring VP push TIMA op
Implement the phys (aka hard) VP push. PowerVM uses this operation.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3a50f36469c318d3c66360a8e5ada6f2dc1a349d
https://github.com/qemu/qemu/commit/3a50f36469c318d3c66360a8e5ada6f2dc1a349d
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive.c
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive: Split need_resend into restore_nvp
This is needed by the next patch which will re-send on all lower
rings when pushing a context.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: df3614b7983e0629b0d422259968985ca0117bfa
https://github.com/qemu/qemu/commit/df3614b7983e0629b0d422259968985ca0117bfa
Author: Nicholas Piggin <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Enable lower level contexts on VP push
When pushing a context, the lower-level context becomes valid if it
had V=1, and so on. Iterate lower level contexts and send them
pending interrupts if they become enabled.
Signed-off-by: Nicholas Piggin <[email protected]>
Reviewed-by: Glenn Miles <[email protected]>
Reviewed-by: Michael Kowal <[email protected]>
Tested-by: Gautam Menghani <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 4bc8fb0135ac48cd1c8f0698976b7d73c60b7caa
https://github.com/qemu/qemu/commit/4bc8fb0135ac48cd1c8f0698976b7d73c60b7caa
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-07-21 (Mon, 21 Jul 2025)
Changed paths:
M hw/intc/pnv_xive.c
M hw/intc/pnv_xive2.c
M hw/intc/pnv_xive2_regs.h
M hw/intc/spapr_xive.c
M hw/intc/trace-events
M hw/intc/xive.c
M hw/intc/xive2.c
M hw/ppc/pnv.c
M hw/ppc/spapr.c
M include/hw/ppc/xive.h
M include/hw/ppc/xive2.h
M include/hw/ppc/xive2_regs.h
Log Message:
-----------
Merge tag 'pull-ppc-20250721' of https://github.com/legoater/qemu into staging
ppc/xive queue:
* Various bug fixes around lost interrupts particularly.
* Major group interrupt work, in particular around redistributing
interrupts. Upstream group support is not in a complete or usable
state as it is.
* Significant context push/pull improvements, particularly pool and
phys context handling was quite incomplete beyond trivial OPAL
case that pushes at boot.
* Improved tracing and checking for unimp and guest error situations.
* Various other missing feature support.
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# gpg: Signature made Mon 21 Jul 2025 03:08:07 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-ppc-20250721' of https://github.com/legoater/qemu: (50 commits)
ppc/xive2: Enable lower level contexts on VP push
ppc/xive: Split need_resend into restore_nvp
ppc/xive2: Implement PHYS ring VP push TIMA op
ppc/xive2: Implement POOL LGS push TIMA op
ppc/xive2: Implement set_os_pending TIMA op
ppc/xive2: redistribute group interrupts on context push
ppc/xive2: Implement pool context push TIMA op
ppc/xive: Check TIMA operations validity
ppc/xive: Redistribute phys after pulling of pool context
ppc/xive2: Prevent pulling of pool context losing phys interrupt
ppc/xive2: implement NVP context save restore for POOL ring
ppc/xive: Assert group interrupts were redistributed
ppc/xive2: Avoid needless interrupt re-check on CPPR set
ppc/xive2: Consolidate presentation processing in context push
ppc/xive2: split tctx presentation processing from set CPPR
ppc/xive: Add xive_tctx_pipr_set() helper function
ppc/xive: tctx_accept only lower irq line if an interrupt was presented
ppc/xive: tctx signaling registers rework
ppc/xive: Split xive recompute from IPB function
ppc/xive: Fix high prio group interrupt being preempted by low prio VP
...
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/ebcc602aae19...4bc8fb0135ac
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