Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 77707bfdf871199bbee665e721ced961aaf3a798
https://github.com/qemu/qemu/commit/77707bfdf871199bbee665e721ced961aaf3a798
Author: Vac Chen <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/pmp.c
Log Message:
-----------
target/riscv: Fix pmp range wraparound on zero
pmp_is_in_range() prefers to match addresses within the interval
[start, end]. To archieve this, pmpaddrX is decremented during the end
address update.
In TOR mode, a rule is ignored if its start address is greater than or
equal to its end address.
However, if pmpaddrX is set to 0, this decrement operation causes the
calulated end address to wrap around to UINT_MAX. In this scenario, the
address guard for this PMP entry would become ineffective.
This patch addresses the issue by moving the guard check earlier,
preventing the problematic wraparound when pmpaddrX is zero.
Signed-off-by: Vac Chen <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 35d129399d319b7ab806e82ebacd52392e36bf61
https://github.com/qemu/qemu/commit/35d129399d319b7ab806e82ebacd52392e36bf61
Author: Sunil V L <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
Signed-off-by: Sunil V L <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: a3b95362ce90d03d150dffed3add0cb600fb0850
https://github.com/qemu/qemu/commit/a3b95362ce90d03d150dffed3add0cb600fb0850
Author: Sunil V L <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M hw/riscv/virt-acpi-build.c
Log Message:
-----------
hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
RISC-V support is added only in ACPI 6.6. According to the ACPI 6.6
specification, the minor version of the Fixed ACPI Description Table
(FADT) should be 6, and the Multiple APIC Description Table (MADT)
should use revision 7. So, update the RISC-V FADT and MADT to reflect
correct versions.
Update the code comments to reflect ACPI 6.6 version details.
Signed-off-by: Sunil V L <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: f3c8b7767f2e1fac37c727ca17b69e4f1e3351f2
https://github.com/qemu/qemu/commit/f3c8b7767f2e1fac37c727ca17b69e4f1e3351f2
Author: Sunil V L <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M tests/data/acpi/riscv64/virt/APIC
M tests/data/acpi/riscv64/virt/FACP
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/data/acpi/riscv64: Update expected FADT and MADT
Update the expected tables for the version change.
/*
*
* ACPI Data Table [FACP]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 0000 004h] Signature : "FACP" [Fixed ACPI
Description Table (FADT)]
[004h 0004 004h] Table Length : 00000114
[008h 0008 001h] Revision : 06
-[009h 0009 001h] Checksum : 13
+[009h 0009 001h] Checksum : 12
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[018h 0024 004h] Oem Revision : 00000001
[01Ch 0028 004h] Asl Compiler ID : "BXPC"
[020h 0032 004h] Asl Compiler Revision : 00000001
[024h 0036 004h] FACS Address : 00000000
[028h 0040 004h] DSDT Address : 00000000
[02Ch 0044 001h] Model : 00
[02Dh 0045 001h] PM Profile : 00 [Unspecified]
[02Eh 0046 002h] SCI Interrupt : 0000
[030h 0048 004h] SMI Command Port : 00000000
[034h 0052 001h] ACPI Enable Value : 00
[035h 0053 001h] ACPI Disable Value : 00
[036h 0054 001h] S4BIOS Command : 00
[037h 0055 001h] P-State Control : 00
@@ -86,33 +86,33 @@
Use APIC Physical Destination Mode (V4) : 0
Hardware Reduced (V5) : 1
Low Power S0 Idle (V5) : 0
[074h 0116 00Ch] Reset Register : [Generic Address Structure]
[074h 0116 001h] Space ID : 00 [SystemMemory]
[075h 0117 001h] Bit Width : 00
[076h 0118 001h] Bit Offset : 00
[077h 0119 001h] Encoded Access Width : 00 [Undefined/Legacy]
[078h 0120 008h] Address : 0000000000000000
[080h 0128 001h] Value to cause reset : 00
[081h 0129 002h] ARM Flags (decoded below) : 0000
PSCI Compliant : 0
Must use HVC for PSCI : 0
-[083h 0131 001h] FADT Minor Revision : 05
+[083h 0131 001h] FADT Minor Revision : 06
[084h 0132 008h] FACS Address : 0000000000000000
[...]
/*
*
* ACPI Data Table [APIC]
*
* Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue (in
hex)
*/
[000h 0000 004h] Signature : "APIC" [Multiple APIC
Description Table (MADT)]
[004h 0004 004h] Table Length : 00000074
-[008h 0008 001h] Revision : 06
-[009h 0009 001h] Checksum : B4
+[008h 0008 001h] Revision : 07
+[009h 0009 001h] Checksum : B3
[00Ah 0010 006h] Oem ID : "BOCHS "
[010h 0016 008h] Oem Table ID : "BXPC "
[...]
Signed-off-by: Sunil V L <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b6f1244678bebaf7e2c775cfc66d452f95678ebf
https://github.com/qemu/qemu/commit/b6f1244678bebaf7e2c775cfc66d452f95678ebf
Author: Yang Jialong <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
intc/riscv_aplic: Fix target register read when source is inactive
The RISC-V Advanced interrupt Architecture:
4.5.16. Interrupt targets:
If interrupt source i is inactive in this domain, register target[i] is
read-only zero.
Signed-off-by: Yang Jialong <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e111ffe48b29ca8abd450af9ee5dd71af3f93536
https://github.com/qemu/qemu/commit/e111ffe48b29ca8abd450af9ee5dd71af3f93536
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M linux-user/strace.list
Log Message:
-----------
linux-user/strace.list: add riscv_hwprobe entry
We're missing a strace entry for riscv_hwprobe, and using -strace will
report it as "Unknown syscall 258".
After this patch we'll have:
$ ./build/qemu-riscv64 -strace test_mutex_riscv
110182 riscv_hwprobe(0x7f207efdc700,1,0,0,0,0) = 0
110182 brk(NULL) = 0x0000000000082000
(...)
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 16aa7771afeac422dcf7be2833d5426da6b814fa
https://github.com/qemu/qemu/commit/16aa7771afeac422dcf7be2833d5426da6b814fa
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/op_helper.c
Log Message:
-----------
target/riscv: do not call GETPC() in check_ret_from_m_mode()
GETPC() should always be called from the top level helper, e.g. the
first helper that is called by the translation code. We stopped doing
that in commit 3157a553ec, and then we introduced problems when
unwinding the exceptions being thrown by helper_mret(), as reported by
[1].
Call GETPC() at the top level helper and pass the value along.
[1] https://gitlab.com/qemu-project/qemu/-/issues/3020
Suggested-by: Richard Henderson <[email protected]>
Fixes: 3157a553ec ("target/riscv: Add Smrnmi mnret instruction")
Closes: https://gitlab.com/qemu-project/qemu/-/issues/3020
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 09ac27a9b59bf87786cb35f7126fb5788b0b4bca
https://github.com/qemu/qemu/commit/09ac27a9b59bf87786cb35f7126fb5788b0b4bca
Author: Daniel Henrique Barboza <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
Log Message:
-----------
riscv: Revert "Generate strided vector loads/stores with tcg nodes."
This reverts commit 28c12c1f2f50d7f7f1ebfc587c4777ecd50aac5b.
As reported in [1] this commit is breaking Linux vector code, and
although a simpler reproducer was provided, the fix itself isn't trivial
due to the amount and the nature of the changes. And we really do not
want to keep Linux broken while we work on it.
The revert will fix Linux and will give us time to do a proper fix.
[1] https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02525.html
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Tested-by: Eric Biggers <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 30ef718423e8018723087cd17be0fd9c6dfa2e53
https://github.com/qemu/qemu/commit/30ef718423e8018723087cd17be0fd9c6dfa2e53
Author: Xu Lu <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Fix exception type when VU accesses supervisor CSRs
When supervisor CSRs are accessed from VU-mode, a virtual instruction
exception should be raised instead of an illegal instruction.
Fixes: c1fbcecb3a (target/riscv: Fix csr number based privilege checking)
Signed-off-by: Xu Lu <[email protected]>
Reviewed-by: Anup Patel <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e443ba03361b63218e6c3aa4f73d2cb5b9b1d372
https://github.com/qemu/qemu/commit/e443ba03361b63218e6c3aa4f73d2cb5b9b1d372
Author: Jay Chang <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
RISC-V Privileged Spec states:
"In harts with S-mode, the medeleg and mideleg registers must exist, and
setting a bit in medeleg or mideleg will delegate the corresponding trap
, when occurring in S-mode or U-mode, to the S-mode trap handler. In
harts without S-mode, the medeleg and mideleg registers should not
exist."
Add smode predicate to ensure these CSRs are only accessible when S-mode
is supported.
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Nutty Liu<[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 86bc3a0abf10072081cddd8dff25aa72c60e67b8
https://github.com/qemu/qemu/commit/86bc3a0abf10072081cddd8dff25aa72c60e67b8
Author: Jay Chang <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Restrict midelegh access to S-mode harts
RISC-V AIA Spec states:
"For a machine-level environment, extension Smaia encompasses all added
CSRs and all modifications to interrupt response behavior that the AIA
specifies for a hart, over all privilege levels. For a supervisor-level
environment, extension Ssaia is essentially the same as Smaia except
excluding the machine-level CSRs and behavior not directly visible to
supervisor level."
Since midelegh is an AIA machine-mode CSR, add Smaia extension check in
aia_smode32 predicate.
Reviewed-by: Frank Chang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Jay Chang <[email protected]>
Reviewed-by: Nutty Liu<[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4e06566dbd1b1251c2788af26a30bd148d4eb6c1
https://github.com/qemu/qemu/commit/4e06566dbd1b1251c2788af26a30bd148d4eb6c1
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-07-30 (Wed, 30 Jul 2025)
Changed paths:
M hw/intc/riscv_aplic.c
M hw/riscv/virt-acpi-build.c
M linux-user/strace.list
M target/riscv/csr.c
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/op_helper.c
M target/riscv/pmp.c
M tests/data/acpi/riscv64/virt/APIC
M tests/data/acpi/riscv64/virt/FACP
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20250730-2' of
https://github.com/alistair23/qemu into staging
Third RISC-V PR for 10.1
* Fix pmp range wraparound on zero
* Update FADT and MADT versions in ACPI tables
* Fix target register read when source is inactive
* Add riscv_hwprobe entry to linux-user strace list
* Do not call GETPC() in check_ret_from_m_mode()
* Revert "Generate strided vector loads/stores with tcg nodes."
* Fix exception type when VU accesses supervisor CSRs
* Restrict mideleg/medeleg/medelegh access to S-mode harts
* Restrict midelegh access to S-mode harts
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmiJbsUACgkQr3yVEwxT
# gBPXCxAAhgcGh/mbdk/DZM4Gx9WqbfjU/1jZR9FCld9im3GLtJfq7IdEcsUZzpNb
# E4sp49lr99qoogKhh3exYhBl0/t0WBoT5mtHNPLFRD3LX2gw6EFQWnD8FN1D//sO
# QvyulomYbmI/Ywf5n5SszF4BpOKh7nyUEZBp4PU6vLT5btsZheSoTyCypH4a7KAy
# GMFNO+O1k6NEwkUqqiIb9Pg8NOp/R3TlNWOjS8fwqyPSU/F8/pzehJQu4WOMAyM8
# eGvqCZiwTg5CcLZfhQZ8dmqJ2qqI44FEzPjyq/Woq5hDmGDMl1iYhgjX5Ozy0X5j
# m4Q+ZH0KIr18EkUD9z4fJbcQAMIm/2b90TShYon6+JYXX8DI8gUCvtg2vgsPAlnS
# M6vgNT25qY8QZa/FbUGcP2+96AlaqX11jUou+TMuJMSr036gTP7gXux5hqYDrd0B
# 4WL1XPcfNZshK5+LAQ+2uwQ9JcKlEaw/mkZHvHgYN7a03UynjCn0oFZtTYvaB4Qx
# Du8Rm9VPlLp3e25VmOiObYyq2Cf6sQXlWomKLJbvfCj217ZXvjOwEjj8hBcg3zJ/
# 6ix/wmDic+YtwmYE7EaGZaExpV5ZjZog61jzMziilZrCJarAoguq0P9tThXGtViX
# TqQcn1V391EfVZYbS3JBO08xmkkX2k7Ia//Th35nByLt7zzrRbs=
# =pKhf
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 29 Jul 2025 21:00:53 EDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu:
target/riscv: Restrict midelegh access to S-mode harts
target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts
target/riscv: Fix exception type when VU accesses supervisor CSRs
riscv: Revert "Generate strided vector loads/stores with tcg nodes."
target/riscv: do not call GETPC() in check_ret_from_m_mode()
linux-user/strace.list: add riscv_hwprobe entry
intc/riscv_aplic: Fix target register read when source is inactive
tests/data/acpi/riscv64: Update expected FADT and MADT
hw/riscv/virt-acpi-build.c: Update FADT and MADT versions
bios-tables-test-allowed-diff.h: Allow RISC-V FADT and MADT changes
target/riscv: Fix pmp range wraparound on zero
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/9b80226ece69...4e06566dbd1b
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications
