Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: cd9f752fee75238f842a91be1146c988bd16a010
https://github.com/qemu/qemu/commit/cd9f752fee75238f842a91be1146c988bd16a010
Author: Alex Richardson <[email protected]>
Date: 2025-07-31 (Thu, 31 Jul 2025)
Changed paths:
M target/arm/cpregs-pmu.c
Log Message:
-----------
target/arm: add support for 64-bit PMCCNTR in AArch32 mode
In the PMUv3, a new AArch32 64-bit (MCRR/MRRC) accessor for the
PMCCNTR was added. In QEMU we forgot to implement this, so only
provide the 32-bit accessor. Since we have a 64-bit PMCCNTR
sysreg for AArch64, adding the 64-bit AArch32 version is easy.
We add the PMCCNTR to the v8_cp_reginfo because PMUv3 was added
in the ARMv8 architecture. This is consistent with how we
handle the existing PMCCNTR support, where we always implement
it for all v7 CPUs. This is arguably something we should
clean up so it is gated on ARM_FEATURE_PMU and/or an ID
register check for the relevant PMU version, but we should
do that as its own tidyup rather than being inconsistent between
this PMCCNTR accessor and the others.
Since the register name is the same as the 32-bit PMCCNTR, we set
ARM_CP_NO_GDB on the 32-bit one to avoid generating an invalid GDB XML.
See
https://developer.arm.com/documentation/ddi0601/2024-06/AArch32-Registers/PMCCNTR--Performance-Monitors-Cycle-Count-Register?lang=en
Note for potential backporting:
* this code in cpregs-pmu.c will be in helper.c on stable
branches that don't have commit ae2086426d37
Cc: [email protected]
Signed-off-by: Alex Richardson <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: a0555e36fc44ea98edf7c50924de8b973cd4267d
https://github.com/qemu/qemu/commit/a0555e36fc44ea98edf7c50924de8b973cd4267d
Author: Zenghui Yu <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm: Remove writes to ICPENDR registers
As per the arm-vgic-v3 kernel doc [1]:
Accesses to GICD_ICPENDR register region and GICR_ICPENDR0 registers
have RAZ/WI semantics, meaning that reads always return 0 and writes
are always ignored.
The state behind these registers (both 0 and 1 bits) is written by
writing to the GICD_ISPENDR and GICR_ISPENDR0 registers, unlike
some of the other set/clear register pairs.
Remove the useless writes to ICPENDR registers in kvm_arm_gicv3_put().
[1] https://docs.kernel.org/virt/kvm/devices/arm-vgic-v3.html
Signed-off-by: Zenghui Yu <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: b10bd4bd17ac8628ede8735a08ad82dc3b721c64
https://github.com/qemu/qemu/commit/b10bd4bd17ac8628ede8735a08ad82dc3b721c64
Author: Zenghui Yu <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M hw/intc/arm_gicv3_kvm.c
Log Message:
-----------
hw/intc/arm_gicv3_kvm: Write all 1's to clear enable/active
KVM's userspace access interface to the GICD enable and active bits
is via set/clear register pairs which implement the hardware's "write
1s to the clear register to clear the 0 bits, and write 1s to the set
register to set the 1 bits" semantics. We didn't get this right,
because we were writing 0 to the clear register.
Writing 0 to GICD_IC{ENABLE,ACTIVE}R architecturally has no effect on
interrupt status (all writes are simply ignored by KVM) and doesn't
comply with the intention of "first write to the clear-reg to clear
all bits".
Write all 1's to actually clear the enable/active status.
This didn't have any adverse effects on migration because there
we start with a clean VM state; it would be guest-visible when
doing a system reset, but since Linux always cleans up the
register state of the GIC during bootup before it enables it
most users won't have run into a problem here.
Cc: [email protected]
Fixes: 367b9f527bec ("hw/intc/arm_gicv3_kvm: Implement get/put functions")
Signed-off-by: Zenghui Yu <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: e7b77e681f8ecf7d9360e47243f7c1a0fb88f51c
https://github.com/qemu/qemu/commit/e7b77e681f8ecf7d9360e47243f7c1a0fb88f51c
Author: Peter Maydell <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M hw/display/framebuffer.c
Log Message:
-----------
hw/display/framebuffer: Add cast to force 64x64 multiply
In framebuffer_update_display(), Coverity complains because we
multiply two values of type 'int' (which will be done as a 32x32
multiply and so in theory might overflow) and then add the result to
a ram_addr_t, which can be 64 bits.
4GB framebuffers are not plausible anyway, but keep Coverity happy
by adding casts which force these multiplies to be done as 64x64.
Coverity: CID 1487248
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-id: [email protected]
Commit: 4f2b82f60431e4792ecfd86a4d6b824248ee4c21
https://github.com/qemu/qemu/commit/4f2b82f60431e4792ecfd86a4d6b824248ee4c21
Author: Peter Maydell <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M target/arm/debug_helper.c
Log Message:
-----------
target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat
In commit 655659a74a we fixed some bugs in the encoding of the
Debug Communications Channel registers, including that we were
incorrectly exposing an AArch32 register at p14, 3, c0, c5, 0.
Unfortunately removing a register is a break of forwards migration
compatibility for TCG, because we will fail the migration if the
source QEMU passes us a cpreg which the destination QEMU does not
have. We don't have a mechanism for saying "it's OK to ignore this
sysreg in the inbound data", so for the 10.1 release reinstate the
incorrect AArch32 register.
(We probably have had other cases in the past of breaking migration
compatibility like this, but we didn't notice because we didn't test
and in any case not that many people care about TCG migration
compatibility. KVM migration compat is not affected because for KVM
we treat the kernel as the source of truth for what system registers
are present.)
Fixes: 655659a74a36b ("target/arm: Correct encoding of Debug Communications
Channel registers")
Reported-by: Fabiano Rosas <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Fabiano Rosas <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Commit: 35cca0f95ff5345f54c11d116efc8940a0dab8aa
https://github.com/qemu/qemu/commit/35cca0f95ff5345f54c11d116efc8940a0dab8aa
Author: Vacha Bhavsar <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M target/arm/gdbstub64.c
Log Message:
-----------
target/arm: Fix big-endian handling of NEON gdb remote debugging
In the code for allowing the gdbstub to set the value of an AArch64
FP/SIMD register, we weren't accounting for target_big_endian()
being true. This meant that for aarch64_be-linux-user we would
set the two halves of the FP register the wrong way around.
The much more common case of a little-endian guest is not affected;
nor are big-endian hosts.
Correct the handling of this case.
Cc: [email protected]
Signed-off-by: Vacha Bhavsar <[email protected]>
Message-id: [email protected]
[PMM: added comment, expanded commit message, fixed missing space]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 97b3d732afec9b165c33697452e31267a845338f
https://github.com/qemu/qemu/commit/97b3d732afec9b165c33697452e31267a845338f
Author: Vacha Bhavsar <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M target/arm/gdbstub64.c
Log Message:
-----------
target/arm: Fix handling of setting SVE registers from gdb
The code to handle setting SVE registers via the gdbstub is broken:
* it sets each pair of elements in the zregs[].d[] array in the
wrong order for the most common (little endian) case: the least
significant 64-bit value comes first
* it makes no attempt to handle target_endian()
* it does a simple copy out of the (target endian) gdbstub buffer
into the (host endan) zregs data structure, which is wrong on
big endian hosts
Fix all these problems:
* use ldq_p() to read from the gdbstub buffer
* check target_big_endian() to see if we need to handle the
128-bit values the opposite way around
Cc: [email protected]
Signed-off-by: Vacha Bhavsar <[email protected]>
Message-id: [email protected]
[PMM: adjusted commit message, fixed spacing]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 676ab6a21117858393a4440e4cdc3d314277cf20
https://github.com/qemu/qemu/commit/676ab6a21117858393a4440e4cdc3d314277cf20
Author: Gustavo Romero <[email protected]>
Date: 2025-08-01 (Fri, 01 Aug 2025)
Changed paths:
M tests/tcg/Makefile.target
M tests/tcg/multiarch/Makefile.target
M tests/tcg/multiarch/system/Makefile.softmmu-target
M tests/tcg/x86_64/Makefile.softmmu-target
Log Message:
-----------
tests/tcg: Fix run for tests with specific plugin
Commit 25aaf0cb7f (“tests/tcg: reduce the number of plugin test
combinations”) added support for running tests with specific plugins
passed via the EXTRA_RUNS variable.
However, due to the optimization, the rules generated as a shuffled
combination of tests and plugins might not cover the rules required to
run the tests with a specific plugin passed via EXTRA_RUNS.
This commit fixes it by correctly generating the rules for the tests
that require a specific plugin to run, which are now passed via the
EXTRA_RUNS_WITH_PLUGIN instead of via the EXTRA_RUNS variable.
The fix essentially excludes the tests passed via EXTRA_RUNS_WITH_PLUGIN
from the rules created by the shuffled combination of tests and plugins,
to avoid running the tests twice, and generates the rules for the
test/plugin combinations listed in the EXTRA_RUNS_WITH_PLUGIN variable.
Signed-off-by: Gustavo Romero <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Tested-by: Pierrick Bouvier <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 7bf9ae8cc2484f83ec77ad475538d78355e424ea
https://github.com/qemu/qemu/commit/7bf9ae8cc2484f83ec77ad475538d78355e424ea
Author: Michael Tokarev <[email protected]>
Date: 2025-08-03 (Sun, 03 Aug 2025)
Changed paths:
M roms/vbootrom
Log Message:
-----------
roms/vbootrom: update to 7b1eb5f7fe6a
Changes:
7b1eb5f ast27x0: Fix Makefile to unconditionally set CC to support correct
cross-compilation
601d410 ast27x0: Fix missing SCU module reset for SSP and TSP initialization
80768e4 ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory
from DTB
f8ab635 ast27x0: Show build date and git version
53294f5 Add initial support for AST27x0
b1c2803 Dynamically detects NPCM8XX UBOOT destination and size.
4f54dfc Automatically search for UBOOT location for NPCM8xx images.
The actual bootroms are not updated yet.
Signed-off-by: Michael Tokarev <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/2a89ad4c8f5665d07952a4f1749caa6ec0cd3d9c.1753654515.git....@tls.msk.ru
[ clg: Update to latest vbootrom ]
Reviewed-by: Jamin Lin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 5ff7ad61c0af08d81dc7fd050c14b944fbeb9c35
https://github.com/qemu/qemu/commit/5ff7ad61c0af08d81dc7fd050c14b944fbeb9c35
Author: Michael Tokarev <[email protected]>
Date: 2025-08-03 (Sun, 03 Aug 2025)
Changed paths:
M roms/Makefile
Log Message:
-----------
roms/Makefile: build ast27x0_bootrom
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3052
Signed-off-by: Michael Tokarev <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/607a943a587248fbe0ff0897de80aee98a093caa.1753654515.git....@tls.msk.ru
[ clg: Removed make CC= workaround ]
Reviewed-by: Jamin Lin <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d63961f957ffaa586b166846f2c6a580923b08f6
https://github.com/qemu/qemu/commit/d63961f957ffaa586b166846f2c6a580923b08f6
Author: Cédric Le Goater <[email protected]>
Date: 2025-08-03 (Sun, 03 Aug 2025)
Changed paths:
M pc-bios/ast27x0_bootrom.bin
M pc-bios/npcm7xx_bootrom.bin
M pc-bios/npcm8xx_bootrom.bin
Log Message:
-----------
pc-bios: Update vbootrom image to commit 183c9ff8056b
Full changelog since last update (1287b6e42e83) :
Hao Wu (2):
Automatically search for UBOOT location for NPCM8xx images.
Dynamically detects NPCM8XX UBOOT destination and size.
Jamin Lin (5):
Add initial support for AST27x0
ast27x0: Show build date and git version
ast27x0: Initialize and enable SSP/TSP using SCU with reserved-memory
from DTB
ast27x0: Fix missing SCU module reset for SSP and TSP initialization
ast27x0: Fix Makefile to unconditionally set CC to support correct
cross-compilation
Compiled with gcc version 13.3.0
Reviewed-by: Jamin Lin <[email protected]>
Reviewed-by: Michael Tokarev <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 13ed972b4ce57198914a37217251d30fbec20e41
https://github.com/qemu/qemu/commit/13ed972b4ce57198914a37217251d30fbec20e41
Author: Jamin Lin <[email protected]>
Date: 2025-08-04 (Mon, 04 Aug 2025)
Changed paths:
M hw/ssi/aspeed_smc.c
Log Message:
-----------
hw/ssi/aspeed_smc: Fix incorrect FMC_WDT2 register read on AST1030
On AST1030, reading the FMC_WDT2 register always returns 0xFFFFFFFF.
This issue is due to the aspeed_smc_read function, which checks for the
ASPEED_SMC_FEATURE_WDT_CONTROL feature. Since AST1030 was missing this
feature flag, the read operation fails and returns -1.
To resolve this, add the WDT_CONTROL feature to AST1030's feature set
so that FMC_WDT2 can be correctly accessed by firmware.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Fixes: 2850df6a81bcdc2e063dfdd56751ee2d11c58030 ("aspeed/smc: Add AST1030
support ")
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a666a84b32690fa414325ab23e50616f91ef00b1
https://github.com/qemu/qemu/commit/a666a84b32690fa414325ab23e50616f91ef00b1
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-08-04 (Mon, 04 Aug 2025)
Changed paths:
M hw/display/framebuffer.c
M hw/intc/arm_gicv3_kvm.c
M target/arm/cpregs-pmu.c
M target/arm/debug_helper.c
M target/arm/gdbstub64.c
M tests/tcg/Makefile.target
M tests/tcg/multiarch/Makefile.target
M tests/tcg/multiarch/system/Makefile.softmmu-target
M tests/tcg/x86_64/Makefile.softmmu-target
Log Message:
-----------
Merge tag 'pull-target-arm-20250801' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Add missing 64-bit PMCCNTR in AArch32 mode
* Reinstate bogus AArch32 DBGDTRTX register for migration compat
* fix big-endian handling of AArch64 FPU registers in gdbstub
* fix handling of setting SVE registers from gdbstub
* hw/intc/arm_gicv3_kvm: fix writing of enable/active/pending state to KVM
* hw/display/framebuffer: Add cast to force 64x64 multiply
* tests/tcg: Fix run for tests with specific plugin
# -----BEGIN PGP SIGNATURE-----
#
# iQJMBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmiM4mgZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3lH/D/iniJpHRVDVAvHcYe7vSgLl
# HHfdEro/lOJJbaktQwOwkSuyl5HFy3YoIg3/5K2kX40DRkeA/M1HWkaWpwpCUReV
# 6XS8fCDmxw5M0oncJsTD1cYxCAAHm/CSt2uvdwgHo6nU+vnEa85ml3Q57phLEkvl
# 2R6xjXDD2FY3Xi6l2Jvqhnx/y60D5YnZVo/G9jcwRI2kIvpwTxukge5rGRTeagzL
# fKwsgr8jThvWyzTJtd88n36uD8xiH8/IfHh+e0kGYfzPRjEGfN3rKh4OlyfRyv7D
# AVI8qgVz0ex7DEjJTCS2nNYmNhO8hTE+cybcsH6AU2e3V7/vqg3Lh0/1cWlmvGnR
# 8L0/RBy0exPI1kRABfjXPV4VtNSuByxp+F+s4LvUrxgnnbv29ldOnQNHn3BZJtZn
# OuuixZNa3/tJFa+2U20fPW+q2H9uhPhvLn5fhtCx1ucYONLMrWl3Z8Q3/qwbW+5e
# FR459UaVHUvqKDGL6cjnaQ3VclrsXngCbeBmLm7fDfniRf/4uIc3q6RzdwY3waj3
# t7D/+GmLwZzajEaCU1NcI+Uz+yO/wJhEXUtWAzm6xeowYfOEeZc1pRgGWSqy4qvi
# L9vKmZtRW5LvwLwpMLdcoB3BOIszSDy7AylX4onSWl3Vp3GYiOhYqv9OKlQoUGtu
# xjFCVDCB/0FPl9b+xoYK
# =lN06
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 01 Aug 2025 11:51:04 EDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>" [full]
# gpg: aka "Peter Maydell <[email protected]>"
[full]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20250801' of https://gitlab.com/pm215/qemu:
tests/tcg: Fix run for tests with specific plugin
target/arm: Fix handling of setting SVE registers from gdb
target/arm: Fix big-endian handling of NEON gdb remote debugging
target/arm: Reinstate bogus AArch32 DBGDTRTX register for migration compat
hw/display/framebuffer: Add cast to force 64x64 multiply
hw/intc/arm_gicv3_kvm: Write all 1's to clear enable/active
hw/intc/arm_gicv3_kvm: Remove writes to ICPENDR registers
target/arm: add support for 64-bit PMCCNTR in AArch32 mode
Signed-off-by: Stefan Hajnoczi <[email protected]>
Commit: a41280fd5b94c49089f7631c6fa8bb9c308b7962
https://github.com/qemu/qemu/commit/a41280fd5b94c49089f7631c6fa8bb9c308b7962
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-08-04 (Mon, 04 Aug 2025)
Changed paths:
M hw/ssi/aspeed_smc.c
M pc-bios/ast27x0_bootrom.bin
M pc-bios/npcm7xx_bootrom.bin
M pc-bios/npcm8xx_bootrom.bin
M roms/Makefile
M roms/vbootrom
Log Message:
-----------
Merge tag 'pull-aspeed-20250804' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Fixed vbootrom build under roms/
* Updated vbootrom image to 183c9ff805
* Fixed SMC model of AST1030 SoC
# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmiQkpMACgkQUaNDx8/7
# 7KFVFw//X8mpLW97oCdh2ZuelkwQh+udAn34/f8cZWu97g9/Dmi6oDNb/GmPy5t2
# lFNg4hCSBh3JcRbHSMLVieE3lZLi5XuRb/g64TSH0gzgfhFKaPsqxzaD51R5cxVF
# JG9JSsGKJdbp1inWZvr1uEZsioAOdUPP4qeD+WLoTHKrhSPCrUHsjslVmReBKu/O
# sbgTGHkI8RJA6knz+j5JzXgy5y7XGsfbkl3pWlI8Ni9l6VDVrgfCcSgGtjQdzF4Q
# J/QtpYYjo6crJ4wbvAPhKP3RZNNl0m60oxn0BSLFzrM3fZ95VP4pGVOrkCKtZLgG
# Q0KvHcDKvm3BsgLPaUeyMjYHKbku2f/U3acsY4VqfLbvLNarmsG8OtFPiEs1tKnu
# Dkqb1Ac85O/8dKohyIFhxEy1nEY4iW4495iDD2CklD2lY1Ck+bFkwC2jBNfpgaO6
# xzfLPpiyyU+GbnXbV5HASHland+5AyIjxEKfYpIcARIsfuDOR0qYPl/wmPkV8utO
# /X0cKHZxSZ0x3E7xiOwTo6ZIgKdYbNEljTRT0AYxChB/ZRIEByQvYnwAXaL9IqLc
# qSc2GRXTy+G8WNy4z1kn2B0Sp9rENvB5uzoRGZ1PtwBySclzUHICQ653a7HKEYeH
# imXU9dGNhkQ+RMdA9+bZ3B3H8ykJDtX27woK6yerlbk3CUT9ZIs=
# =oAuL
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 04 Aug 2025 06:59:31 EDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
# Primary key fingerprint: A0F6 6548 F048 95EB FE6B 0B60 51A3 43C7 CFFB ECA1
* tag 'pull-aspeed-20250804' of https://github.com/legoater/qemu:
hw/ssi/aspeed_smc: Fix incorrect FMC_WDT2 register read on AST1030
pc-bios: Update vbootrom image to commit 183c9ff8056b
roms/Makefile: build ast27x0_bootrom
roms/vbootrom: update to 7b1eb5f7fe6a
Signed-off-by: Stefan Hajnoczi <[email protected]>
Compare: https://github.com/qemu/qemu/compare/e5859141b9b6...a41280fd5b94
To unsubscribe from these emails, change your notification settings at
https://github.com/qemu/qemu/settings/notifications
