Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: e1e2909f8e74051a34a044940f90d4650b6e784a
https://github.com/qemu/qemu/commit/e1e2909f8e74051a34a044940f90d4650b6e784a
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: restrict isapc machine to 32-bit CPUs
The isapc machine represents a legacy ISA PC with a 486 CPU. Whilst it is
possible to specify any CPU via -cpu on the command line, it makes no
sense to allow modern 64-bit CPUs to be used.
Restrict the isapc machine to the available 32-bit CPUs, taking care to
handle the case where if a user inadvertently uses either -cpu max or
-cpu host then the "best" 32-bit CPU is used (in this case the pentium3).
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 483a232e0431f19a4d6596be59c1d51370407249
https://github.com/qemu/qemu/commit/483a232e0431f19a4d6596be59c1d51370407249
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: restrict isapc machine to 3.5G memory
Since the isapc machine is now limited to using 32-bit CPUs, add a hard
restriction
so that the machine cannot be started with more than 3.5G memory. This matches
the
default value for max_ram_below_4g if not specified and provides consistent
behaviour betweem TCG and KVM accelerators.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b55eab382cfbeb11f0afe116a06243d3fe5e43d9
https://github.com/qemu/qemu/commit/b55eab382cfbeb11f0afe116a06243d3fe5e43d9
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove include for loader.h
This header is not required since the loader functionality is handled separately
by pc_memory_init() in pc.c.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 79233a7e600ff26c623aecee81aa9a04cbbc7668
https://github.com/qemu/qemu/commit/79233a7e600ff26c623aecee81aa9a04cbbc7668
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: inline pc_xen_hvm_init_pci() into pc_xen_hvm_init()
This helps to simplify the initialisation of the Xen hvm machine.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 469be2f11f7279fe9174199183cf51ba1f557e2d
https://github.com/qemu/qemu/commit/469be2f11f7279fe9174199183cf51ba1f557e2d
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: duplicate pc_init1() into pc_isa_init()
This is to prepare for splitting the isapc machine into its own separate file.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: ba5500e0385fad2dd1d4878872695023e5e32e92
https://github.com/qemu/qemu/commit/ba5500e0385fad2dd1d4878872695023e5e32e92
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove pcmc->pci_enabled dependent initialisation from
pc_init_isa()
PCI code will never be used for an isapc machine.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: dc58530f0a58fe09862026ab6c26c68c00f4d535
https://github.com/qemu/qemu/commit/dc58530f0a58fe09862026ab6c26c68c00f4d535
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove igvm initialisation from pc_init_isa()
According to the QEMU documentation igvm is only supported for the pc and q35
machines so remove igvm support from the isapc machine.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: ae4199af92d38fffd0d1fb9f02eaeb0632eff6df
https://github.com/qemu/qemu/commit/ae4199af92d38fffd0d1fb9f02eaeb0632eff6df
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove SMI and piix4_pm initialisation from pc_init_isa()
These are based upon the PIIX4 PCI chipset and so can never be used on an isapc
machine.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d7916f6d5ec346d05ef63f5419d97a4d9f7d0a75
https://github.com/qemu/qemu/commit/d7916f6d5ec346d05ef63f5419d97a4d9f7d0a75
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove SGX initialisation from pc_init_isa()
The Intel SGX instructions only exist on recent CPUs and so would never be
available
on a CPU from the pre-PCI era.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 62f8d562bb86cd7e1a0ce06f191c402a1eeba309
https://github.com/qemu/qemu/commit/62f8d562bb86cd7e1a0ce06f191c402a1eeba309
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove nvdimm initialisation from pc_init_isa()
NVDIMMs cannot be used by PCs from a pre-PCI era.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f2096fa151cbdf6cd169a6f0be9c5ccb5cd10466
https://github.com/qemu/qemu/commit/f2096fa151cbdf6cd169a6f0be9c5ccb5cd10466
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: simplify RAM size logic in pc_init_isa()
All isapc machines must have 32-bit CPUs and so the RAM split logic can be
hardcoded
accordingly.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 20fd284ec3c6ec39fb8e062d52f1ee514e89c554
https://github.com/qemu/qemu/commit/20fd284ec3c6ec39fb8e062d52f1ee514e89c554
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: hardcode hole64_size to 0 in pc_init_isa()
All isapc machines must have 32-bit CPUs and have no PCI 64-bit hole so it can
be
hardcoded to 0.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b11ad71e32441baff354cdab1993847b61923570
https://github.com/qemu/qemu/commit/b11ad71e32441baff354cdab1993847b61923570
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove pc_system_flash_cleanup_unused() from pc_init_isa()
This function contains 'assert(PC_MACHINE_GET_CLASS(pcms)->pci_enabled)' and so
we can
safely assume that it should never be used for the isapc machine.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 32c73eb73c7c09290a642c0c3ea541ce00350994
https://github.com/qemu/qemu/commit/32c73eb73c7c09290a642c0c3ea541ce00350994
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: always initialise ISA IDE drives in pc_init_isa()
By definition an isapc machine must always use ISA IDE drives so ensure that
they
are always enabled. At the same time also remove the surrounding CONFIG_IDE_ISA
define since it will be enabled via the ISAPC Kconfig.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 99d0630a454581eeb2bfabdc0bc15cc07d145876
https://github.com/qemu/qemu/commit/99d0630a454581eeb2bfabdc0bc15cc07d145876
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1()
PCI is always enabled on the pc-i440fx machine so hardcode the relevant logic
in pc_init1(). Add an assert() to ensure that this is always the case at
runtime as already done in pc_q35_init().
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 3113e7db1d5d683e91cdbb4796e1b154cdda73bf
https://github.com/qemu/qemu/commit/3113e7db1d5d683e91cdbb4796e1b154cdda73bf
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/Kconfig
A hw/i386/isapc.c
M hw/i386/meson.build
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386: move isapc machine to separate isapc.c file
Now that pc_init_isa() is independent of any PCI initialisation, move it into a
separate isapc.c file including the ISA IDE variables which are now no longer
needed for the pc-i440fx machine. This enables us to finally fix the dependency
of ISAPC on I440FX in hw/i386/Kconfig.
Note that as part of the move to a separate file we can see that the licence
text
is a verbatim copy of the MIT licence. The text originates from commit
1df912cf9e
("VL license of the day is MIT/BSD") so we can be sure that this was the
original
intent. As a consequence we can update the file header to use a SPDX tag as per
the current project contribution guidelines.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Bernhard Beschow <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d773f9689109eb00ba6627c2264af949c66897fb
https://github.com/qemu/qemu/commit/d773f9689109eb00ba6627c2264af949c66897fb
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: remove unused headers after isapc machine split
The headers for isapc-only devices can be removed from pc_piix.c since they are
no longer used by the i440fx-pc machine.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 523a64f388a689a1e9bc593ca8768fe1449613db
https://github.com/qemu/qemu/commit/523a64f388a689a1e9bc593ca8768fe1449613db
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/pc_piix.c
Log Message:
-----------
hw/i386/pc_piix.c: replace rom_memory with pci_memory
Now that we can guarantee the i440fx-pc machine will always have a PCI bus, any
instances of rom_memory can be replaced by pci_memory and rom_memory removed
completely.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d8701867d12241f53f3b17973e7fd533c764c76a
https://github.com/qemu/qemu/commit/d8701867d12241f53f3b17973e7fd533c764c76a
Author: Mark Cave-Ayland <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/i386/isapc.c
Log Message:
-----------
hw/i386/isapc.c: replace rom_memory with system_memory
Now that we can guarantee the isapc machine will never have a PCI bus, any
instances of rom_memory can be replaced by system_memory and rom_memory
removed completely.
Signed-off-by: Mark Cave-Ayland <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b8217bbaf2bafef1a4f54082a3548613eeef8f2b
https://github.com/qemu/qemu/commit/b8217bbaf2bafef1a4f54082a3548613eeef8f2b
Author: Paolo Bonzini <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/user-exec.c
M include/hw/core/cpu.h
Log Message:
-----------
user-exec: ensure interrupt_request is not used
cpu_interrupt() is not called anymore except by ARM but even there
it is dead code; disentangling the various cpregs accessors from user-mode
emulation is a work in progress.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 87511341c30d8c9c77178db16491a0ccacc5d64b
https://github.com/qemu/qemu/commit/87511341c30d8c9c77178db16491a0ccacc5d64b
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops.c
M hw/intc/s390_flic.c
M hw/openrisc/cputimer.c
M include/hw/core/cpu.h
M system/cpus.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/hvf/hvf.c
M target/i386/hvf/x86hvf.c
M target/i386/kvm/kvm.c
M target/i386/nvmm/nvmm-all.c
M target/i386/tcg/system/seg_helper.c
M target/i386/tcg/system/svm_helper.c
M target/i386/whpx/whpx-all.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/mips/kvm.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/ppc/kvm.c
M target/rx/cpu.c
M target/rx/helper.c
M target/s390x/cpu-system.c
M target/sh4/cpu.c
M target/sh4/helper.c
M target/sparc/cpu.c
M target/sparc/int64_helper.c
Log Message:
-----------
add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide
The helpers form load-acquire/store-release pair and ensure
that appropriate barriers are in place in case checks happen
outside of BQL.
Use them to replace open-coded checkers/setters across the code,
to make sure that barriers are not missed. Helpers also make code a
bit more readable.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Reviewed-by: Jason J. Herne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 73c520b088878682e2d3b7fa19a6366ec8d39829
https://github.com/qemu/qemu/commit/73c520b088878682e2d3b7fa19a6366ec8d39829
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M include/system/memory.h
M system/memory.c
M system/physmem.c
Log Message:
-----------
memory: reintroduce BQL-free fine-grained PIO/MMIO
This patch brings back Jan's idea [1] of BQL-free IO access
This will let us make access to ACPI PM/HPET timers cheaper,
and prevent BQL contention in case of workload that heavily
uses the timers with a lot of vCPUs.
1) 196ea13104f (memory: Add global-locking property to memory regions)
... de7ea885c539 (kvm: Switch to unlocked MMIO)
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4ae5e2b2bf65452538511a2895d7a4e2115058a5
https://github.com/qemu/qemu/commit/4ae5e2b2bf65452538511a2895d7a4e2115058a5
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/acpi/core.c
Log Message:
-----------
acpi: mark PMTIMER as unlocked
Reading QEMU_CLOCK_VIRTUAL is thread-safe, write access is NOP.
This makes possible to boot Windows with large vCPUs count when
hv-time is not used.
Reproducer:
-M q35,hpet=off -cpu host -enable-kvm -smp 240,sockets=4 -m 8G WS2025.img
fails to boot within 30min.
With this fix it boots within 2-1min.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7defb58bafac8dcb23c06be5e4f2d1a33d8392fd
https://github.com/qemu/qemu/commit/7defb58bafac8dcb23c06be5e4f2d1a33d8392fd
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/timer/hpet.c
Log Message:
-----------
hpet: switch to fine-grained device locking
as a step towards lock-less HPET counter read,
use per device locking instead of BQL.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a453bf0354412592362139bdf4df0d4900ec0686
https://github.com/qemu/qemu/commit/a453bf0354412592362139bdf4df0d4900ec0686
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/timer/hpet.c
Log Message:
-----------
hpet: move out main counter read into a separate block
Follow up patche will switch main counter read to
lock-less mode. As preparation for that move relevant
branch into a separate top level block to make followup
patch cleaner/simplier by reducing contextual noise
when lock-less read is introduced.
no functional changes.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 20c2345290f34aac434284cf9a242c7904d39a27
https://github.com/qemu/qemu/commit/20c2345290f34aac434284cf9a242c7904d39a27
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M hw/timer/hpet.c
Log Message:
-----------
hpet: make main counter read lock-less
Make access to main HPET counter lock-less.
In unlikely event of an update in progress, readers will busy wait
untill update is finished.
As result micro benchmark of concurrent reading of HPET counter
with large number of vCPU shows over 80% better (less) latency.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 17e645c6f17999cd0306c4d18d6f6cb3db55756d
https://github.com/qemu/qemu/commit/17e645c6f17999cd0306c4d18d6f6cb3db55756d
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
kvm: i386: irqchip: take BQL only if there is an interrupt
when kernel-irqchip=split is used, QEMU still hits BQL
contention issue when reading ACPI PM/HPET timers
(despite of timer[s] access being lock-less).
So Windows with more than 255 cpus is still not able to
boot (since it requires iommu -> split irqchip).
Problematic path is in kvm_arch_pre_run() where BQL is taken
unconditionally when split irqchip is in use.
There are a few parts that BQL protects there:
1. interrupt check and injecting
however we do not take BQL when checking for pending
interrupt (even within the same function), so the patch
takes the same approach for cpu->interrupt_request checks
and takes BQL only if there is a job to do.
2. request_interrupt_window access
CPUState::kvm_run::request_interrupt_window doesn't need BQL
as it's accessed by its own vCPU thread.
3. cr8/cpu_get_apic_tpr access
the same (as #2) applies to CPUState::kvm_run::cr8,
and APIC registers are also cached/synced (get/put) within
the vCPU thread it belongs to.
Taking BQL only when is necessary, eleminates BQL bottleneck on
IO/MMIO only exit path, improoving latency by 80% on HPET micro
benchmark.
This lets Windows to boot succesfully (in case hv-time isn't used)
when more than 255 vCPUs are in use.
Signed-off-by: Igor Mammedov <[email protected]>
Reviewed-by: Peter Xu <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 83bd8e65bc70cef03a207df315004f8b1301dc53
https://github.com/qemu/qemu/commit/83bd8e65bc70cef03a207df315004f8b1301dc53
Author: Igor Mammedov <[email protected]>
Date: 2025-08-29 (Fri, 29 Aug 2025)
Changed paths:
M accel/tcg/cpu-exec.c
Log Message:
-----------
tcg: move interrupt caching and single step masking closer to user
in cpu_handle_interrupt() the only place where cached interrupt_request
might have effect is when CPU_INTERRUPT_SSTEP_MASK applied and
cached interrupt_request handed over to cpu_exec_interrupt() and
need_replay_interrupt().
Simplify code by moving interrupt_request caching and CPU_INTERRUPT_SSTEP_MASK
masking into the block where it actually matters and drop reloading cached value
from CPUState:interrupt_request as the rest of the code directly uses
CPUState:interrupt_request.
Signed-off-by: Igor Mammedov <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 91589bcd9fee0e66b241d04e5f37cd4f218187a2
https://github.com/qemu/qemu/commit/91589bcd9fee0e66b241d04e5f37cd4f218187a2
Author: Richard Henderson <[email protected]>
Date: 2025-08-31 (Sun, 31 Aug 2025)
Changed paths:
M accel/tcg/cpu-exec.c
M accel/tcg/tcg-accel-ops.c
M accel/tcg/user-exec.c
M hw/acpi/core.c
M hw/i386/Kconfig
A hw/i386/isapc.c
M hw/i386/meson.build
M hw/i386/pc_piix.c
M hw/intc/s390_flic.c
M hw/openrisc/cputimer.c
M hw/timer/hpet.c
M include/hw/core/cpu.h
M include/system/memory.h
M system/cpus.c
M system/memory.c
M system/physmem.c
M target/alpha/cpu.c
M target/arm/cpu.c
M target/arm/helper.c
M target/arm/hvf/hvf.c
M target/avr/cpu.c
M target/hppa/cpu.c
M target/i386/hvf/hvf.c
M target/i386/hvf/x86hvf.c
M target/i386/kvm/kvm.c
M target/i386/nvmm/nvmm-all.c
M target/i386/tcg/system/seg_helper.c
M target/i386/tcg/system/svm_helper.c
M target/i386/whpx/whpx-all.c
M target/loongarch/cpu.c
M target/m68k/cpu.c
M target/microblaze/cpu.c
M target/mips/cpu.c
M target/mips/kvm.c
M target/openrisc/cpu.c
M target/ppc/cpu_init.c
M target/ppc/kvm.c
M target/rx/cpu.c
M target/rx/helper.c
M target/s390x/cpu-system.c
M target/sh4/cpu.c
M target/sh4/helper.c
M target/sparc/cpu.c
M target/sparc/int64_helper.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* hw/i386: split isapc from PCI boards
* cpu-exec, accel: remove BQL usage for interrupt_request != 0
* memory, hpet, pmtimer: introduce BQL-free PIO/MMIO
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# gpg: Signature made Fri 29 Aug 2025 09:03:10 PM AEST
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [unknown]
# gpg: aka "Paolo Bonzini <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (28 commits)
tcg: move interrupt caching and single step masking closer to user
kvm: i386: irqchip: take BQL only if there is an interrupt
hpet: make main counter read lock-less
hpet: move out main counter read into a separate block
hpet: switch to fine-grained device locking
acpi: mark PMTIMER as unlocked
memory: reintroduce BQL-free fine-grained PIO/MMIO
add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide
user-exec: ensure interrupt_request is not used
hw/i386/isapc.c: replace rom_memory with system_memory
hw/i386/pc_piix.c: replace rom_memory with pci_memory
hw/i386/pc_piix.c: remove unused headers after isapc machine split
hw/i386: move isapc machine to separate isapc.c file
hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1()
hw/i386/pc_piix.c: always initialise ISA IDE drives in pc_init_isa()
hw/i386/pc_piix.c: remove pc_system_flash_cleanup_unused() from pc_init_isa()
hw/i386/pc_piix.c: hardcode hole64_size to 0 in pc_init_isa()
hw/i386/pc_piix.c: simplify RAM size logic in pc_init_isa()
hw/i386/pc_piix.c: remove nvdimm initialisation from pc_init_isa()
hw/i386/pc_piix.c: remove SGX initialisation from pc_init_isa()
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/e101d3379253...91589bcd9fee
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