Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 98ee172538abdc1ac42d094bc8859765e5f8a79b
https://github.com/qemu/qemu/commit/98ee172538abdc1ac42d094bc8859765e5f8a79b
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_core.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_xscom.h
Log Message:
-----------
ppc/pnv: Introduce Pnv11Chip
Implement Pnv11Chip, currently without chiptod, xive and phb.
Chiptod, XIVE, PHB are implemented in later patches.
Since Power11 core is same as Power10, the implementation of Pnv11Chip
is a duplicate of corresponding Pnv10Chip.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 73a911e966acd8314e39a4ce4bc58e2254e68324
https://github.com/qemu/qemu/commit/73a911e966acd8314e39a4ce4bc58e2254e68324
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M docs/system/ppc/powernv.rst
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Introduce Power11 PowerNV machine
The Powernv11 machine doesn't have XIVE & PHBs as of now
XIVE2 interface and PHB5 added in later patches to Powernv11 machine
Also add mention of Power11 to powernv documentation
Note: A difference from P10's and P11's machine_class_init is, in P11
different number of PHBs cannot be used on the command line, ie. the
following line does NOT exist in pnv_machine_power11_class_init, which
existed in case of Power10:
machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB);
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 849a6bb854b48d757fab5e408f6a17dff568ec13
https://github.com/qemu/qemu/commit/849a6bb854b48d757fab5e408f6a17dff568ec13
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/pnv_xive2.c
M hw/ppc/pnv.c
M include/hw/ppc/pnv_chip.h
Log Message:
-----------
ppc/pnv: Add PnvChipClass handler to get reference to interrupt controller
Existing code in XIVE2 assumes the chip to be a Power10 Chip.
Instead add a handler to get reference to the interrupt controller (XIVE)
for a given Power Chip.
Signed-off-by: Aditya Gupta <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 0dcbc88865432504dc452d9ded8218dff3bdf0d2
https://github.com/qemu/qemu/commit/0dcbc88865432504dc452d9ded8218dff3bdf0d2
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/pnv.c
M include/hw/ppc/pnv.h
Log Message:
-----------
ppc/pnv: Add XIVE2 controller to Power11
Add a XIVE2 controller to Power11 chip and machine.
The controller has the same logic as Power10.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 91a1cc6a2ce72aefbc9084ce245b562c1d21e082
https://github.com/qemu/qemu/commit/91a1cc6a2ce72aefbc9084ce245b562c1d21e082
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/pnv.c
Log Message:
-----------
ppc/pnv: Add PHB5 PCIe Host bridge to Power11
Power11 also uses PHB5, same as Power10.
Add Power11 PHBs with similar code as the corresponding Power10 implementation.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 46835d806aaacc6c89d7eaf961e21e550d0222f5
https://github.com/qemu/qemu/commit/46835d806aaacc6c89d7eaf961e21e550d0222f5
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/pnv.c
M hw/ppc/pnv_chiptod.c
M include/hw/ppc/pnv_chiptod.h
Log Message:
-----------
ppc/pnv: Add ChipTOD model for Power11
Introduce Power11 ChipTod. The code has been copied from Power10 ChipTod
code as the Power11 core is same as Power10 core.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 968f1af16aa8da8927eb167e57b224dc58f67637
https://github.com/qemu/qemu/commit/968f1af16aa8da8927eb167e57b224dc58f67637
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M tests/functional/ppc64/test_powernv.py
Log Message:
-----------
tests/powernv: Switch to buildroot images instead of op-build
As op-build images haven't been updated from long time (and may not get
updated in future), use buildroot images provided by cedric [1].
Use existing nvme device being used in the test to mount the initrd.
Also replace the check for "zImage loaded message" to skiboot's message
when it starts the kernel: "Starting kernel at", since we are no longer
using zImage from op-build
This is required for newer processor tests such as Power11, as the
op-build kernel image is old and doesn't support Power11.
Power11 test has been added in a later patch.
[1]:
https://github.com/legoater/qemu-ppc-boot/tree/main/buildroot/qemu_ppc64le_powernv8-2025.02
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 5f810b912eea7d91c55927a1bde94f61d7c9e8a0
https://github.com/qemu/qemu/commit/5f810b912eea7d91c55927a1bde94f61d7c9e8a0
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M tests/functional/ppc64/test_powernv.py
Log Message:
-----------
tests/powernv: Add PowerNV test for Power11
With all Power11 support in place, add Power11 PowerNV test.
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Amit Machhiwal <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 556d19fdcb1a07afc05bde7b38cfd2a1f4a89552
https://github.com/qemu/qemu/commit/556d19fdcb1a07afc05bde7b38cfd2a1f4a89552
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/cpu-models.h
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: IBM PPE42 general regs and flags
Introduces general IBM PPE42 processor register definitions
and flags.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 0af45e550b50f1c41164e5c0440654319942707e
https://github.com/qemu/qemu/commit/0af45e550b50f1c41164e5c0440654319942707e
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu_init.c
M target/ppc/helper_regs.c
M target/ppc/translate.c
Log Message:
-----------
target/ppc: Add IBM PPE42 family of processors
Adds the IBM PPE42 family of 32-bit processors supporting
the PPE42, PPE42X and PPE42XM processor versions. These
processors are used as embedded processors in the IBM
Power9, Power10 and Power12 processors for various
tasks. It is basically a stripped down version of the
IBM PowerPC 405 processor, with some added instructions
for handling 64-bit loads and stores.
For more information on the PPE 42 processor please visit:
https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf
Supports PPE42 SPR's (Including the MSR).
Does not yet support exceptions, new PPE42 instructions and
does not prevent access to some invalid instructions and
registers (currently allows access to invalid GPR's and CR
fields).
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 27eee49e6e3cecf69ab02f84fc2d9e19ef8bd3e2
https://github.com/qemu/qemu/commit/27eee49e6e3cecf69ab02f84fc2d9e19ef8bd3e2
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/cpu.h
Log Message:
-----------
target/ppc: IBM PPE42 exception flags and regs
Introduces flags and register definitions needed
for the IBM PPE42 exception model.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 7928680e0aaf0c755ce97800791bf73185749a88
https://github.com/qemu/qemu/commit/7928680e0aaf0c755ce97800791bf73185749a88
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/tcg-excp_helper.c
Log Message:
-----------
target/ppc: Add IBM PPE42 exception model
Add support for the IBM PPE42 exception model including
new exception vectors, exception priorities and setting
of PPE42 SPRs for determining the cause of an exception.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 880aa4cb06ff5e86b6feab3030e14a16fea1dced
https://github.com/qemu/qemu/commit/880aa4cb06ff5e86b6feab3030e14a16fea1dced
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/helper_regs.c
Log Message:
-----------
target/ppc: Support for IBM PPE42 MMU
The IBM PPE42 processor only supports real mode
addressing and does not distinguish between
problem and supervisor states. It also uses
the IR and DR MSR bits for other purposes.
Therefore, add a check for PPE42 when we update
hflags and cause it to ignore the IR and DR bits
when calculating MMU indexes.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: f7ec91c23906ca364650e95f2a28e0ef6c411386
https://github.com/qemu/qemu/commit/f7ec91c23906ca364650e95f2a28e0ef6c411386
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate.c
A target/ppc/translate/ppe-impl.c.inc
Log Message:
-----------
target/ppc: Add IBM PPE42 special instructions
Adds the following instructions exclusively for
IBM PPE42 processors:
LSKU
LCXU
STSKU
STCXU
LVD
LVDU
LVDX
STVD
STVDU
STVDX
SLVD
SRVD
CMPWBC
CMPLWBC
CMPWIBC
BNBWI
BNBW
CLRBWIBC
CLRWBC
DCBQ
RLDICL
RLDICR
RLDIMI
A PPE42 GCC compiler is available here:
https://github.com/open-power/ppe42-gcc
For more information on the PPE42 processors please visit:
https://wiki.raptorcs.com/w/images/a/a3/PPE_42X_Core_Users_Manual.pdf
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 7197f6f7baf29fd76486920e5603e43b25880d3b
https://github.com/qemu/qemu/commit/7197f6f7baf29fd76486920e5603e43b25880d3b
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/ppc_booke.c
M include/hw/ppc/ppc.h
Log Message:
-----------
hw/ppc: Support for an IBM PPE42 CPU decrementer
The IBM PPE42 processors support a 32-bit decrementer
that can raise an external interrupt when DEC[0]
transitions from a 0 to a -1 (a non-negative value to a
negative value). It also continues decrementing
even after this condition is met.
The BookE timer is slightly different in that it
raises an interrupt when the DEC value reaches 0
and stops decrementing at that point.
Support a PPE42 version of the BookE timer by
adding a new PPC_TIMER_PPE flag that has the timer
code look for the transition from a non-negative value
to a negative value and allows the value to
continue decrementing.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 0ad5b8d9c8fdaa21c8384404d53fc2d86842beba
https://github.com/qemu/qemu/commit/0ad5b8d9c8fdaa21c8384404d53fc2d86842beba
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M MAINTAINERS
M hw/ppc/Kconfig
M hw/ppc/meson.build
A hw/ppc/ppe42_machine.c
Log Message:
-----------
hw/ppc: Add a test machine for the IBM PPE42 CPU
Adds a test machine for the IBM PPE42 processor, including a
DEC, FIT, WDT and 512 KiB of ram.
The purpose of this machine is only to provide a generic platform
for testing instructions of the recently added PPE42 processor
model which is used extensively in the IBM Power9, Power10 and
future Power server processors.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: fd93e521b01a5416bb7f106ac29d755bc3059aaa
https://github.com/qemu/qemu/commit/fd93e521b01a5416bb7f106ac29d755bc3059aaa
Author: Glenn Miles <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M MAINTAINERS
M tests/functional/ppc/meson.build
A tests/functional/ppc/test_ppe42.py
Log Message:
-----------
tests/functional: Add test for IBM PPE42 instructions
Adds a functional test for the IBM PPE42 instructions which
downloads a test image from a public github repo and then
loads and executes the image.
(see https://github.com/milesg-github/ppe42-tests for details)
Test status is checked by periodically issuing 'info register'
commands and checking the NIP value. If the NIP is 0xFFF80200
then the test successfully executed to completion. If the
machine stops before the test completes or if a 90 second
timeout is reached, then the test is marked as having failed.
This test does not test any PowerPC instructions as it is
expected that these instructions are well covered in other
tests. Only instructions that are unique to the IBM PPE42
processor are tested.
Signed-off-by: Glenn Miles <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Tested-by: Cédric Le Goater <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: f5738aedc21790bd07dbead6b6272a605d5c1138
https://github.com/qemu/qemu/commit/f5738aedc21790bd07dbead6b6272a605d5c1138
Author: Fabian Vogt <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/xics.c
Log Message:
-----------
hw/intc/xics: Add missing call to register vmstate_icp_server
An obsolete wrapper function with a workaround was removed entirely,
without restoring the call it wrapped.
Without this, the guest is stuck after savevm/loadvm.
Fixes: 24ee9229fe31 ("ppc/spapr: remove deprecated machine pseries-2.9")
Signed-off-by: Fabian Vogt <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link: https://lore.kernel.org/qemu-devel/6187781.lOV4Wx5bFT@fvogt-thinkpad
Signed-off-by: Fabiano Rosas <[email protected]>
Reviewed-by: Gautam Menghani <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 6285eebd3a5fea018eb51d696b51079f44dd1eb3
https://github.com/qemu/qemu/commit/6285eebd3a5fea018eb51d696b51079f44dd1eb3
Author: Harsh Prateek Bora <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/ppc/spapr.c
Log Message:
-----------
ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided
lrdr-capacity contains phys field which communicates the maximum address
in bytes and therefore, the most memory that can be allocated to this
partition. This is usually populated when maxmem is provided alongwith
memory size on qemu command line. However since maxmem is an optional
param, this leads to bits being set to 0 in absence of maxmem param.
Fix this by initializing the respective bits as per total mem size in
such case.
Reported-by: Gaurav Batra <[email protected]>
Tested-by: David Christensen <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Reviewed-by: Shivaprasad G Bhat <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 936a0f208833083fc4f4f8aebfe0f63751d2b7d6
https://github.com/qemu/qemu/commit/936a0f208833083fc4f4f8aebfe0f63751d2b7d6
Author: Gautam Menghani <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M hw/intc/xive2.c
Log Message:
-----------
ppc/xive2: Fix integer overflow warning in xive2_redistribute()
Coverity reported an integer overflow warning in xive2_redistribute()
where the code does a left shift operation "0xffffffff << crowd". Fix the
warning by using a 64 byte integer type. Also refactor the calculation
into dedicated routines.
Resolves: Coverity CID 1612608
Fixes: 555e446019f5 ("ppc/xive2: Support redistribution of group interrupts")
Reviewed-by: Glenn Miles <[email protected]>
Signed-off-by: Gautam Menghani <[email protected]>
Reviewed-by: Amit Machhiwal <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: f291e329e20e1ab4aafdde38533cadc11f2cf5a4
https://github.com/qemu/qemu/commit/f291e329e20e1ab4aafdde38533cadc11f2cf5a4
Author: Chinmay Rath <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Move floating-point rounding and conversion instructions to
decodetree.
Move below instructions to decodetree specification :
fr{sp, in, iz, im}[s][.],
fcti{w, d}[u, z, uz][s][.],
fcfid[s, u, us][s][.] : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: f22aae5d8a2d8de807d6fa77a1901f815207c627
https://github.com/qemu/qemu/commit/f22aae5d8a2d8de807d6fa77a1901f815207c627
Author: Chinmay Rath <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Move floating-point compare instructions to decodetree.
Move below instructions to decodetree specification :
fcmp{u, o} : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 5c89a201a92f49c8946727f451014ec05587645b
https://github.com/qemu/qemu/commit/5c89a201a92f49c8946727f451014ec05587645b
Author: Chinmay Rath <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Move floating-point move instructions to decodetree.
Move below instructions to decodetree specification:
f{mr, neg, abs, nabs} : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 241f6f7994a3b448d9471e43d8e31ed6245b47c7
https://github.com/qemu/qemu/commit/241f6f7994a3b448d9471e43d8e31ed6245b47c7
Author: Chinmay Rath <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/insn32.decode
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
Log Message:
-----------
target/ppc: Move remaining floating-point move instructions to decodetree.
Move below instructions to decodetree specification:
fcpsgn, fmrg{e, o}w : X-form
The changes were verified by validating that the tcg ops generated by
those instructions remain the same, which were captured with the '-d
in_asm,op' flag.
Signed-off-by: Chinmay Rath <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: f19052110e32afd94f897ef069735bbd7172a800
https://github.com/qemu/qemu/commit/f19052110e32afd94f897ef069735bbd7172a800
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/cpu-models.c
M target/ppc/cpu_init.c
Log Message:
-----------
target/ppc: Introduce macro for deprecating PowerPC CPUs
QEMU has a way to deprecate CPUs by setting the 'deprecation_note' in
CPUClass.
Currently PowerPC CPUs don't use this deprecation process.
Introduce 'POWERPC_DEPRECATED_CPU' macro to deprecate particular PowerPC
CPUs in future.
With the change, QEMU will print a warning like below when the
deprecated CPU/Chips are used (example output if power8nvl is deprecated):
$ ./build/qemu-system-ppc64 -M powernv8 --cpu power8nvl -nographic
qemu-system-ppc64: warning: CPU model power8nvl_v1.0-powerpc64-cpu is
deprecated -- CPU is unmaintained.
...
Also, print '(deprecated)' for deprecated CPUs in 'qemu-system-ppc64
--cpu ?' (example output if power8nvl is deprecated):
$ ./build/qemu-system-ppc64 --cpu help
...
power8e (alias for power8e_v2.1)
power8nvl_v1.0 PVR 004c0100 (deprecated)
power8nvl (alias for power8nvl_v1.0)
power8_v2.0 PVR 004d0200
...
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Anushree Mathur <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 264a604e71636bd04bfbbe3cf887259f246dccb3
https://github.com/qemu/qemu/commit/264a604e71636bd04bfbbe3cf887259f246dccb3
Author: Aditya Gupta <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M docs/about/deprecated.rst
M target/ppc/cpu-models.c
Log Message:
-----------
target/ppc: Deprecate Power8E and Power8NVL
Power8E and Power8NVL variants are not of much use in QEMU now, and not
being maintained either.
Power8NVL CPU doesn't boot since skiboot v7.0, or following skiboot commit
to be exact:
commit c5424f683ee3 ("Remove support for POWER8 DD1")
Deprecate the 8E and 8NVL variants.
Suggested-by: Cédric Le Goater <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Signed-off-by: Aditya Gupta <[email protected]>
Tested-by: Anushree Mathur <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 6c51df580d2a64b4e1ef7bdbffeb3615ffe25d43
https://github.com/qemu/qemu/commit/6c51df580d2a64b4e1ef7bdbffeb3615ffe25d43
Author: Denis Sergeev <[email protected]>
Date: 2025-09-28 (Sun, 28 Sep 2025)
Changed paths:
M target/ppc/translate/fp-impl.c.inc
Log Message:
-----------
target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask
In gen_mcrfs() the FPSCR nibble mask is computed as:
`~((0xF << shift) & FP_EX_CLEAR_BITS)`
Here, 0xF is of type int, so the left shift is performed in
32-bit signed arithmetic. For bfa=0 we get shift=28,
and (0xF << 28) = 0xF0000000, which is not representable as a 32-bit
signed int. Static analyzers flag this as a potential integer
overflow.
Found by Linux Verification Center (linuxtesting.org) with SVACE.
Signed-off-by: Denis Sergeev <[email protected]>
Reviewed-by: Chinmay Rath <[email protected]>
Signed-off-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Message-ID: <[email protected]>
Commit: 9b16edec6e9a483469c789475b2065d26b52db35
https://github.com/qemu/qemu/commit/9b16edec6e9a483469c789475b2065d26b52db35
Author: Richard Henderson <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M MAINTAINERS
M docs/about/deprecated.rst
M docs/system/ppc/powernv.rst
M hw/intc/pnv_xive2.c
M hw/intc/xics.c
M hw/intc/xive2.c
M hw/ppc/Kconfig
M hw/ppc/meson.build
M hw/ppc/pnv.c
M hw/ppc/pnv_chiptod.c
M hw/ppc/pnv_core.c
M hw/ppc/ppc_booke.c
A hw/ppc/ppe42_machine.c
M hw/ppc/spapr.c
M include/hw/ppc/pnv.h
M include/hw/ppc/pnv_chip.h
M include/hw/ppc/pnv_chiptod.h
M include/hw/ppc/pnv_xscom.h
M include/hw/ppc/ppc.h
M target/ppc/cpu-models.c
M target/ppc/cpu-models.h
M target/ppc/cpu.h
M target/ppc/cpu_init.c
M target/ppc/excp_helper.c
M target/ppc/fpu_helper.c
M target/ppc/helper.h
M target/ppc/helper_regs.c
M target/ppc/insn32.decode
M target/ppc/tcg-excp_helper.c
M target/ppc/translate.c
M target/ppc/translate/fp-impl.c.inc
M target/ppc/translate/fp-ops.c.inc
A target/ppc/translate/ppe-impl.c.inc
M tests/functional/ppc/meson.build
A tests/functional/ppc/test_ppe42.py
M tests/functional/ppc64/test_powernv.py
Log Message:
-----------
Merge tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu
into staging
ppc queue for 20250928
* Support for PowerNV11 and PPE42 CPU/Machines.
* Deprecation of Power8E and Power8NVL
* Decodetree patches for some floating-point instructions
* Minor bug fixes, improvements in ppc/spapr/xive/xics.
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# gpg: Signature made Sun 28 Sep 2025 11:42:12 AM PDT
# gpg: using RSA key 6B810CD6D2BE10F3883D21424544E994F9D68FBB
# gpg: Good signature from "Harsh Prateek Bora <[email protected]>"
[undefined]
# gpg: aka "Harsh Prateek Bora <[email protected]>"
[undefined]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6B81 0CD6 D2BE 10F3 883D 2142 4544 E994 F9D6 8FBB
* tag 'pull-ppc-for-20250928-20250929' of https://gitlab.com/harshpb/qemu: (27
commits)
target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask
target/ppc: Deprecate Power8E and Power8NVL
target/ppc: Introduce macro for deprecating PowerPC CPUs
target/ppc: Move remaining floating-point move instructions to decodetree.
target/ppc: Move floating-point move instructions to decodetree.
target/ppc: Move floating-point compare instructions to decodetree.
target/ppc: Move floating-point rounding and conversion instructions to
decodetree.
ppc/xive2: Fix integer overflow warning in xive2_redistribute()
ppc/spapr: init lrdr-capapcity phys with ram size if maxmem not provided
hw/intc/xics: Add missing call to register vmstate_icp_server
tests/functional: Add test for IBM PPE42 instructions
hw/ppc: Add a test machine for the IBM PPE42 CPU
hw/ppc: Support for an IBM PPE42 CPU decrementer
target/ppc: Add IBM PPE42 special instructions
target/ppc: Support for IBM PPE42 MMU
target/ppc: Add IBM PPE42 exception model
target/ppc: IBM PPE42 exception flags and regs
target/ppc: Add IBM PPE42 family of processors
target/ppc: IBM PPE42 general regs and flags
tests/powernv: Add PowerNV test for Power11
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/4975b64efb5a...9b16edec6e9a
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