Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: faccaa34f0cb75b93ff1f4bcdd2f40f23f6aa10f
https://github.com/qemu/qemu/commit/faccaa34f0cb75b93ff1f4bcdd2f40f23f6aa10f
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M subprojects/.gitignore
Log Message:
-----------
subprojects: Remove version number from .gitignore
Get rid of all the version numbers, and use wildcard matches instead,
because peopl will repeatedly forgot to change these versions.
Suggested-by: Manos Pitsidianakis <[email protected]>
Suggested-by: Daniel P. Berrangé <[email protected]>
Suggested-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4c18783a88726c3fc39cea9117b720adb82e557f
https://github.com/qemu/qemu/commit/4c18783a88726c3fc39cea9117b720adb82e557f
Author: Marc-André Lureau <[email protected]>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M rust/meson.build
M scripts/archive-source.sh
M subprojects/.gitignore
A subprojects/glib-sys-0.21-rs.wrap
A subprojects/packagefiles/glib-sys-0.21-rs/meson.build
Log Message:
-----------
subprojects: add glib-sys-rs
Signed-off-by: Marc-André Lureau <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 9c40c1ff970d7ec3d4456aeb65245d66e1226118
https://github.com/qemu/qemu/commit/9c40c1ff970d7ec3d4456aeb65245d66e1226118
Author: Marc-André Lureau <[email protected]>
Date: 2025-10-03 (Fri, 03 Oct 2025)
Changed paths:
M include/hw/core/cpu.h
M meson.build
M rust/Cargo.lock
M rust/Cargo.toml
M rust/bql/Cargo.toml
M rust/bql/meson.build
M rust/bql/src/bindings.rs
M rust/chardev/Cargo.toml
M rust/chardev/meson.build
M rust/chardev/src/bindings.rs
M rust/hw/char/pl011/Cargo.toml
M rust/hw/char/pl011/meson.build
M rust/hw/char/pl011/src/bindings.rs
M rust/hw/core/Cargo.toml
M rust/hw/core/meson.build
M rust/hw/core/src/bindings.rs
M rust/migration/Cargo.toml
M rust/migration/meson.build
M rust/migration/src/bindings.rs
M rust/qom/Cargo.toml
M rust/qom/meson.build
M rust/qom/src/bindings.rs
M rust/system/Cargo.toml
M rust/system/meson.build
M rust/system/src/bindings.rs
M rust/util/Cargo.toml
M rust/util/meson.build
M rust/util/src/bindings.rs
Log Message:
-----------
rust: use glib-sys
Don't generate FFI for glib, rely on glib-sys crate.
Signed-off-by: Marc-André Lureau <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2438f18ee01108ead65be81be056e5a5da69120c
https://github.com/qemu/qemu/commit/2438f18ee01108ead65be81be056e5a5da69120c
Author: Marc-André Lureau <[email protected]>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M configure
Log Message:
-----------
build-sys: default to host vendor for rust target triple
This fixes docker-test@alpine, which uses "alpine" vendor.
Signed-off-by: Marc-André Lureau <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e9efa4a77168ac2816bf9471f878252ce6224710
https://github.com/qemu/qemu/commit/e9efa4a77168ac2816bf9471f878252ce6224710
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M hw/i386/pc.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/kvm/kvm.c
Log Message:
-----------
target/i386: add compatibility property for arch_capabilities
Prior to v10.1, if requested by user, arch-capabilities is always on
despite the fact that CPUID advertises it to be off/unvailable.
This causes a migration issue for VMs that are run on a machine
without arch-capabilities and expect this feature to be present
on the destination host with QEMU 10.1.
Add a compatibility property to restore the legacy behavior for all
machines with version prior to 10.1.
To preserve the functionality (added by 10.1) of turning off
ARCH_CAPABILITIES where Windows does not like it, use directly
the guest CPU vendor: x86_cpu_get_supported_feature_word is not
KVM-specific and therefore should not necessarily use the host
CPUID.
Co-authored-by: Hector Cao <[email protected]>
Signed-off-by: Hector Cao <[email protected]>
Fixes: d3a24134e37 ("target/i386: do not expose ARCH_CAPABILITIES on AMD CPU",
2025-07-17)
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 6529f31e0dccadb532c80b36e3efe7aef83f9cad
https://github.com/qemu/qemu/commit/6529f31e0dccadb532c80b36e3efe7aef83f9cad
Author: Hector Cao <[email protected]>
Date: 2025-10-07 (Tue, 07 Oct 2025)
Changed paths:
M hw/i386/pc.c
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: add compatibility property for pdcm feature
The pdcm feature is supposed to be disabled when PMU is not
available. Up until v10.1, pdcm feature is enabled even when PMU
is off. This behavior has been fixed but this change breaks the
migration of VMs that are run with QEMU < 10.0 and expect the pdcm
feature to be enabled on the destination host.
This commit restores the legacy behavior for machines with version
prior to 10.1 to allow the migration from older QEMU to QEMU 10.1.
Signed-off-by: Hector Cao <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Fixes: e68ec298090 ("i386/cpu: Move adjustment of CPUID_EXT_PDCM before
feature_dependencies[] check", 2025-06-20)
[Move property from migration object to CPU. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 37e12da5df8eb74042f11e9e7bec8a50b8090adb
https://github.com/qemu/qemu/commit/37e12da5df8eb74042f11e9e7bec8a50b8090adb
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/Kconfig
M meson.build
M meson_options.txt
M scripts/meson-buildoptions.sh
Log Message:
-----------
accel: Add Meson and config support for MSHV accelerator
Introduce a Meson feature option and default-config entry to allow
building QEMU with MSHV (Microsoft Hypervisor) acceleration support.
This is the first step toward implementing an MSHV backend in QEMU.
Signed-off-by: Magnus Kulke <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Add error for unavailable accelerator. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1e25327b244a217078e3fa5df18322c70932f478
https://github.com/qemu/qemu/commit/1e25327b244a217078e3fa5df18322c70932f478
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/emulate/x86_decode.c
M target/i386/emulate/x86_decode.h
M target/i386/emulate/x86_emu.c
M target/i386/emulate/x86_emu.h
Log Message:
-----------
target/i386/emulate: Allow instruction decoding from stream
Introduce a new helper function to decode x86 instructions from a
raw instruction byte stream. MSHV delivers an instruction stream in a
buffer of the vm_exit message. It can be used to speed up MMIO
emulation, since instructions do not have to be fetched and translated.
Added "fetch_instruction()" op to x86_emul_ops() to improve
traceability.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0daf817c80b57e58168309420abf0a8a3d2a60f6
https://github.com/qemu/qemu/commit/0daf817c80b57e58168309420abf0a8a3d2a60f6
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A include/system/mshv.h
M target/i386/cpu.h
M target/i386/emulate/meson.build
M target/i386/meson.build
A target/i386/mshv/meson.build
A target/i386/mshv/x86.c
Log Message:
-----------
target/i386/mshv: Add x86 decoder/emu implementation
The MSHV accelerator requires a x86 decoder/emulator in userland to
emulate MMIO instructions. This change contains the implementations for
the generalized i386 instruction decoder/emulator.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 638ac1c78457dd93ccd795b9c6c2673af8c7dd21
https://github.com/qemu/qemu/commit/638ac1c78457dd93ccd795b9c6c2673af8c7dd21
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A accel/accel-irq.c
M accel/meson.build
M hw/intc/ioapic.c
M hw/virtio/virtio-pci.c
A include/system/accel-irq.h
M include/system/mshv.h
Log Message:
-----------
hw/intc: Generalize APIC helper names from kvm_* to accel_*
Rename APIC helper functions to use an accel_* prefix instead of kvm_*
to support use by accelerators other than KVM. This is a preparatory
step for integrating MSHV support with common APIC logic.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Remove dead definition of mshv_msi_via_irqfd_enabled. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7db6086287502ad5a015ccc31e85ec9cac7e2716
https://github.com/qemu/qemu/commit/7db6086287502ad5a015ccc31e85ec9cac7e2716
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A include/hw/hyperv/hvgdk.h
A include/hw/hyperv/hvgdk_mini.h
A include/hw/hyperv/hvhdk.h
A include/hw/hyperv/hvhdk_mini.h
M scripts/update-linux-headers.sh
Log Message:
-----------
include/hw/hyperv: Add MSHV ABI header definitions
Introduce headers for the Microsoft Hypervisor (MSHV) userspace ABI,
including IOCTLs and structures used to interface with the hypervisor.
These definitions are based on the upstream Linux MSHV interface and
will be used by the MSHV accelerator backend in later patches.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Do not use __uN types. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: a6d6878650a0f4982918e8cd9d7ea6c3c3c681f7
https://github.com/qemu/qemu/commit/a6d6878650a0f4982918e8cd9d7ea6c3c3c681f7
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A linux-headers/linux/mshv.h
Log Message:
-----------
linux-headers/linux: Add mshv.h headers
This file has been added to the tree by running `update-linux-header.sh`
on linux v6.16.
Signed-off-by: Magnus Kulke <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d0d2918f968c55628e17e2733b799fcefb50f16b
https://github.com/qemu/qemu/commit/d0d2918f968c55628e17e2733b799fcefb50f16b
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/meson.build
A accel/mshv/meson.build
A accel/mshv/mshv-all.c
M include/system/mshv.h
A include/system/mshv_int.h
Log Message:
-----------
accel/mshv: Add accelerator skeleton
Introduce the initial scaffold for the MSHV (Microsoft Hypervisor)
accelerator backend. This includes the basic directory structure and
stub implementations needed to integrate with QEMU's accelerator
framework.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Move include of linux/mshv.h in the per-target section; create
include/system/mshv_int.h. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5006ea1344d134356a9b2e1afd521cf8df0c6a85
https://github.com/qemu/qemu/commit/5006ea1344d134356a9b2e1afd521cf8df0c6a85
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A accel/mshv/mem.c
M accel/mshv/meson.build
M accel/mshv/mshv-all.c
M include/system/mshv_int.h
Log Message:
-----------
accel/mshv: Register memory region listeners
Add memory listener hooks for the MSHV accelerator to track guest
memory regions. This enables the backend to respond to region
additions, removals and will be used to manage guest memory mappings
inside the hypervisor.
Actually registering physical memory in the hypervisor is still stubbed
out.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: c5f23bccde416aab52fe14dec6f6716a85f0cd04
https://github.com/qemu/qemu/commit/c5f23bccde416aab52fe14dec6f6716a85f0cd04
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
A accel/mshv/irq.c
M accel/mshv/mem.c
M accel/mshv/meson.build
M accel/mshv/mshv-all.c
A accel/mshv/trace-events
A accel/mshv/trace.h
M accel/stubs/meson.build
A accel/stubs/mshv-stub.c
M hw/intc/apic.c
M include/system/mshv.h
M include/system/mshv_int.h
M meson.build
M target/i386/mshv/meson.build
A target/i386/mshv/mshv-cpu.c
Log Message:
-----------
accel/mshv: Initialize VM partition
Create the MSHV virtual machine by opening a partition and issuing
the necessary ioctl to initialize it. This sets up the basic VM
structure and initial configuration used by MSHV to manage guest state.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Add stubs; fix format strings for trace-events; make mshv_hvcall
available only in per-target files; mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4dc5d4257259764b6fcd035870517fc4140d8962
https://github.com/qemu/qemu/commit/4dc5d4257259764b6fcd035870517fc4140d8962
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/mshv-all.c
M accel/mshv/trace-events
M include/system/mshv.h
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
accel/mshv: Add vCPU creation and execution loop
Create MSHV vCPUs using MSHV_CREATE_VP and initialize their state.
Register the MSHV CPU execution loop loop with the QEMU accelerator
framework to enable guest code execution.
The target/i386 functionality is still mostly stubbed out and will be
populated in a later commit in this series.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Fix g_free/g_clear_pointer confusion; rename qemu_wait_io_event;
mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 575df4df54e060661db45e6f80293b29ea8901c1
https://github.com/qemu/qemu/commit/575df4df54e060661db45e6f80293b29ea8901c1
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/mshv-all.c
Log Message:
-----------
accel/mshv: Add vCPU signal handling
Implement signal handling for MSHV vCPUs to support asynchronous
interrupts from the main thread.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4ed605c06e743b2ec0bfe35954d88b8c64dd3767
https://github.com/qemu/qemu/commit/4ed605c06e743b2ec0bfe35954d88b8c64dd3767
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Add CPU create and remove logic
Implement MSHV-specific hooks for vCPU creation and teardown in the
i386 target.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2bd7a6aa4743ee85c77c0520e8b422b3bfeab386
https://github.com/qemu/qemu/commit/2bd7a6aa4743ee85c77c0520e8b422b3bfeab386
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M include/system/mshv.h
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Implement mshv_store_regs()
Add support for writing general-purpose registers to MSHV vCPUs
during initialization or migration using the MSHV register interface. A
generic set_register call is introduced to abstract the HV call over
the various register types.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 66480a048a01fc833ba153410282609f26166141
https://github.com/qemu/qemu/commit/66480a048a01fc833ba153410282609f26166141
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Implement mshv_get_standard_regs()
Fetch standard register state from MSHV vCPUs to support debugging,
migration, and other introspection features in QEMU.
Fetch standard register state from a MHSV vCPU's. A generic get_regs()
function and a mapper to map the different register representations are
introduced.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0382c2c8544da66619d16988caaab8e3d9e881d4
https://github.com/qemu/qemu/commit/0382c2c8544da66619d16988caaab8e3d9e881d4
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Implement mshv_get_special_regs()
Retrieve special registers (e.g. segment, control, and descriptor
table registers) from MSHV vCPUs.
Various helper functions to map register state representations between
Qemu and MSHV are introduced.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 25a1d871e0f19bbf8fee471af5fefec52465bb09
https://github.com/qemu/qemu/commit/25a1d871e0f19bbf8fee471af5fefec52465bb09
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Implement mshv_arch_put_registers()
Write CPU register state to MSHV vCPUs. Various mapping functions to
prepare the payload for the HV call have been implemented.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: ca20d46fa94887a6e42061646a71ee44cbc9adb0
https://github.com/qemu/qemu/commit/ca20d46fa94887a6e42061646a71ee44cbc9adb0
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Set local interrupt controller state
To set the local interrupt controller state, perform hv calls retrieving
partition state from the hypervisor.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4fa04dd16216e266564606b7da582e5fce07bced
https://github.com/qemu/qemu/commit/4fa04dd16216e266564606b7da582e5fce07bced
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Register CPUID entries with MSHV
Convert the guest CPU's CPUID model into MSHV's format and register it
with the hypervisor. This ensures that the guest observes the correct
CPU feature set during CPUID instructions.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: f38e2a63e541730e114f6ed09e5f8719e388c8db
https://github.com/qemu/qemu/commit/f38e2a63e541730e114f6ed09e5f8719e388c8db
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/meson.build
A accel/mshv/msr.c
M include/system/mshv_int.h
M target/i386/cpu.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Register MSRs with MSHV
Build and register the guest vCPU's model-specific registers using
the MSHV interface.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 9bc6a1d29605a13c541629a651e41787af65a963
https://github.com/qemu/qemu/commit/9bc6a1d29605a13c541629a651e41787af65a963
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/mem.c
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Integrate x86 instruction decoder/emulator
Connect the x86 instruction decoder and emulator to the MSHV backend
to handle intercepted instructions. This enables software emulation
of MMIO operations in MSHV guests. MSHV has a translate_gva hypercall
that is used to accessing the physical guest memory.
A guest might read from unmapped memory regions (e.g. OVMF will probe
0xfed40000 for a vTPM). In those cases 0xFF bytes is returned instead of
aborting the execution.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 64118f452cbd97cd9fa790b1c15b65b435f136d2
https://github.com/qemu/qemu/commit/64118f452cbd97cd9fa790b1c15b65b435f136d2
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Write MSRs to the hypervisor
Push current model-specific register (MSR) values to MSHV's vCPUs as
part of setting state to the hypervisor.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 6dec60528c419781f1f79cd9837d5f26415a3fd7
https://github.com/qemu/qemu/commit/6dec60528c419781f1f79cd9837d5f26415a3fd7
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Implement mshv_vcpu_run()
Add the main vCPU execution loop for MSHV using the MSHV_RUN_VP ioctl.
The execution loop handles guest entry and VM exits. There are handlers for
memory r/w, PIO and MMIO to which the exit events are dispatched.
In case of MMIO the i386 instruction decoder/emulator is invoked to
perform the operation in user space.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: efc4093358511a58846a409b965213aa1bb9f31a
https://github.com/qemu/qemu/commit/efc4093358511a58846a409b965213aa1bb9f31a
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/mem.c
M accel/mshv/mshv-all.c
M accel/mshv/trace-events
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
accel/mshv: Handle overlapping mem mappings
QEMU maps certain regions into the guest multiple times, as seen in the
trace below. Currently the MSHV kernel driver will reject those
mappings. To workaround this, a record is kept (a static global list of
"slots", inspired by what the HVF accelerator has implemented). An
overlapping region is not registered at the hypervisor, and marked as
mapped=false. If there is an UNMAPPED_GPA exit, we can look for a slot
that is unmapped and would cover the GPA. In this case we map out the
conflicting slot and map in the requested region.
mshv_set_phys_mem add=1 name=pc.bios
mshv_map_memory => u_a=7ffff4e00000 gpa=00fffc0000 size=00040000
mshv_set_phys_mem add=1 name=ioapic
mshv_set_phys_mem add=1 name=hpet
mshv_set_phys_mem add=0 name=pc.ram
mshv_unmap_memory u_a=7fff67e00000 gpa=0000000000 size=80000000
mshv_set_phys_mem add=1 name=pc.ram
mshv_map_memory u_a=7fff67e00000 gpa=0000000000 size=000c0000
mshv_set_phys_mem add=1 name=pc.rom
mshv_map_memory u_a=7ffff4c00000 gpa=00000c0000 size=00020000
mshv_set_phys_mem add=1 name=pc.bios
mshv_remap_attempt => u_a=7ffff4e20000 gpa=00000e0000 size=00020000
The mapping table is guarded by a mutex for concurrent modification and
RCU mechanisms for concurrent reads. Writes occur rarely, but we'll have
to verify whether an unmapped region exist for each UNMAPPED_GPA exit,
which happens frequently.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Fix format strings for trace-events; mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e7b08dfb902430b4f8226d23d7cf9b2762b6fc83
https://github.com/qemu/qemu/commit/e7b08dfb902430b4f8226d23d7cf9b2762b6fc83
Author: Praveen K Paladugu <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M hmp-commands-info.hx
M hw/core/machine-hmp-cmds.c
M hw/core/machine-qmp-cmds.c
M include/monitor/hmp.h
M include/system/hw_accel.h
M qapi/accelerator.json
Log Message:
-----------
qapi/accel: Allow to query mshv capabilities
Allow to query mshv capabilities via query-mshv QMP and info mshv HMP commands.
Signed-off-by: Magnus Kulke <[email protected]>
Acked-by: Dr. David Alan Gilbert <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Fix "since" version. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: e4a20afce59937073298d716cc829bdc026542dc
https://github.com/qemu/qemu/commit/e4a20afce59937073298d716cc829bdc026542dc
Author: Magnus Kulke <[email protected]>
Date: 2025-10-08 (Wed, 08 Oct 2025)
Changed paths:
M accel/mshv/mshv-all.c
M include/system/mshv_int.h
M target/i386/mshv/mshv-cpu.c
Log Message:
-----------
target/i386/mshv: Use preallocated page for hvcall
There are hvcalls that are invoked during MMIO exits, the payload is of
dynamic size. To avoid heap allocations we can use preallocated pages as
in/out buffer for those calls. A page is reserved per vCPU and used for
set/get register hv calls.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Use standard MAX_CONST macro; mshv.h/mshv_int.h split. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 3af71a1a6a7a497df7d3026239d6136b56e3d5ab
https://github.com/qemu/qemu/commit/3af71a1a6a7a497df7d3026239d6136b56e3d5ab
Author: Magnus Kulke <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M docs/about/build-platforms.rst
M docs/devel/codebase.rst
M docs/glossary.rst
M docs/system/introduction.rst
M qemu-options.hx
Log Message:
-----------
docs: Add mshv to documentation
Added mshv to the list of accelerators in doc text.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1872bd9f2dad5113b0c27d352ec49683e0953c7f
https://github.com/qemu/qemu/commit/1872bd9f2dad5113b0c27d352ec49683e0953c7f
Author: Magnus Kulke <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M MAINTAINERS
Log Message:
-----------
MAINTAINERS: Add maintainers for mshv accelerator
Adding Magnus Kulke and Wei Liu to the maintainers file for the
respective folders/files.
Signed-off-by: Magnus Kulke <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
[Rename "MAHV CPUs" to mention x86. - Paolo]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 1a583ca382f63be537977e76bf54a0670e57a2a1
https://github.com/qemu/qemu/commit/1a583ca382f63be537977e76bf54a0670e57a2a1
Author: Marc-André Lureau <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M tests/docker/common.rc
Log Message:
-----------
tests/docker: make --enable-rust overridable with EXTRA_CONFIGURE_OPTS
Signed-off-by: Marc-André Lureau <[email protected]>
Link:
https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b9ef6198d709f431d893d1b5525cdf7fd7a3e11b
https://github.com/qemu/qemu/commit/b9ef6198d709f431d893d1b5525cdf7fd7a3e11b
Author: Stefan Hajnoczi <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M scripts/rust/rust_root_crate.sh
Log Message:
-----------
rust: fix path to rust_root_crate.sh
Generated Rust root crate source files contain the wrong path to the
rust_root_crate.sh script.
Signed-off-by: Stefan Hajnoczi <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: cdcb1d39eb72410bee55b6d3344f176c86224447
https://github.com/qemu/qemu/commit/cdcb1d39eb72410bee55b6d3344f176c86224447
Author: Huacai Chen <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.*
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: dd333bf0e3ab2096702844ae0d0cff8a8864e5f7
https://github.com/qemu/qemu/commit/dd333bf0e3ab2096702844ae0d0cff8a8864e5f7
Author: Huacai Chen <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes
Now VIRT_GED_CPUHP_ADDR is not aligned to 4 bytes, but if Linux kernel
is built with ACPI_MISALIGNMENT_NOT_SUPPORTED, it assumes the alignment,
otherwise we get ACPI errors at boot phase:
ACPI Error: AE_AML_ALIGNMENT, Returned by Handler for [SystemMemory]
(20250404/evregion-301)
ACPI Error: Aborting method \_SB.CPUS.CSTA due to previous error
(AE_AML_ALIGNMENT) (20250404/psparse-529)
ACPI Error: Aborting method \_SB.CPUS.C000._STA due to previous error
(AE_AML_ALIGNMENT) (20250404/psparse-529)
ACPI Error: Method execution failed \_SB.CPUS.C000._STA due to previous error
(AE_AML_ALIGNMENT) (20250404/uteval-68)
VIRT_GED_MEM_ADDR and VIRT_GED_REG_ADDR are already aligned now, but use
QEMU_ALIGN_UP() to explicitly align them can make code more robust.
Reported-by: Nathan Chancellor <[email protected]>
Suggested-by: WANG Rui <[email protected]>
Signed-off-by: Huacai Chen <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 68e8df8cfa4fcf053e306f24edeaea59d90b0b3d
https://github.com/qemu/qemu/commit/68e8df8cfa4fcf053e306f24edeaea59d90b0b3d
Author: Huacai Chen <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M tests/data/acpi/loongarch64/virt/DSDT
M tests/data/acpi/loongarch64/virt/DSDT.memhp
M tests/data/acpi/loongarch64/virt/DSDT.numamem
M tests/data/acpi/loongarch64/virt/DSDT.topology
M tests/qtest/bios-tables-test-allowed-diff.h
Log Message:
-----------
tests/data/acpi/loongarch64: Update expected DSDT.*
DSDT diffs from "iasl -d":
@@ -11,7 +11,7 @@
* Signature "DSDT"
* Length 0x000011FB (4603)
* Revision 0x01 **** 32-bit table (V1), no 64-bit math support
- * Checksum 0x5D
+ * Checksum 0x5B
* OEM ID "BOCHS "
* OEM Table ID "BXPC "
* OEM Revision 0x00000001 (1)
@@ -1426,11 +1426,11 @@
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
Memory32Fixed (ReadWrite,
- 0x100E001F, // Address Base
+ 0x100E0020, // Address Base
0x0000000C, // Address Length
)
})
- OperationRegion (PRST, SystemMemory, 0x100E001F, 0x0C)
+ OperationRegion (PRST, SystemMemory, 0x100E0020, 0x0C)
Field (PRST, ByteAcc, NoLock, WriteAsZeros)
{
Offset (0x04),
Signed-off-by: Huacai Chen <[email protected]>
Acked-by: Michael S. Tsirkin <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 410dfbf620aef6361a4fdb40f7a7ee32bf5581b4
https://github.com/qemu/qemu/commit/410dfbf620aef6361a4fdb40f7a7ee32bf5581b4
Author: Bibo Mao <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/internals.h
M target/loongarch/tcg/meson.build
A target/loongarch/tcg/tcg_cpu.c
M target/loongarch/tcg/tcg_loongarch.h
Log Message:
-----------
target/loongarch: Move TCG specified functions to tcg_cpu.c
New file target/loongarch/tcg/tcg_cpu.c is created, and move TCG
specified functions to here from file target/loongarch/cpu.c
It is only code movement and there is no any function change.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 29332340e14738998a7ebcb62c5c9a310e8fb455
https://github.com/qemu/qemu/commit/29332340e14738998a7ebcb62c5c9a310e8fb455
Author: Bibo Mao <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M target/loongarch/cpu.c
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
target/loongarch: Move function do_raise_exception() to tcg_cpu.c
Function do_raise_exception() is specified with TCG mode, so move
it to file target/loongarch/tcg/tcg_cpu.c
It is only code movement and there is no any function change.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: fa6af7f6bf6dbc4c83595905d2572ad86358aa67
https://github.com/qemu/qemu/commit/fa6af7f6bf6dbc4c83595905d2572ad86358aa67
Author: Bibo Mao <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M target/loongarch/internals.h
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
target/loongarch: Define loongarch_exception_name() as static
Function loongarch_exception_name() is only called in defined file
target/loongarch/tcg/tcg_cpu.c, set this function as static.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Song Gao <[email protected]>
Commit: 1188b07e606e52ba6efd69d97a9909e00d2bb70e
https://github.com/qemu/qemu/commit/1188b07e606e52ba6efd69d97a9909e00d2bb70e
Author: Richard Henderson <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M MAINTAINERS
M accel/Kconfig
A accel/accel-irq.c
M accel/meson.build
A accel/mshv/irq.c
A accel/mshv/mem.c
A accel/mshv/meson.build
A accel/mshv/mshv-all.c
A accel/mshv/msr.c
A accel/mshv/trace-events
A accel/mshv/trace.h
M accel/stubs/meson.build
A accel/stubs/mshv-stub.c
M configure
M docs/about/build-platforms.rst
M docs/devel/codebase.rst
M docs/glossary.rst
M docs/system/introduction.rst
M hmp-commands-info.hx
M hw/core/machine-hmp-cmds.c
M hw/core/machine-qmp-cmds.c
M hw/i386/pc.c
M hw/intc/apic.c
M hw/intc/ioapic.c
M hw/virtio/virtio-pci.c
M include/hw/core/cpu.h
A include/hw/hyperv/hvgdk.h
A include/hw/hyperv/hvgdk_mini.h
A include/hw/hyperv/hvhdk.h
A include/hw/hyperv/hvhdk_mini.h
M include/monitor/hmp.h
A include/system/accel-irq.h
M include/system/hw_accel.h
A include/system/mshv.h
A include/system/mshv_int.h
A linux-headers/linux/mshv.h
M meson.build
M meson_options.txt
M qapi/accelerator.json
M qemu-options.hx
M rust/Cargo.lock
M rust/Cargo.toml
M rust/bql/Cargo.toml
M rust/bql/meson.build
M rust/bql/src/bindings.rs
M rust/chardev/Cargo.toml
M rust/chardev/meson.build
M rust/chardev/src/bindings.rs
M rust/hw/char/pl011/Cargo.toml
M rust/hw/char/pl011/meson.build
M rust/hw/char/pl011/src/bindings.rs
M rust/hw/core/Cargo.toml
M rust/hw/core/meson.build
M rust/hw/core/src/bindings.rs
M rust/meson.build
M rust/migration/Cargo.toml
M rust/migration/meson.build
M rust/migration/src/bindings.rs
M rust/qom/Cargo.toml
M rust/qom/meson.build
M rust/qom/src/bindings.rs
M rust/system/Cargo.toml
M rust/system/meson.build
M rust/system/src/bindings.rs
M rust/util/Cargo.toml
M rust/util/meson.build
M rust/util/src/bindings.rs
M scripts/archive-source.sh
M scripts/meson-buildoptions.sh
M scripts/rust/rust_root_crate.sh
M scripts/update-linux-headers.sh
M subprojects/.gitignore
A subprojects/glib-sys-0.21-rs.wrap
A subprojects/packagefiles/glib-sys-0.21-rs/meson.build
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/emulate/meson.build
M target/i386/emulate/x86_decode.c
M target/i386/emulate/x86_decode.h
M target/i386/emulate/x86_emu.c
M target/i386/emulate/x86_emu.h
M target/i386/kvm/kvm.c
M target/i386/meson.build
A target/i386/mshv/meson.build
A target/i386/mshv/mshv-cpu.c
A target/i386/mshv/x86.c
M tests/docker/common.rc
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* i386: fix migration issues in 10.1
* target/i386/mshv: new accelerator
* rust: use glib-sys-rs
* rust: fixes for docker tests
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# gpg: Good signature from "Paolo Bonzini <[email protected]>" [unknown]
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* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (35 commits)
rust: fix path to rust_root_crate.sh
tests/docker: make --enable-rust overridable with EXTRA_CONFIGURE_OPTS
MAINTAINERS: Add maintainers for mshv accelerator
docs: Add mshv to documentation
target/i386/mshv: Use preallocated page for hvcall
qapi/accel: Allow to query mshv capabilities
accel/mshv: Handle overlapping mem mappings
target/i386/mshv: Implement mshv_vcpu_run()
target/i386/mshv: Write MSRs to the hypervisor
target/i386/mshv: Integrate x86 instruction decoder/emulator
target/i386/mshv: Register MSRs with MSHV
target/i386/mshv: Register CPUID entries with MSHV
target/i386/mshv: Set local interrupt controller state
target/i386/mshv: Implement mshv_arch_put_registers()
target/i386/mshv: Implement mshv_get_special_regs()
target/i386/mshv: Implement mshv_get_standard_regs()
target/i386/mshv: Implement mshv_store_regs()
target/i386/mshv: Add CPU create and remove logic
accel/mshv: Add vCPU signal handling
accel/mshv: Add vCPU creation and execution loop
...
Signed-off-by: Richard Henderson <[email protected]>
Commit: 94474a7733a57365d5a27efc28c05462e90e8944
https://github.com/qemu/qemu/commit/94474a7733a57365d5a27efc28c05462e90e8944
Author: Richard Henderson <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M include/hw/loongarch/virt.h
M target/loongarch/cpu.c
M target/loongarch/internals.h
M target/loongarch/tcg/meson.build
A target/loongarch/tcg/tcg_cpu.c
M target/loongarch/tcg/tcg_loongarch.h
M tests/data/acpi/loongarch64/virt/DSDT
M tests/data/acpi/loongarch64/virt/DSDT.memhp
M tests/data/acpi/loongarch64/virt/DSDT.numamem
M tests/data/acpi/loongarch64/virt/DSDT.topology
Log Message:
-----------
Merge tag 'pull-loongarch-20251009' of https://github.com/gaosong715/qemu
into staging
pull-loongarch-20251009
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# zSHZKODKAADNt1lgzQ9iJx3uUBeUMdFKagIOrURPeCItLpoaKA==
# =OnvQ
# -----END PGP SIGNATURE-----
# gpg: Signature made Thu 09 Oct 2025 04:54:19 AM PDT
# gpg: using RSA key CA473C44D6A09C189A193FCD452B96852B268216
# gpg: Good signature from "Song Gao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: CA47 3C44 D6A0 9C18 9A19 3FCD 452B 9685 2B26 8216
* tag 'pull-loongarch-20251009' of https://github.com/gaosong715/qemu:
target/loongarch: Define loongarch_exception_name() as static
target/loongarch: Move function do_raise_exception() to tcg_cpu.c
target/loongarch: Move TCG specified functions to tcg_cpu.c
tests/data/acpi/loongarch64: Update expected DSDT.*
hw/loongarch/virt: Align VIRT_GED_CPUHP_ADDR to 4 bytes
bios-tables-test-allowed-diff.h: Allow LoongArch DSDT.*
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/37ad0e48e9fd...94474a7733a5
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