[Qemu-commits] [qemu/qemu] 971e25: system/ramblock: Remove obsolete comment

[Richard Henderson via Qemu-commits]

  Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: 971e25424c0e2cbbea28cc7e6d09a4569ca6cb06
      
https://github.com/qemu/qemu/commit/971e25424c0e2cbbea28cc7e6d09a4569ca6cb06
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ramblock.h

  Log Message:
  -----------
  system/ramblock: Remove obsolete comment

This comment was added almost 5 years ago in commit 41aa4e9fd84
("ram_addr: Split RAMBlock definition"). Clearly it got ignored:

  $ git grep -l system/ramblock.h
  hw/display/virtio-gpu-udmabuf.c
  hw/hyperv/hv-balloon.c
  hw/virtio/vhost-user.c
  migration/dirtyrate.c
  migration/file.c
  migration/multifd-nocomp.c
  migration/multifd-qatzip.c
  migration/multifd-qpl.c
  migration/multifd-uadk.c
  migration/multifd-zero-page.c
  migration/multifd-zlib.c
  migration/multifd-zstd.c
  migration/multifd.c
  migration/postcopy-ram.c
  system/ram-block-attributes.c
  target/i386/kvm/tdx.c
  tests/qtest/fuzz/generic_fuzz.c

At this point it seems saner to just remove it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: David Hildenbrand <da...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Message-Id: <20251002032812.26069-2-phi...@linaro.org>


  Commit: 34f9b0ad082268e347cee5c4903940e4ea67614f
      
https://github.com/qemu/qemu/commit/34f9b0ad082268e347cee5c4903940e4ea67614f
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M include/system/ramblock.h
    M migration/ram.c
    M system/physmem.c

  Log Message:
  -----------
  system/ramblock: Move ram_block_is_pmem() declaration

Move ramblock_is_pmem() along with the RAM Block API
exposed by the "system/ramblock.h" header. Rename as
ram_block_is_pmem() to keep API prefix consistency.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Message-Id: <20251002032812.26069-3-phi...@linaro.org>


  Commit: 8fe6ce40190872b4ccb4a3d601f4361b4bcdb0bb
      
https://github.com/qemu/qemu/commit/8fe6ce40190872b4ccb4a3d601f4361b4bcdb0bb
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M accel/kvm/kvm-all.c
    M hw/hyperv/hv-balloon-our_range_memslots.c
    M hw/virtio/virtio-balloon.c
    M hw/virtio/virtio-mem.c
    M include/exec/cpu-common.h
    M include/system/ramblock.h

  Log Message:
  -----------
  system/ramblock: Move ram_block_discard_*_range() declarations

Keep RAM blocks API in the same header: "system/ramblock.h".

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Message-Id: <20251002032812.26069-4-phi...@linaro.org>


  Commit: fe11c4957b8120c48ed650e7c970ea004d8432f4
      
https://github.com/qemu/qemu/commit/fe11c4957b8120c48ed650e7c970ea004d8432f4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ramblock.h
    M system/physmem.c

  Log Message:
  -----------
  system/ramblock: Rename @start -> @offset in ram_block_discard_range()

Rename @start as @offset, since it express an offset within a RAMBlock.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Message-Id: <20251002032812.26069-5-phi...@linaro.org>


  Commit: 6feb119d32ed1b8853e407495fad33795b9c2137
      
https://github.com/qemu/qemu/commit/6feb119d32ed1b8853e407495fad33795b9c2137
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M include/system/ramblock.h

  Log Message:
  -----------
  system/ramblock: Move RAMBlock helpers out of "system/ram_addr.h"

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Acked-by: Peter Xu <pet...@redhat.com>
Message-Id: <20251002032812.26069-6-phi...@linaro.org>


  Commit: bb02dcf2d4c0ec446fb53516eea76087f8b7a3ed
      
https://github.com/qemu/qemu/commit/bb02dcf2d4c0ec446fb53516eea76087f8b7a3ed
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M system/physmem.c

  Log Message:
  -----------
  system/memory: Split address_space_write_rom_internal

In 2dbaf58bbe7 we conditionally skipped the increment
of buf because ubsan warns incrementing NULL, and buf
is always NULL for FLUSH_CACHE.  However, the existence
of the test for NULL caused Coverity to warn that the
memcpy in the WRITE_DATA case lacked a test for NULL.

Duplicate address_space_write_rom_internal into the two
callers, dropping enum write_rom_type, and simplify.
This eliminates buf in the flush case, and eliminates
the conditional increment of buf in the write case.

Coverity: CID 1621220
Fixes: 2dbaf58bbe7 ("system/physmem: Silence warning from ubsan")
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-ID: <20250922192940.2908002-1-richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>


  Commit: 7d4c9d2cb89818ef800718a4f462b34a21ee65cb
      
https://github.com/qemu/qemu/commit/7d4c9d2cb89818ef800718a4f462b34a21ee65cb
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/devel/loads-stores.rst

  Log Message:
  -----------
  docs/devel/loads-stores: Stop mentioning cpu_physical_memory_write_rom()

Update the documentation after commit 3c8133f9737 ("Rename
cpu_physical_memory_write_rom() to address_space_write_rom()").

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-2-phi...@linaro.org>


  Commit: 839976e9da4b577aca284847b7e965332f2ca687
      
https://github.com/qemu/qemu/commit/839976e9da4b577aca284847b7e965332f2ca687
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/memory.h
    M system/physmem.c

  Log Message:
  -----------
  system/memory: Factor address_space_is_io() out

Factor address_space_is_io() out of cpu_physical_memory_is_io().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-3-phi...@linaro.org>


  Commit: 6ffaa9219616d12bc6c3e7cb26a77f7432ac0c70
      
https://github.com/qemu/qemu/commit/6ffaa9219616d12bc6c3e7cb26a77f7432ac0c70
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/i386/arch_memory_mapping.c

  Log Message:
  -----------
  target/i386/arch_memory_mapping: Use address_space_memory_is_io()

Since all functions have an address space argument, it is
trivial to replace cpu_physical_memory_is_io() by
address_space_memory_is_io().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-4-phi...@linaro.org>


  Commit: 1e440937d699514207946c36c353a7a616f8b805
      
https://github.com/qemu/qemu/commit/1e440937d699514207946c36c353a7a616f8b805
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/s390x/sclp.c

  Log Message:
  -----------
  hw/s390x/sclp: Use address_space_memory_is_io() in sclp_service_call()

When cpu_address_space_init() isn't called during vCPU creation,
its single address space is the global &address_space_memory.

As s390x boards don't call cpu_address_space_init(), cpu->as
points to &address_space_memory.

We can then replace cpu_physical_memory_is_io() by the semantically
equivalent address_space_memory_is_io() call.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Eric Farman <far...@linux.ibm.com>
Message-Id: <20251002084203.63899-5-phi...@linaro.org>


  Commit: ec1eb357cb86eee74d63940154db1e1bfa86026a
      
https://github.com/qemu/qemu/commit/ec1eb357cb86eee74d63940154db1e1bfa86026a
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/exec/cpu-common.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Remove cpu_physical_memory_is_io()

There are no more uses of the legacy cpu_physical_memory_is_io()
method. Remove it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-6-phi...@linaro.org>


  Commit: c2cac27dba3db3348563154f9b4b436ecde7b09a
      
https://github.com/qemu/qemu/commit/c2cac27dba3db3348563154f9b4b436ecde7b09a
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/core/loader.c
    M include/exec/cpu-common.h
    M include/system/memory.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Pass address space argument to cpu_flush_icache_range()

Rename cpu_flush_icache_range() as address_space_flush_icache_range(),
passing an address space by argument. The single caller, rom_reset(),
already operates on an address space. Use it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-7-phi...@linaro.org>


  Commit: 0d4e15e8f80e77a5bf22e3620ed990331f05256d
      
https://github.com/qemu/qemu/commit/0d4e15e8f80e77a5bf22e3620ed990331f05256d
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/s390x/sclp.c

  Log Message:
  -----------
  hw/s390x/sclp: Replace [cpu_physical_memory -> address_space]_r/w()

cpu_physical_memory_read() and cpu_physical_memory_write() are
legacy (see commit b7ecba0f6f6), replace by address_space_read()
and address_space_write().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Eric Farman <far...@linux.ibm.com>
Message-Id: <20251002084203.63899-8-phi...@linaro.org>


  Commit: 2fd38d9c2944efef3b96fe9047b3c0f4d4e25eb4
      
https://github.com/qemu/qemu/commit/2fd38d9c2944efef3b96fe9047b3c0f4d4e25eb4
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/s390x/mmu_helper.c

  Log Message:
  -----------
  target/s390x/mmu: Replace [cpu_physical_memory -> address_space]_rw()

When cpu_address_space_init() isn't called during vCPU creation,
its single address space is the global &address_space_memory.

As s390x boards don't call cpu_address_space_init(), cpu->as
points to &address_space_memory.

We can then replace cpu_physical_memory_rw() by the semantically
equivalent address_space_rw() call.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-9-phi...@linaro.org>


  Commit: 04979ddde45f1064aa98317172b0a5b99b4b4d39
      
https://github.com/qemu/qemu/commit/04979ddde45f1064aa98317172b0a5b99b4b4d39
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/i386/whpx/whpx-all.c

  Log Message:
  -----------
  target/i386/whpx: Replace legacy cpu_physical_memory_rw() call

Get the vCPU address space and convert the legacy
cpu_physical_memory_rw() by address_space_rw().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-10-phi...@linaro.org>


  Commit: 12a65afbbfd8bef09cafb1e0e7883c30ddc1c956
      
https://github.com/qemu/qemu/commit/12a65afbbfd8bef09cafb1e0e7883c30ddc1c956
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/i386/kvm/xen-emu.c

  Log Message:
  -----------
  target/i386/kvm: Replace legacy cpu_physical_memory_rw() call

Get the vCPU address space and convert the legacy
cpu_physical_memory_rw() by address_space_rw().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-11-phi...@linaro.org>


  Commit: 5699f6a4409af985d45cd67a0695a97655fec8bf
      
https://github.com/qemu/qemu/commit/5699f6a4409af985d45cd67a0695a97655fec8bf
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/i386/nvmm/nvmm-all.c

  Log Message:
  -----------
  target/i386/nvmm: Inline cpu_physical_memory_rw() in nvmm_mem_callback

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-12-phi...@linaro.org>


  Commit: 94c460835df5b810309a5ae4c89f0cddddbd9f6e
      
https://github.com/qemu/qemu/commit/94c460835df5b810309a5ae4c89f0cddddbd9f6e
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/xen/xen-hvm-common.c

  Log Message:
  -----------
  hw/xen/hvm: Inline cpu_physical_memory_rw() in rw_phys_req_item()

cpu_physical_memory_rw() is legacy, replace by address_space_rw().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-13-phi...@linaro.org>


  Commit: be481476bae495191c1184b368531401a5584904
      
https://github.com/qemu/qemu/commit/be481476bae495191c1184b368531401a5584904
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/exec/cpu-common.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_read/write()

In order to remove cpu_physical_memory_rw() in a pair of commits,
and due to a cyclic dependency between "exec/cpu-common.h" and
"system/memory.h", un-inline cpu_physical_memory_read() and
cpu_physical_memory_write() as a prerequired step.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-14-phi...@linaro.org>


  Commit: 5b7502234c7ede51ab6e684b6abc64d5fee3c1a1
      
https://github.com/qemu/qemu/commit/5b7502234c7ede51ab6e684b6abc64d5fee3c1a1
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M scripts/coccinelle/exec_rw_const.cocci
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Avoid cpu_physical_memory_rw when is_write is constant

Following the mechanical changes of commit adeefe01671 ("Avoid
cpu_physical_memory_rw() with a constant is_write argument"),
replace:

 - cpu_physical_memory_rw(, is_write=false) -> address_space_read()
 - cpu_physical_memory_rw(, is_write=true)  -> address_space_write()

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-15-phi...@linaro.org>


  Commit: e98ae807c42e5c9f5089c947f7c6ef444248a946
      
https://github.com/qemu/qemu/commit/e98ae807c42e5c9f5089c947f7c6ef444248a946
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/devel/loads-stores.rst
    M include/exec/cpu-common.h
    M scripts/coccinelle/exec_rw_const.cocci
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Remove legacy cpu_physical_memory_rw()

The legacy cpu_physical_memory_rw() method is no more used,
remove it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-16-phi...@linaro.org>


  Commit: 41d5e37e0e2080e9d351f75ebd60d21e0b4e115e
      
https://github.com/qemu/qemu/commit/41d5e37e0e2080e9d351f75ebd60d21e0b4e115e
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/virtio/vhost.c

  Log Message:
  -----------
  hw/virtio/vhost: Replace legacy cpu_physical_memory_*map() calls

Use VirtIODevice::dma_as address space to convert the legacy
cpu_physical_memory_[un]map() calls to address_space_[un]map().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-17-phi...@linaro.org>


  Commit: f9f713f1b4a272826f4acc4d57483e9dd1faa3f7
      
https://github.com/qemu/qemu/commit/f9f713f1b4a272826f4acc4d57483e9dd1faa3f7
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/virtio/virtio.c

  Log Message:
  -----------
  hw/virtio/virtio: Replace legacy cpu_physical_memory_map() call

Propagate VirtIODevice::dma_as to virtqueue_undo_map_desc()
in order to replace the legacy cpu_physical_memory_unmap()
call by address_space_unmap().

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251002084203.63899-18-phi...@linaro.org>


  Commit: 2fb5ae9832728f766b66120fd23c7cf9db9d3ec2
      
https://github.com/qemu/qemu/commit/2fb5ae9832728f766b66120fd23c7cf9db9d3ec2
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h

  Log Message:
  -----------
  system/ram_addr: Remove unnecessary 'exec/cpu-common.h' header

Nothing in "system/ram_addr.h" requires definitions from
"exec/cpu-common.h", remove it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-2-phi...@linaro.org>


  Commit: a55e8ffe47ebe0d7da7b5008b5efdfa652545a7b
      
https://github.com/qemu/qemu/commit/a55e8ffe47ebe0d7da7b5008b5efdfa652545a7b
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M accel/kvm/kvm-all.c

  Log Message:
  -----------
  accel/kvm: Include missing 'exec/target_page.h' header

The "exec/target_page.h" header is indirectly pulled from
"system/ram_addr.h". Include it explicitly, in order to
avoid unrelated issues when refactoring "system/ram_addr.h":

  accel/kvm/kvm-all.c: In function ‘kvm_init’:
  accel/kvm/kvm-all.c:2636:12: error: ‘TARGET_PAGE_SIZE’ undeclared (first use 
in this function); did you mean ‘TARGET_PAGE_BITS’?
   2636 |     assert(TARGET_PAGE_SIZE <= qemu_real_host_page_size());
        |            ^~~~~~~~~~~~~~~~

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-3-phi...@linaro.org>


  Commit: d08bc190a0302d1fad8ca71a3ba13c51f7337bbf
      
https://github.com/qemu/qemu/commit/d08bc190a0302d1fad8ca71a3ba13c51f7337bbf
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/s390x/s390-stattrib-kvm.c
    M hw/s390x/s390-stattrib.c

  Log Message:
  -----------
  hw/s390x/s390-stattrib: Include missing 'exec/target_page.h' header

The "exec/target_page.h" header is indirectly pulled from
"system/ram_addr.h". Include it explicitly, in order to
avoid unrelated issues when refactoring "system/ram_addr.h":

  hw/s390x/s390-stattrib-kvm.c: In function ‘kvm_s390_stattrib_set_stattr’:
  hw/s390x/s390-stattrib-kvm.c:89:57: error: ‘TARGET_PAGE_SIZE’ undeclared 
(first use in this function); did you mean ‘TARGET_PAGE_BITS’?
     89 |     unsigned long max = s390_get_memory_limit(s390ms) / 
TARGET_PAGE_SIZE;
        |                                                         
^~~~~~~~~~~~~~~~
        |                                                         
TARGET_PAGE_BITS

Since "system/ram_addr.h" is actually not needed, remove it.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Eric Farman <far...@linux.ibm.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-Id: <20251001175448.18933-4-phi...@linaro.org>


  Commit: edd1f91d38dfc341cac02529fcd315609e959763
      
https://github.com/qemu/qemu/commit/edd1f91d38dfc341cac02529fcd315609e959763
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/vfio/listener.c

  Log Message:
  -----------
  hw/vfio/listener: Include missing 'exec/target_page.h' header

The "exec/target_page.h" header is indirectly pulled from
"system/ram_addr.h". Include it explicitly, in order to
avoid unrelated issues when refactoring "system/ram_addr.h":

  hw/vfio/listener.c: In function ‘vfio_ram_discard_register_listener’:
  hw/vfio/listener.c:258:28: error: implicit declaration of function 
‘qemu_target_page_size’; did you mean ‘qemu_ram_pagesize’?
    258 |     int target_page_size = qemu_target_page_size();
        |                            ^~~~~~~~~~~~~~~~~~~~~

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Message-Id: <20251001175448.18933-5-phi...@linaro.org>


  Commit: 6204f64260b78cc4080ca7b1ee221718273d6566
      
https://github.com/qemu/qemu/commit/6204f64260b78cc4080ca7b1ee221718273d6566
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/tcg/mte_helper.c

  Log Message:
  -----------
  target/arm/tcg/mte: Include missing 'exec/target_page.h' header

The "exec/target_page.h" header is indirectly pulled from
"system/ram_addr.h". Include it explicitly, in order to
avoid unrelated issues when refactoring "system/ram_addr.h":

  target/arm/tcg/mte_helper.c:815:23: error: use of undeclared identifier 
'TARGET_PAGE_MASK'
    815 |     prev_page = ptr & TARGET_PAGE_MASK;
        |                       ^
  target/arm/tcg/mte_helper.c:816:29: error: use of undeclared identifier 
'TARGET_PAGE_SIZE'
    816 |     next_page = prev_page + TARGET_PAGE_SIZE;
        |                             ^

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-6-phi...@linaro.org>


  Commit: 97480ca692e94bb790190a43bb122bd0752b8f62
      
https://github.com/qemu/qemu/commit/97480ca692e94bb790190a43bb122bd0752b8f62
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_pci.c
    M hw/remote/memory.c
    M hw/remote/proxy-memory-listener.c
    M hw/s390x/s390-virtio-ccw.c
    M hw/vfio/spapr.c
    M hw/virtio/virtio-mem.c

  Log Message:
  -----------
  hw: Remove unnecessary 'system/ram_addr.h' header

None of these files require definition exposed by "system/ram_addr.h",
remove its inclusion.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Jagannathan Raman <jag.ra...@oracle.com>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Reviewed-by: Eric Farman <far...@linux.ibm.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Acked-by: Michael S. Tsirkin <m...@redhat.com>
Message-Id: <20251001175448.18933-7-phi...@linaro.org>


  Commit: 81aef73696c37c1680412e52d0a63c9c1fdd0466
      
https://github.com/qemu/qemu/commit/81aef73696c37c1680412e52d0a63c9c1fdd0466
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_get_dirty_flag()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

cpu_physical_memory_get_dirty() doesn't involve any CPU,
remove the 'cpu_' prefix.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-8-phi...@linaro.org>


  Commit: 3a0539afcbdf83aa919e32a36107bbe357ae9ef2
      
https://github.com/qemu/qemu/commit/3a0539afcbdf83aa919e32a36107bbe357ae9ef2
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_is_clean()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-9-phi...@linaro.org>


  Commit: 84a8e6399bc06550e41f5b2f7b94e4a2213b2ebc
      
https://github.com/qemu/qemu/commit/84a8e6399bc06550e41f5b2f7b94e4a2213b2ebc
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_range_includes_clean()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

cpu_physical_memory_all_dirty() doesn't involve any CPU,
remove the 'cpu_' prefix.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-10-phi...@linaro.org>


  Commit: 62c889eb7dfd4da5e30e9496496917bad53851fe
      
https://github.com/qemu/qemu/commit/62c889eb7dfd4da5e30e9496496917bad53851fe
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_set_dirty_flag()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-11-phi...@linaro.org>


  Commit: 6290580e9b712d5cbaa1cc2a314d07cd4a6c283d
      
https://github.com/qemu/qemu/commit/6290580e9b712d5cbaa1cc2a314d07cd4a6c283d
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_set_dirty_range()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-12-phi...@linaro.org>


  Commit: 3037def8b8e91ed3ce3f711dc646e07e0ef894dc
      
https://github.com/qemu/qemu/commit/3037def8b8e91ed3ce3f711dc646e07e0ef894dc
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h

  Log Message:
  -----------
  system/physmem: Remove _WIN32 #ifdef'ry

Commit fb3ecb7ea40 ("exec: Exclude non portable function for
MinGW") guarded cpu_physical_memory_set_dirty_lebitmap() within
_WIN32 #ifdef'ry because of the non-portable ffsl() call, which
was later replaced for the same reason by commit 7224f66ec3c
("exec: replace ffsl with ctzl"); we don't need that anymore.

Reported-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-13-phi...@linaro.org>


  Commit: 198c5f707f43d970b22e9b52a0ec573aa595ef35
      
https://github.com/qemu/qemu/commit/198c5f707f43d970b22e9b52a0ec573aa595ef35
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_set_dirty_lebitmap()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

Remove the now unneeded "system/xen.h" header.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-14-phi...@linaro.org>


  Commit: 57f3d859bf947cdef418dec14445b1f8935f2d20
      
https://github.com/qemu/qemu/commit/57f3d859bf947cdef418dec14445b1f8935f2d20
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Un-inline cpu_physical_memory_dirty_bits_cleared()

Avoid maintaining large functions in header, rely on the
linker to optimize at linking time.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-15-phi...@linaro.org>


  Commit: 1085a44ebb55346b30888ce1b7b18565a719f78b
      
https://github.com/qemu/qemu/commit/1085a44ebb55346b30888ce1b7b18565a719f78b
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M system/physmem.c

  Log Message:
  -----------
  system/physmem: Reduce cpu_physical_memory_clear_dirty_range() scope

cpu_physical_memory_clear_dirty_range() is now only called within
system/physmem.c, by qemu_ram_resize(). Reduce its scope by making
it internal to this file. Since it doesn't involve any CPU, remove
the 'cpu_' prefix. As it operates on a range, rename @start as @addr.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-16-phi...@linaro.org>


  Commit: 8bf3a883088b65430f58aeb3d2d1db87f01eabec
      
https://github.com/qemu/qemu/commit/8bf3a883088b65430f58aeb3d2d1db87f01eabec
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M include/system/ram_addr.h
    M migration/ram.c

  Log Message:
  -----------
  system/physmem: Reduce cpu_physical_memory_sync_dirty_bitmap() scope

cpu_physical_memory_sync_dirty_bitmap() is now only called within
system/physmem.c, by ramblock_sync_dirty_bitmap(). Reduce its scope
by making it internal to this file. Since it doesn't involve any CPU,
remove the 'cpu_' prefix.
Remove the now unneeded "qemu/rcu.h" and "system/memory.h" headers.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20251001175448.18933-17-phi...@linaro.org>


  Commit: aa60bdb700f4afa8577a495c734870516910864f
      
https://github.com/qemu/qemu/commit/aa60bdb700f4afa8577a495c734870516910864f
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M accel/kvm/kvm-all.c
    M accel/tcg/cputlb.c
    M hw/vfio/container-legacy.c
    M hw/vfio/container.c
    M include/system/ram_addr.h
    M migration/ram.c
    M system/memory.c
    M system/memory_ldst.c.inc
    M system/physmem.c
    M target/arm/tcg/mte_helper.c
    M tests/tsan/ignore.tsan

  Log Message:
  -----------
  system/physmem: Drop 'cpu_' prefix in Physical Memory API

The functions related to the Physical Memory API declared
in "system/ram_addr.h" do not operate on vCPU. Remove the
'cpu_' prefix.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Message-Id: <20251001175448.18933-18-phi...@linaro.org>


  Commit: 4db362f68c7cd28a6b1aa2f9ada68aa3556f9613
      
https://github.com/qemu/qemu/commit/4db362f68c7cd28a6b1aa2f9ada68aa3556f9613
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M MAINTAINERS
    M accel/kvm/kvm-all.c
    M accel/tcg/cputlb.c
    M hw/vfio/container-legacy.c
    M hw/vfio/container.c
    M hw/vfio/listener.c
    A include/system/physmem.h
    M include/system/ram_addr.h
    M migration/ram.c
    M system/memory.c
    M system/physmem.c
    M target/arm/tcg/mte_helper.c

  Log Message:
  -----------
  system/physmem: Extract API out of 'system/ram_addr.h' header

Very few files use the Physical Memory API. Declare its
methods in their own header: "system/physmem.h".

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Cédric Le Goater <c...@redhat.com>
Message-Id: <20251001175448.18933-19-phi...@linaro.org>


  Commit: 547d94ffc62a96736953c35c94c7916181805895
      
https://github.com/qemu/qemu/commit/547d94ffc62a96736953c35c94c7916181805895
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .gitpublish

  Log Message:
  -----------
  .gitpublish: use origin/master as default base

This is very much the result of my recent fat finger but I think it's
safer to assume that origin/master points to a recent commit (or at
least a commit a given branch is based on) than master.

Acked-by: Stefan Hajnoczi <stefa...@redhat.com>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-2-alex.ben...@linaro.org>


  Commit: 43a1c177426ff1babb863b3c45281fbc9f47f130
      
https://github.com/qemu/qemu/commit/43a1c177426ff1babb863b3c45281fbc9f47f130
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .gitmodules

  Log Message:
  -----------
  .gitmodules: restore qemu-project mirror of u-boot

With this change also reference the upstream repo.

Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-3-alex.ben...@linaro.org>


  Commit: 88091789f0d6234d9050c1c7a2dfc2515044ece0
      
https://github.com/qemu/qemu/commit/88091789f0d6234d9050c1c7a2dfc2515044ece0
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .gitmodules

  Log Message:
  -----------
  .gitmodules: restore qemu-project mirror of u-boot-sam460ex

With this change also reference the upstream repo.

Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-4-alex.ben...@linaro.org>


  Commit: 3d8c04b0eee35b7345c34c5265bb0478fcfc90ac
      
https://github.com/qemu/qemu/commit/3d8c04b0eee35b7345c34c5265bb0478fcfc90ac
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/docker/dockerfiles/debian-i686-cross.docker
    M tests/lcitool/refresh

  Log Message:
  -----------
  tests/lcitool: drop 64 bit guests from i686 cross build

With only TCG available we can't support 64 bit guests on a 32 bit
host.

Fixes: 5c27baf9519 (docs/about/deprecated: Deprecate 32-bit x86 hosts for 
system emulation)
Reviewed-by: Marc-André Lureau <marcandre.lur...@redhat.com>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-5-alex.ben...@linaro.org>


  Commit: 07a58aac21c80c3b74b2955ea9f9ba02070be75b
      
https://github.com/qemu/qemu/commit/07a58aac21c80c3b74b2955ea9f9ba02070be75b
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M scripts/ci/setup/gitlab-runner.yml
    M scripts/ci/setup/ubuntu/build-environment.yml
    R scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
    R scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
    A scripts/ci/setup/ubuntu/ubuntu-2404-aarch64.yaml
    A scripts/ci/setup/ubuntu/ubuntu-2404-s390x.yaml
    M tests/lcitool/refresh

  Log Message:
  -----------
  tests/lcitool: bump custom runner packages to Ubuntu 24.04

In anticipation of new runners lets move to a newer Ubuntu LTS.

Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-6-alex.ben...@linaro.org>


  Commit: eafc5f69e621725dcdcedcc1955d820af7abfc82
      
https://github.com/qemu/qemu/commit/eafc5f69e621725dcdcedcc1955d820af7abfc82
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .gitlab-ci.d/custom-runners.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-s390x.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-aarch32.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-aarch64.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-s390x.yml

  Log Message:
  -----------
  gitlab: move custom runners to Ubuntu 24.04

Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-7-alex.ben...@linaro.org>


  Commit: 1f3a37ae1c170114ae2730176b4a8cba73abb620
      
https://github.com/qemu/qemu/commit/1f3a37ae1c170114ae2730176b4a8cba73abb620
  Author: Alex Bennée <alex.ben...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M scripts/ci/setup/gitlab-runner.yml
    M scripts/ci/setup/vars.yml.template

  Log Message:
  -----------
  scripts/ci: use recommended registration command

The registration-token method is being deprecated:

  https://docs.gitlab.com/ci/runners/new_creation_workflow/

As a result we can drop a bunch of the descriptive stuff as that is
entered on the web UI. We don't need a secondary runner if we just
create one with both aarch64 and aarch32 tags.

Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Message-ID: <20251001170947.2769296-8-alex.ben...@linaro.org>


  Commit: 75b1786996c422878d09bd12f166004a7d32e459
      
https://github.com/qemu/qemu/commit/75b1786996c422878d09bd12f166004a7d32e459
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/Makefile.include

  Log Message:
  -----------
  tests/functional: Re-activate the check-venv target

Add check-venv target as a dependency for the functional tests. This
causes Python modules listed in pythondeps.toml, under the testdeps
group, to be installed when 'make check-functional{-<ARCH>}' is executed
to prepare and run the functional tests.

Suggested-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-2-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: c8f24e1b95430759f79223dc75c66fa7ec3ef2ee
      
https://github.com/qemu/qemu/commit/c8f24e1b95430759f79223dc75c66fa7ec3ef2ee
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M pythondeps.toml

  Log Message:
  -----------
  python: Install pygdbmi in meson's venv

The upcoming changes in the reverse_debugging functional test to remove
Avocado as a dependency will require pygdbmi for interacting with GDB,
so install it in meson's venv (located in the build dir's pyvenv/).

Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-3-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: b46b3818cf8d838991b15f20d3cb747b71ce040e
      
https://github.com/qemu/qemu/commit/b46b3818cf8d838991b15f20d3cb747b71ce040e
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M configure
    M meson_options.txt
    M scripts/meson-buildoptions.sh
    M tests/functional/meson.build

  Log Message:
  -----------
  tests/functional: Provide GDB to the functional tests

The probe of GDB is done in 'configure' and the full path is passed to
meson.build via the -Dgdb=option.

Meson then can pass the location of GDB to the functional tests via an
environment variable: QEMU_TEST_GDB.

Signed-off-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-4-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: aa7b1b726a0009c9147d9e2f64e0f6e82d4394af
      
https://github.com/qemu/qemu/commit/aa7b1b726a0009c9147d9e2f64e0f6e82d4394af
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/qemu_test/__init__.py
    A tests/functional/qemu_test/gdb.py

  Log Message:
  -----------
  tests/functional: Add GDB class

Add GDB class, which provides methods to run GDB commands and capture
their output. The GDB class is a wrapper around the pygdbmi module and
interacts with GDB via GDB's machine interface (MI).

Acked-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-5-gustavo.rom...@linaro.org>
[AJB: trimmed excess license text]
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: a0ad64c390b19242ae1d246d1ccfff77dcc752a4
      
https://github.com/qemu/qemu/commit/a0ad64c390b19242ae1d246d1ccfff77dcc752a4
  Author: Daniel P. Berrangé <berra...@redhat.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/reverse_debugging.py

  Log Message:
  -----------
  tests/functional: replace avocado process with subprocess

The standard python subprocess.check_call method is better than
avocado.utils.process as it doesn't require stuffing all args
into a single string.

Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-ID: <20251003141820.85278-6-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: db205774d1b2dc8e3a0e925f090a5b2f59b9bb70
      
https://github.com/qemu/qemu/commit/db205774d1b2dc8e3a0e925f090a5b2f59b9bb70
  Author: Daniel P. Berrangé <berra...@redhat.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/reverse_debugging.py

  Log Message:
  -----------
  tests/functional: drop datadrainer class in reverse debugging

The reverse debugging test uses the avocado datadrainer class to
create a background thread that reads from the console socket and
dumps it via python logger.

Most tests log console output as a side effect of doing calls
to match strings, but this test never tries to match anything.

This isn't critical, so just drop the functionality.

Signed-off-by: Daniel P. Berrangé <berra...@redhat.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
Reviewed-by: Thomas Huth <th...@redhat.com>
Message-ID: <20251003141820.85278-7-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: fb8f35949384c3a00ef56528cb43e851c95268e6
      
https://github.com/qemu/qemu/commit/fb8f35949384c3a00ef56528cb43e851c95268e6
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/qemu_test/__init__.py
    M tests/functional/qemu_test/decorators.py

  Log Message:
  -----------
  tests/functional: Add decorator to skip test on missing env vars

Add a decorator to skip tests on missing env variable(s). Multiple
variable names can be provided and if one or more of them are not set in
the test environment the test is skipped and the missing vars are
printed out.

Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-8-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: bddce216192122c51ff7fef171a16af9da514b61
      
https://github.com/qemu/qemu/commit/bddce216192122c51ff7fef171a16af9da514b61
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/reverse_debugging.py

  Log Message:
  -----------
  tests/functional: Adapt reverse_debugging to run w/o Avocado

This commit removes Avocado as a dependency for running the
reverse_debugging test.

The main benefit, beyond eliminating an extra dependency, is that there
is no longer any need to handle GDB packets manually. This removes the
need for ad-hoc functions dealing with endianness and arch-specific
register numbers, making the test easier to read. The timeout variable
is also removed, since Meson now manages timeouts automatically.

reverse_debugging now uses the pygdbmi module to interact with GDB, if
it is available in the test environment, otherwise the test is skipped.
GDB is detect via the QEMU_TEST_GDB env. variable.

This commit also significantly improves the output for the test and
now prints all the GDB commands used in sequence. It also adds
some clarifications to existing comments, for example, clarifying that
once the replay-break is reached, a SIGINT is captured in GDB.

reverse_debugging is kept "skipped" for aarch64, ppc64, and x86_64, so
won't run unless QEMU_TEST_FLAKY_TESTS=1 is set in the test environment,
before running 'make check-functional' or 'meson test [...]'.

Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-9-gustavo.rom...@linaro.org>
[AJB: it is and broke long line]
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>
Tested-by: Thomas Huth <th...@redhat.com>


  Commit: 4d3eb329ccf34da76b0b7822eecaaacc6e6fe646
      
https://github.com/qemu/qemu/commit/4d3eb329ccf34da76b0b7822eecaaacc6e6fe646
  Author: Gustavo Romero <gustavo.rom...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/aarch64/test_reverse_debug.py
    M tests/functional/ppc64/test_reverse_debug.py
    M tests/functional/x86_64/test_reverse_debug.py

  Log Message:
  -----------
  tests/functional: Adapt arches to reverse_debugging w/o Avocado

reverse_debugging no longer depends on Avocado, so remove the import
checks for Avocado, the per-arch endianness tweaks, and the per-arch
register settings. All of these are now handled in the ReverseDebugging
class, automatically.

Reviewed-by: Thomas Huth <th...@redhat.com>
Reviewed-by: Daniel P. Berrangé <berra...@redhat.com>
Signed-off-by: Gustavo Romero <gustavo.rom...@linaro.org>
Message-ID: <20251003141820.85278-10-gustavo.rom...@linaro.org>
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: 41f8f2be27736192bab29aa38380c9ebaae810fa
      
https://github.com/qemu/qemu/commit/41f8f2be27736192bab29aa38380c9ebaae810fa
  Author: Vladimir Lukianov <1844...@gmail.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M replay/replay.c
    M tests/functional/aarch64/test_reverse_debug.py

  Log Message:
  -----------
  record/replay: fix race condition on test_aarch64_reverse_debug

Ensures EVENT_INSTRUCTION written to replay.bin before EVENT_SHUTDOWN_HOST_QMP

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2921
Signed-off-by: Vladimir Lukianov <1844...@gmail.com>
Message-ID: <20250603125459.17688-1-1844...@gmail.com>
[AJB: fix re-base file mode]
Signed-off-by: Alex Bennée <alex.ben...@linaro.org>


  Commit: a23e719ca8e80d22eafe4b2b57833918d439fa0c
      
https://github.com/qemu/qemu/commit/a23e719ca8e80d22eafe4b2b57833918d439fa0c
  Author: Peter Maydell <peter.mayd...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Don't set HCR.RW for AArch32 only CPUs

In commit 39ec3fc0301 we fixed a bug where we were not implementing
HCR_EL2.RW as RAO/WI for CPUs where EL1 doesn't support AArch32.
However, we got the condition wrong, so we now set this bit even on
CPUs which have no AArch64 support at all.  This is wrong because the
AArch32 HCR register defines this bit as RES0.

Correct the condition we use for forcing HCR_RW to be set.

Cc: qemu-sta...@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3128
Fixes: 39ec3fc0301 ("target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't 
support AArch32")
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
Message-id: 20250925115723.1293233-1-peter.mayd...@linaro.org


  Commit: 3471ae96b10bc0a1efeeeff85aea7a823cb57f77
      
https://github.com/qemu/qemu/commit/3471ae96b10bc0a1efeeeff85aea7a823cb57f77
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    A include/hw/arm/xlnx-versal-version.h
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: split the xlnx-versal type

Split the xlnx-versal device into two classes, a base, abstract class
and the existing concrete one. Introduce a VersalVersion type that will
be used across several device models when versal2 implementation is
added.

This is in preparation for versal2 implementation.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-2-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d82be8c5de7a8bc1602b89678e69312c1716bd10
      
https://github.com/qemu/qemu/commit/d82be8c5de7a8bc1602b89678e69312c1716bd10
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: prepare for FDT creation

The following commits will move FDT creation logic from the
xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by
passing the FDT handle to the SoC before it is realized.

For now the SoC only creates the two clock nodes. The ones from the
xlnx-versal virt machine are renamed with a `old-' prefix and will be
removed once they are not referenced anymore.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-3-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 288dc87244c97c8674967c12bb5c8e38fd7d9ff5
      
https://github.com/qemu/qemu/commit/288dc87244c97c8674967c12bb5c8e38fd7d9ff5
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: uart: refactor creation

Refactor the UARTs creations. The VersalMap struct is now used to
describe the SoC and its peripherals. For now it contains the two UARTs
mapping information. The creation function now embeds the FDT creation
logic as well. The devices are now created dynamically using qdev_new
and (qdev|sysbus)_realize_and_unref.

This will allow to rely entirely on the VersalMap structure to create
the SoC and allow easy addition of new SoCs of the same family (like
versal2 coming with next commits).

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-4-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d70df574d67c459521f7b93fae42451b8e83bbea
      
https://github.com/qemu/qemu/commit/d70df574d67c459521f7b93fae42451b8e83bbea
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: canfd: refactor creation

Refactor the CAN controllers creation using the VersalMap structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

The xlnx-versal-virt machine now dynamically creates the correct amount
of CAN bus link properties based on the number of CAN controller
advertised by the SoC.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-5-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b392177e42e25b076104eb8fe3a484a9a16642c7
      
https://github.com/qemu/qemu/commit/b392177e42e25b076104eb8fe3a484a9a16642c7
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: sdhci: refactor creation

Refactor the SDHCI controllers creation using the VersalMap structure.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-6-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 8aaeb96405d2e4b6593cb9d5d943a54e36cbccbc
      
https://github.com/qemu/qemu/commit/8aaeb96405d2e4b6593cb9d5d943a54e36cbccbc
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: gem: refactor creation

Refactor the GEM ethernet controllers creation using the VersalMap
structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

The FDT nodes are created in reverse order compared to the devices
creation to keep backward compatibility with the previous generated
FDTs.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-7-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 51668b79be5ac5d490ffc7fcde2a95f9a2460997
      
https://github.com/qemu/qemu/commit/51668b79be5ac5d490ffc7fcde2a95f9a2460997
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: adma: refactor creation

Refactor the ADMA creation using the VersalMap structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-8-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3d10ac78480f4bdb17b908733fa9d2cf30ea2939
      
https://github.com/qemu/qemu/commit/3d10ac78480f4bdb17b908733fa9d2cf30ea2939
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: xram: refactor creation

Refactor the XRAM devices creation using the VersalMap structure.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-9-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a0b535a57b28fe2c58481fb07e17b2f4a5dcae2e
      
https://github.com/qemu/qemu/commit/a0b535a57b28fe2c58481fb07e17b2f4a5dcae2e
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: usb: refactor creation

Refactor the USB controller creation using the VersalMap structure.

Note that the connection to the CRL is removed for now and will be
re-added by next commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-10-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 98cb650c5cd73e28ec389373dcc7a656bf70368a
      
https://github.com/qemu/qemu/commit/98cb650c5cd73e28ec389373dcc7a656bf70368a
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: efuse: refactor creation

Refactore the eFuse devices creation using the VersalMap structure.

Note that the corresponding FDT nodes are removed. They do not
correspond to any real node in standard Versal DTBs. No matching drivers
exist for them.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-11-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 6532bc7cc7f5560b7782a2799d9d5f0ac2719c42
      
https://github.com/qemu/qemu/commit/6532bc7cc7f5560b7782a2799d9d5f0ac2719c42
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: ospi: refactor creation

Refactor the OSPI controller creation using the VersalMap structure.

Note that the connection to the PMC IOU SLCR is removed for now and will
be re-added by next commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-12-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 1bec18fc13dce2f9a066fcb52b5d15b6d3141499
      
https://github.com/qemu/qemu/commit/1bec18fc13dce2f9a066fcb52b5d15b6d3141499
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: VersalMap: add support for OR'ed IRQs

Improve the IRQ index in the VersalMap structure to turn it into a
descriptor:
   - the lower 16 bits still represent the IRQ index
   - bit 18 is used to indicate a shared IRQ connected to a OR gate
   - bits 19 to 22 indicate the index on the OR gate.

This allows to share an IRQ among multiple devices. An OR gate is
created to connect the devices to the actual IRQ pin.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-13-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 482f95526a52eff123b810953b6f5eb9674e279b
      
https://github.com/qemu/qemu/commit/482f95526a52eff123b810953b6f5eb9674e279b
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: PMC IOU SCLR: refactor creation

Refactor the PMC IOU SLCR device creation using the VersalMap structure.
This is the first user of a shared IRQ using an OR gate. The OSPI
controller is reconnected to the SLCR.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-14-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c58d45a2b9d62638b94cc003c61603f5030dcba7
      
https://github.com/qemu/qemu/commit/c58d45a2b9d62638b94cc003c61603f5030dcba7
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: bbram: refactor creation

Refactor the BBRAM device creation using the VersalMap structure.

Note that the corresponding FDT node is removed. It does not correspond
to any real node in standard Versal DTBs. No matching drivers exist for
it.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-15-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 060b809271f9d0d6205fe2232d0aead4a37fa0e7
      
https://github.com/qemu/qemu/commit/060b809271f9d0d6205fe2232d0aead4a37fa0e7
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: trng: refactor creation

Refactor the TRNG device creation using the VersalMap structure.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-16-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 176faad4bf7565966398df0d6e8cd05825dfceea
      
https://github.com/qemu/qemu/commit/176faad4bf7565966398df0d6e8cd05825dfceea
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: rtc: refactor creation

Refactor the RTC device creation using the VersalMap structure.

The sysbus IRQ output 0 (APB IRQ) is connected instead of the output 1
(addr error IRQ). This does not change the current behaviour since the
RTC model does not implement those IRQs anyway.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-17-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b913b3cb26d531f71ccf89e886c0d0f520e80077
      
https://github.com/qemu/qemu/commit/b913b3cb26d531f71ccf89e886c0d0f520e80077
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: cfu: refactor creation

Refactor the CFU device creation using the VersalMap structure. All
users of the APB IRQ OR gate have now been converted. The OR gate device
can be dropped.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-18-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: aaf889ebdc6ed054a975465fee18feea2450c446
      
https://github.com/qemu/qemu/commit/aaf889ebdc6ed054a975465fee18feea2450c446
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: crl: refactor creation

Refactor the CRL device creation using the VersalMap structure. The
connections to the RPU CPUs are temporarily removed and will be
reintroduced with next refactoring commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-19-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e17df660769d24dc6d5d0c75ab4de16033705924
      
https://github.com/qemu/qemu/commit/e17df660769d24dc6d5d0c75ab4de16033705924
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal-virt: virtio: refactor creation

Refactor the creation of virtio devices. Use the accessors provided by
the Versal SoC to retrieve the reserved MMIO and IRQ space. Those are
defined in the VersalMap structure.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-20-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 7c21633676fe3249cb8af80e3831bffea1457242
      
https://github.com/qemu/qemu/commit/7c21633676fe3249cb8af80e3831bffea1457242
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: refactor CPU cluster creation

Refactor the CPU cluster creation using the VersalMap structure. There
is no functional change. The clusters properties are now described in
the VersalMap structure. For now only the APU is converted. The RPU will
be taken care of by next commits.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-21-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c2ba2adf2dc0f51146f70eaeb32c84932573a906
      
https://github.com/qemu/qemu/commit/c2ba2adf2dc0f51146f70eaeb32c84932573a906
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: add the mp_affinity property to the CPU mapping

Add a way to configure the MP affinity value of the CPUs given their
core and cluster IDs. For the Versal APU CPUs, the MP affinity value is
given by the core ID in Aff0.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-22-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 6926b0b26071ce740f026212f5c437a694117645
      
https://github.com/qemu/qemu/commit/6926b0b26071ce740f026212f5c437a694117645
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: instantiate the GIC ITS in the APU

Add the instance of the GIC ITS in the APU.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-23-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 27493e5e687e65829f548bf0145dd44bc223fbe5
      
https://github.com/qemu/qemu/commit/27493e5e687e65829f548bf0145dd44bc223fbe5
  Author: Francisco Iglesias <francisco.igles...@xilinx.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_kvm.c
    M include/hw/intc/arm_gicv3_common.h

  Log Message:
  -----------
  hw/intc/arm_gicv3: Introduce a 'first-cpu-index' property

Introduce a 'first-cpu-index' property for specifying the first QEMU CPU
connected to the GICv3. This makes it possible to have multiple instances
of the GICv3 connected to different CPU clusters.

For KVM, mark this property has unsupported. It probably does not make
much sense as it is intented to be used to model non-SMP systems.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Signed-off-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Sai Pavan Boddu <sai.pavan.bo...@amd.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-24-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: d95bf385567dc635f4cf275af118f3774e3b3d29
      
https://github.com/qemu/qemu/commit/d95bf385567dc635f4cf275af118f3774e3b3d29
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: add support for multiple GICs

The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in
the RPU (currently not instantiated). To prepare for the GICv2
instantiation, add support for multiple GICs when connecting interrupts.

When a GIC is created, the first-cpu-index property is set on it, and a
pointer to the GIC is stored in the intc array. When connecting an IRQ,
a TYPE_SPLIT_IRQ device is created with its num-lines property set to
the number of GICs in the SoC. The split device is used to fan out the
IRQ to all the GICs.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-25-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0dfff625b5dafcb6cd722dd094ddc54c031e9169
      
https://github.com/qemu/qemu/commit/0dfff625b5dafcb6cd722dd094ddc54c031e9169
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: add support for GICv2

Add support for GICv2 instantiation in the Versal SoC. This is in
preparation for the RPU refactoring.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-26-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 805bdea08a17db38f0d860f9acad2eb3cf8e6fb5
      
https://github.com/qemu/qemu/commit/805bdea08a17db38f0d860f9acad2eb3cf8e6fb5
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: rpu: refactor creation

Refactor the RPU cluster creation using the VersalMap structure. This
effectively instantiate the RPU GICv2 which was not instantiated before.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-27-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: cf8f12b6e719dca00e015febb5d5bbb1f3d6aa7f
      
https://github.com/qemu/qemu/commit/cf8f12b6e719dca00e015febb5d5bbb1f3d6aa7f
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: ocm: refactor creation

Refactor the OCM creation using the VersalMap structure.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-28-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e4a9bc0aae9f98c64a9689f9471234636e6d3ae0
      
https://github.com/qemu/qemu/commit/e4a9bc0aae9f98c64a9689f9471234636e6d3ae0
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: ddr: refactor creation

Refactor the DDR aperture regions creation using the VersalMap
structure. Device creation and FDT node creation are split into two
functions because the later must happen during ARM virtual bootloader
modify_dtb callback.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-29-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 87830c4dd626804072181cf126daa206c5721dc4
      
https://github.com/qemu/qemu/commit/87830c4dd626804072181cf126daa206c5721dc4
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: add the versal_get_num_cpu accessor

Add the versal_get_num_cpu accessor to the Versal SoC to retrieve the
number of CPUs in the SoC. Use it in the xlnx-versal-virt machine.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-30-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3074e35115f51387d26774a37d79ca761721fb5c
      
https://github.com/qemu/qemu/commit/3074e35115f51387d26774a37d79ca761721fb5c
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/misc/xlnx-versal-crl.c

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: remove unnecessary include directives

Drop unused include directives from xlnx-versal-crl.c

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-31-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: c27ca57288109b434a464b8ee8d05ec4a387e468
      
https://github.com/qemu/qemu/commit/c27ca57288109b434a464b8ee8d05ec4a387e468
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/misc/xlnx-versal-crl.c
    M include/hw/misc/xlnx-versal-crl.h

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: split into base/concrete classes

Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This
is in preparation for the versal2 version of the CRL.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-32-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ff789d1556af9994494f0bebf7191b50eaacc126
      
https://github.com/qemu/qemu/commit/ff789d1556af9994494f0bebf7191b50eaacc126
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/misc/xlnx-versal-crl.c
    M include/hw/misc/xlnx-versal-crl.h

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: refactor device reset logic

Refactor the device reset logic to have a common register write callback
for all the devices. This uses a decode function to map the register
address to the actual peripheral to reset. This refactoring changes the
CPU property name from cpu_r5[*] to rpu[*] to ease with the connections
in the Versal SoC. It also fixes a bug where the gem device pointer
was mapped to the usb link property.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-33-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 9401022bcddf3de377c5d64a68dad59b493a1315
      
https://github.com/qemu/qemu/commit/9401022bcddf3de377c5d64a68dad59b493a1315
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: reconnect the CRL to the other devices

The CRL connects to various devices through link properties to be able
to reset them. The connections were dropped during the SoC refactoring.
Reintroduce them now.

Rely on the QOM tree to retrieve the devices to connect. The component
parts of the device names are chosen to match the properties on the CRL.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-34-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 48111f7e7266cc94816507bf8c82d8986edfec9c
      
https://github.com/qemu/qemu/commit/48111f7e7266cc94816507bf8c82d8986edfec9c
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: use hw/arm/bsa.h for timer IRQ indices

Use the bsa.h header for ARM timer and maintainance IRQ indices instead
of redefining our owns.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-35-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 4707024bc3362f4b9859214357a687b9154c84cf
      
https://github.com/qemu/qemu/commit/4707024bc3362f4b9859214357a687b9154c84cf
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: tidy up

Remove now unused macros in xlnx-versal.[ch]. Those macros have been
replaced by the VersalMap structure that serves as a central description
for the SoC. The ones still in use in the versal_unimp function are
inlined.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-36-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 00580a9d715138ec1560b91c596dedee07286fee
      
https://github.com/qemu/qemu/commit/00580a9d715138ec1560b91c596dedee07286fee
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/misc/xlnx-versal-crl.c
    M include/hw/arm/xlnx-versal-version.h
    M include/hw/misc/xlnx-versal-crl.h

  Log Message:
  -----------
  hw/misc/xlnx-versal-crl: add the versal2 version

Add the versal2 version of the CRL device. For the implemented part, it
is similar to the versal version but drives reset line of more devices.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-37-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 268f7a3d24a73b94bfab1dd86c6b41f7afd196fc
      
https://github.com/qemu/qemu/commit/268f7a3d24a73b94bfab1dd86c6b41f7afd196fc
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: add a per_cluster_gic switch to VersalCpuClusterMap

Add the per_cluster_gic switch to the VersalCpuClusterMap structure.
When set, this indicates that a GIC instance should by created
per-cluster instead of globally for the whole RPU or APU. This is in
preparation for versal2.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-38-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 16aa53c971c4a2fef5608f8aac372dd03305f0d2
      
https://github.com/qemu/qemu/commit/16aa53c971c4a2fef5608f8aac372dd03305f0d2
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c

  Log Message:
  -----------
  hw/arm/xlnx-versal: add the target field in IRQ descriptor

Add the target field in the IRQ descriptor. This allows to target an IRQ
to another IRQ controller than the GIC(s). Other supported targets are
the PMC PPU1 CPU interrupt controller and the EAM (Error management)
device. Those two devices are currently not implemented so IRQs
targeting those will be left unconnected. This is in preparation for
versal2.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-39-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0252b88c796d05ffbfefe57d4c8f7dc7a69556dd
      
https://github.com/qemu/qemu/commit/0252b88c796d05ffbfefe57d4c8f7dc7a69556dd
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm/tcg/cpu64: add the cortex-a78ae CPU

Add support for the ARM Cortex-A78AE CPU.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-40-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 8cd160dccf763b6680a8c7c6b503965d5aa04cbd
      
https://github.com/qemu/qemu/commit/8cd160dccf763b6680a8c7c6b503965d5aa04cbd
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal.c
    M include/hw/arm/xlnx-versal.h

  Log Message:
  -----------
  hw/arm/xlnx-versal: add versal2 SoC

Add the Versal Gen 2 (versal2) version of the Versal SoC family.
This version embeds up to 8 Cortex-A78AE cores (split into 4 clusters)
and 10 Cortex-R52 cores (split into 5 clusters). The similarities
between versal and versal2 in term of architecture allow to reuse the
VersalMap structure to almost fully describe the implemented parts of
versal2.

The versal2 eFuse device differs quite a lot from the versal one and is
left as future work.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-41-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 84a759c3d24baf13bbf3e95667280758ebb70545
      
https://github.com/qemu/qemu/commit/84a759c3d24baf13bbf3e95667280758ebb70545
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/system/arm/xlnx-versal-virt.rst
    M hw/arm/xlnx-versal-virt.c
    M tests/functional/aarch64/test_xlnx_versal.py

  Log Message:
  -----------
  hw/arm/xlnx-versal-virt: rename the machine to amd-versal-virt

To align with current branding and ensure coherency with the upcoming
versal2 machine, rename the xlnx-versal-virt machine to amd-versal-virt.
Keep an alias of the old name to the new one for command-line backward
compatibility.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-42-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ea7028b87b62c4e93f4c2455760253a224626773
      
https://github.com/qemu/qemu/commit/ea7028b87b62c4e93f4c2455760253a224626773
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm/xlnx-versal-virt: split into base/concrete classes

Split the xlnx-versal-virt machine type into a base abstract type and a
concrete type. There is no functional change. This is in preparation for
the versal2 machine.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-43-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e2e9b9e129f484398326f262de2933a3db3f8c62
      
https://github.com/qemu/qemu/commit/e2e9b9e129f484398326f262de2933a3db3f8c62
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm/xlnx-versal-virt: tidy up

Remove now unused clock nodes. They have been replaced by the ones
created in the SoC. Remove the unused cfg.secure VersalVirt field.
Remove unecessary include directives.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-44-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0ec8c4296d48efc0a9ee7ac7bdc7523b793de4bd
      
https://github.com/qemu/qemu/commit/0ec8c4296d48efc0a9ee7ac7bdc7523b793de4bd
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/system/arm/xlnx-versal-virt.rst

  Log Message:
  -----------
  docs/system/arm/xlnx-versal-virt: update supported devices

Update the list of supported devices in the Versal SoCs.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-45-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 39cf696fc57a74a40beafaa1d341d4ef9b41bbd0
      
https://github.com/qemu/qemu/commit/39cf696fc57a74a40beafaa1d341d4ef9b41bbd0
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/system/arm/xlnx-versal-virt.rst

  Log Message:
  -----------
  docs/system/arm/xlnx-versal-virt: add a note about dumpdtb

Add a note in the DTB section explaining how to dump the generated DTB
using the dumpdtb machine option.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-46-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 3429cdd8bfe6ee8239ea19d0f8211c671832e44b
      
https://github.com/qemu/qemu/commit/3429cdd8bfe6ee8239ea19d0f8211c671832e44b
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/system/arm/xlnx-versal-virt.rst
    M hw/arm/xlnx-versal-virt.c

  Log Message:
  -----------
  hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine

Add the Versal Gen 2 Virtual development machine embedding a
versal2 SoC. This machine follows the same principle than the
xlnx-versal-virt machine. It creates its own DTB and feeds it to the
software payload. This way only implemented devices are exposed to the
guest and the user does not need to provide a DTB.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-47-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f1924af144115a159f854500f134c3769ec388df
      
https://github.com/qemu/qemu/commit/f1924af144115a159f854500f134c3769ec388df
  Author: Luc Michel <luc.mic...@amd.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M tests/functional/aarch64/test_xlnx_versal.py

  Log Message:
  -----------
  tests/functional/test_aarch64_xlnx_versal: test the versal2 machine

Add a test for the amd-versal2-virt machine using the same command line,
kernel, initrd than the ones used for amd-versal-virt.

Signed-off-by: Luc Michel <luc.mic...@amd.com>
Reviewed-by: Francisco Iglesias <francisco.igles...@amd.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Tested-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20250926070806.292065-48-luc.mic...@amd.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: b94246a252a3c04424269928a465d3fac02115e8
      
https://github.com/qemu/qemu/commit/b94246a252a3c04424269928a465d3fac02115e8
  Author: Clément Chigot <chi...@adacore.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header

This define will be needed in a later patch in XlnxZynqMPState
structure, hence move it within xlnx-zynqmp header.

Add XLXN_ZYNQMP prefix as it's now public.

Signed-off-by: Clément Chigot <chi...@adacore.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Message-id: 20250930115718.437100-2-chi...@adacore.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: f51ad36255516a5d41e05734e918b32885923151
      
https://github.com/qemu/qemu/commit/f51ad36255516a5d41e05734e918b32885923151
  Author: Clément Chigot <chi...@adacore.com>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: introduce helper to compute RPU number

This helper will avoid repeating the MIN/MAX formula everytime the
number of RPUs available is requested.

Signed-off-by: Clément Chigot <chi...@adacore.com>
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Message-id: 20250930115718.437100-3-chi...@adacore.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e836211f7df4b7102f571a33bf01722c9b9bd8b8
      
https://github.com/qemu/qemu/commit/e836211f7df4b7102f571a33bf01722c9b9bd8b8
  Author: Frederic Konrad <konrad.frede...@yahoo.fr>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M hw/arm/xlnx-zynqmp.c
    M include/hw/arm/xlnx-zynqmp.h

  Log Message:
  -----------
  hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5

This wires a second GIC for the Cortex-R5, all the IRQs are split when there
is an RPU instanciated.

Signed-off-by: Clément Chigot <chi...@adacore.com>
Acked-by: Edgar E. Iglesias <edgar.igles...@amd.com>
Message-id: 20250930115718.437100-4-chi...@adacore.com
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: cedbe3b24a875c2abd84d1925abf3d288f753e33
      
https://github.com/qemu/qemu/commit/cedbe3b24a875c2abd84d1925abf3d288f753e33
  Author: Philippe Mathieu-Daudé <phi...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M MAINTAINERS
    M hw/gpio/zaurus.c
    R include/hw/arm/sharpsl.h

  Log Message:
  -----------
  hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header

When removing the spitz and tosa board, commit b62151489ae
("hw/arm: Remove deprecated akita, borzoi spitz, terrier,
tosa boards") removed the last calls to sl_bootparam_write().
Remove it, along with the "hw/arm/sharpsl.h" header.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Message-id: 20251001084047.67423-1-phi...@linaro.org
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 0407192ae6a06d649d693a9be5e864243e6de702
      
https://github.com/qemu/qemu/commit/0407192ae6a06d649d693a9be5e864243e6de702
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/cpu-features.h

  Log Message:
  -----------
  target/arm: Add isar feature test for FEAT_RME_GPC2

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-2-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: e2c25b123d48a9bb2d723f19a595914690e348b0
      
https://github.com/qemu/qemu/commit/e2c25b123d48a9bb2d723f19a595914690e348b0
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/cpu.h

  Log Message:
  -----------
  target/arm: Add GPCCR fields from ARM revision L.b

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-3-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: af95e2aaa0b00615728834a79de5c827158b3d9a
      
https://github.com/qemu/qemu/commit/af95e2aaa0b00615728834a79de5c827158b3d9a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/helper.c

  Log Message:
  -----------
  target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-4-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: bd08319bb52cd009f86e9a04af8810f6aa540d8c
      
https://github.com/qemu/qemu/commit/bd08319bb52cd009f86e9a04af8810f6aa540d8c
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Add cur_space to S1Translate

We've been updating in_space and then using hacks to access
the original space.  Instead, update cur_space and leave
in_space unchanged.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-5-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 11dee1cb2f075185ed93b38ad964995290630041
      
https://github.com/qemu/qemu/commit/11dee1cb2f075185ed93b38ad964995290630041
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: GPT_Secure is reserved without FEAT_SEL2

For GPT_Secure, if SEL2 is not enabled, raise a GPCF_Walk exception.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-6-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: ee45f4b4e9e58be886bb48b31ca58c2273f3630a
      
https://github.com/qemu/qemu/commit/ee45f4b4e9e58be886bb48b31ca58c2273f3630a
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Implement GPT_NonSecureOnly

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-7-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 59bcd13b64bf54b35acac8a364b569964d7e0461
      
https://github.com/qemu/qemu/commit/59bcd13b64bf54b35acac8a364b569964d7e0461
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Implement SPAD, NSPAD, RLPAD

These bits disable all access to a particular address space.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-8-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: a0f1bb0dfeb2c8cd806349aa5938d9aab6ef1d61
      
https://github.com/qemu/qemu/commit/a0f1bb0dfeb2c8cd806349aa5938d9aab6ef1d61
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Fix GPT fault type for address outside PPS

The GPT address size fault is for the table itself.  The physical
address being checked gets Granule protection fault at Level 0 (R_JFFHB).

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-9-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 663f9c253eb31d4deacacf5b9de70bfa4674371f
      
https://github.com/qemu/qemu/commit/663f9c253eb31d4deacacf5b9de70bfa4674371f
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M target/arm/ptw.c

  Log Message:
  -----------
  target/arm: Implement APPSAA

This bit allows all spaces to access memory above PPS.

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-10-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 932cac41ca633f24f192a69770bf91b55c4d27bb
      
https://github.com/qemu/qemu/commit/932cac41ca633f24f192a69770bf91b55c4d27bb
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M docs/system/arm/emulation.rst
    M target/arm/tcg/cpu64.c

  Log Message:
  -----------
  target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
Message-id: 20250926001134.295547-11-richard.hender...@linaro.org
Signed-off-by: Peter Maydell <peter.mayd...@linaro.org>


  Commit: 40e62b903ab847eca9ec1f266d4a60c5a3279344
      
https://github.com/qemu/qemu/commit/40e62b903ab847eca9ec1f266d4a60c5a3279344
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M MAINTAINERS
    M docs/system/arm/emulation.rst
    M docs/system/arm/xlnx-versal-virt.rst
    M hw/arm/xlnx-versal-virt.c
    M hw/arm/xlnx-versal.c
    M hw/arm/xlnx-zynqmp.c
    M hw/gpio/zaurus.c
    M hw/intc/arm_gicv3_common.c
    M hw/intc/arm_gicv3_cpuif.c
    M hw/intc/arm_gicv3_kvm.c
    M hw/misc/xlnx-versal-crl.c
    R include/hw/arm/sharpsl.h
    A include/hw/arm/xlnx-versal-version.h
    M include/hw/arm/xlnx-versal.h
    M include/hw/arm/xlnx-zynqmp.h
    M include/hw/intc/arm_gicv3_common.h
    M include/hw/misc/xlnx-versal-crl.h
    M target/arm/cpu-features.h
    M target/arm/cpu.h
    M target/arm/helper.c
    M target/arm/ptw.c
    M target/arm/tcg/cpu64.c
    M tests/functional/aarch64/test_xlnx_versal.py

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu into 
staging

target-arm queue:
 * target/arm: Don't set HCR.RW for AArch32 only CPUs
 * new board model: amd-versal2-virt
 * xlnx-zynqmp: model the GIC for the Cortex-R5 RPU cluster
 * hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header
 * Emulate FEAT_RME_GPC2

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# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 07 Oct 2025 07:10:08 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.mayd...@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.mayd...@linaro.org>" [unknown]
# gpg:                 aka "Peter Maydell <pmayd...@gmail.com>" [unknown]
# gpg:                 aka "Peter Maydell <pmayd...@chiark.greenend.org.uk>" 
[unknown]
# gpg:                 aka "Peter Maydell <pe...@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20251007' of https://gitlab.com/pm215/qemu: (62 commits)
  target/arm: Enable FEAT_RME_GPC2 for -cpu max with x-rme
  target/arm: Implement APPSAA
  target/arm: Fix GPT fault type for address outside PPS
  target/arm: Implement SPAD, NSPAD, RLPAD
  target/arm: Implement GPT_NonSecureOnly
  target/arm: GPT_Secure is reserved without FEAT_SEL2
  target/arm: Add cur_space to S1Translate
  target/arm: Enable FEAT_RME_GPC2 bits in gpccr_write
  target/arm: Add GPCCR fields from ARM revision L.b
  target/arm: Add isar feature test for FEAT_RME_GPC2
  hw/arm: Remove sl_bootparam_write() and 'hw/arm/sharpsl.h' header
  hw/arm/xlnx-zynqmp: wire a second GIC for the Cortex-R5
  hw/arm/xlnx-zynqmp: introduce helper to compute RPU number
  hw/arm/xlnx-zynqmp: move GIC_NUM_SPI_INTR define in header
  tests/functional/test_aarch64_xlnx_versal: test the versal2 machine
  hw/arm/xlnx-versal-virt: add the xlnx-versal2-virt machine
  docs/system/arm/xlnx-versal-virt: add a note about dumpdtb
  docs/system/arm/xlnx-versal-virt: update supported devices
  hw/arm/xlnx-versal-virt: tidy up
  hw/arm/xlnx-versal-virt: split into base/concrete classes
  ...

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 637a8b25a6ff233540b3d1b656359294f5dfb33f
      
https://github.com/qemu/qemu/commit/637a8b25a6ff233540b3d1b656359294f5dfb33f
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M MAINTAINERS
    M accel/kvm/kvm-all.c
    M accel/tcg/cputlb.c
    M docs/devel/loads-stores.rst
    M hw/core/loader.c
    M hw/hyperv/hv-balloon-our_range_memslots.c
    M hw/ppc/spapr.c
    M hw/ppc/spapr_caps.c
    M hw/ppc/spapr_pci.c
    M hw/remote/memory.c
    M hw/remote/proxy-memory-listener.c
    M hw/s390x/s390-stattrib-kvm.c
    M hw/s390x/s390-stattrib.c
    M hw/s390x/s390-virtio-ccw.c
    M hw/s390x/sclp.c
    M hw/vfio/container-legacy.c
    M hw/vfio/container.c
    M hw/vfio/listener.c
    M hw/vfio/spapr.c
    M hw/virtio/vhost.c
    M hw/virtio/virtio-balloon.c
    M hw/virtio/virtio-mem.c
    M hw/virtio/virtio.c
    M hw/xen/xen-hvm-common.c
    M include/exec/cpu-common.h
    M include/system/memory.h
    A include/system/physmem.h
    M include/system/ram_addr.h
    M include/system/ramblock.h
    M migration/ram.c
    M scripts/coccinelle/exec_rw_const.cocci
    M system/memory.c
    M system/memory_ldst.c.inc
    M system/physmem.c
    M target/arm/tcg/mte_helper.c
    M target/i386/arch_memory_mapping.c
    M target/i386/kvm/xen-emu.c
    M target/i386/nvmm/nvmm-all.c
    M target/i386/whpx/whpx-all.c
    M target/s390x/mmu_helper.c
    M tests/tsan/ignore.tsan

  Log Message:
  -----------
  Merge tag 'physmem-20251007' of https://github.com/philmd/qemu into staging

Memory patches

- Cleanups on RAMBlock API
- Cleanups on Physical Memory API
- Remove cpu_physical_memory_is_io()
- Remove cpu_physical_memory_rw()
- Legacy conversion [cpu_physical_memory -> address_space]_[un]map()

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# gpg: Signature made Mon 06 Oct 2025 08:04:21 PM PDT
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4...@amsat.org>" 
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* tag 'physmem-20251007' of https://github.com/philmd/qemu: (41 commits)
  system/physmem: Extract API out of 'system/ram_addr.h' header
  system/physmem: Drop 'cpu_' prefix in Physical Memory API
  system/physmem: Reduce cpu_physical_memory_sync_dirty_bitmap() scope
  system/physmem: Reduce cpu_physical_memory_clear_dirty_range() scope
  system/physmem: Un-inline cpu_physical_memory_dirty_bits_cleared()
  system/physmem: Un-inline cpu_physical_memory_set_dirty_lebitmap()
  system/physmem: Remove _WIN32 #ifdef'ry
  system/physmem: Un-inline cpu_physical_memory_set_dirty_range()
  system/physmem: Un-inline cpu_physical_memory_set_dirty_flag()
  system/physmem: Un-inline cpu_physical_memory_range_includes_clean()
  system/physmem: Un-inline cpu_physical_memory_is_clean()
  system/physmem: Un-inline cpu_physical_memory_get_dirty_flag()
  hw: Remove unnecessary 'system/ram_addr.h' header
  target/arm/tcg/mte: Include missing 'exec/target_page.h' header
  hw/vfio/listener: Include missing 'exec/target_page.h' header
  hw/s390x/s390-stattrib: Include missing 'exec/target_page.h' header
  accel/kvm: Include missing 'exec/target_page.h' header
  system/ram_addr: Remove unnecessary 'exec/cpu-common.h' header
  hw/virtio/virtio: Replace legacy cpu_physical_memory_map() call
  hw/virtio/vhost: Replace legacy cpu_physical_memory_*map() calls
  ...

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


  Commit: 37ad0e48e9fd58b170abbf31c18a994346f62ed7
      
https://github.com/qemu/qemu/commit/37ad0e48e9fd58b170abbf31c18a994346f62ed7
  Author: Richard Henderson <richard.hender...@linaro.org>
  Date:   2025-10-07 (Tue, 07 Oct 2025)

  Changed paths:
    M .gitlab-ci.d/custom-runners.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch32.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-aarch64.yml
    R .gitlab-ci.d/custom-runners/ubuntu-22.04-s390x.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-aarch32.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-aarch64.yml
    A .gitlab-ci.d/custom-runners/ubuntu-24.04-s390x.yml
    M .gitmodules
    M .gitpublish
    M configure
    M meson_options.txt
    M pythondeps.toml
    M replay/replay.c
    M scripts/ci/setup/gitlab-runner.yml
    M scripts/ci/setup/ubuntu/build-environment.yml
    R scripts/ci/setup/ubuntu/ubuntu-2204-aarch64.yaml
    R scripts/ci/setup/ubuntu/ubuntu-2204-s390x.yaml
    A scripts/ci/setup/ubuntu/ubuntu-2404-aarch64.yaml
    A scripts/ci/setup/ubuntu/ubuntu-2404-s390x.yaml
    M scripts/ci/setup/vars.yml.template
    M scripts/meson-buildoptions.sh
    M tests/Makefile.include
    M tests/docker/dockerfiles/debian-i686-cross.docker
    M tests/functional/aarch64/test_reverse_debug.py
    M tests/functional/meson.build
    M tests/functional/ppc64/test_reverse_debug.py
    M tests/functional/qemu_test/__init__.py
    M tests/functional/qemu_test/decorators.py
    A tests/functional/qemu_test/gdb.py
    M tests/functional/reverse_debugging.py
    M tests/functional/x86_64/test_reverse_debug.py
    M tests/lcitool/refresh

  Log Message:
  -----------
  Merge tag 'pull-10.2-maintainer-071025-1' of https://gitlab.com/stsquad/qemu 
into staging

testing updates

 - tweak .gitpublish base to origin/master
 - restore .gitmodules to qemu-project hosts
 - drop 64 bits guests from i686
 - update aarch64/s390x custom runners to 24.04
 - tweak gitlab-runner registration method
 - make check-venv dependency for functional tests
 - replace avocado's gdb support with pygdbmi
 - remove avocado dependencies from reverse_debug tests
 - ensure replay.bin doesn't loose events after SHUTDOWN_HOST_QMP

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# gpg: Signature made Tue 07 Oct 2025 01:51:59 AM PDT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) 
<alex.ben...@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-10.2-maintainer-071025-1' of https://gitlab.com/stsquad/qemu:
  record/replay: fix race condition on test_aarch64_reverse_debug
  tests/functional: Adapt arches to reverse_debugging w/o Avocado
  tests/functional: Adapt reverse_debugging to run w/o Avocado
  tests/functional: Add decorator to skip test on missing env vars
  tests/functional: drop datadrainer class in reverse debugging
  tests/functional: replace avocado process with subprocess
  tests/functional: Add GDB class
  tests/functional: Provide GDB to the functional tests
  python: Install pygdbmi in meson's venv
  tests/functional: Re-activate the check-venv target
  scripts/ci: use recommended registration command
  gitlab: move custom runners to Ubuntu 24.04
  tests/lcitool: bump custom runner packages to Ubuntu 24.04
  tests/lcitool: drop 64 bit guests from i686 cross build
  .gitmodules: restore qemu-project mirror of u-boot-sam460ex
  .gitmodules: restore qemu-project mirror of u-boot
  .gitpublish: use origin/master as default base

Signed-off-by: Richard Henderson <richard.hender...@linaro.org>


Compare: https://github.com/qemu/qemu/compare/eb7abb4a719f...37ad0e48e9fd

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