Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 314a31ea0ba06160a54972ecf08ae56bc0c6b094
https://github.com/qemu/qemu/commit/314a31ea0ba06160a54972ecf08ae56bc0c6b094
Author: Thomas Huth <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M tests/functional/qemu_test/asset.py
Log Message:
-----------
tests/functional: Drop the "Attempting to cache ..." log text
The fetch() function already either prints "Using cached asset ..."
or "Downloading ... to ..." with the same file name to the log,
so the "Attempting to cache ..." message does not provide any
additional valuable information. Thus let's drop it to limit the
length of the logging output to a more reasonable size.
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: 8dd912b042f47bb0468f097df708cf2fab2af614
https://github.com/qemu/qemu/commit/8dd912b042f47bb0468f097df708cf2fab2af614
Author: Jaehoon Kim <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M hw/s390x/s390-pci-bus.c
Log Message:
-----------
s390x/pci: fix interrupt blocking by returning only the device's summary bit
Previously, set_ind_atomic() returned the entire byte containing
multiple summary bits. This meant that if any other summary bit in the
byte was set, interrupt injection could be incorrectly blocked, even
when the current device's summary bit was not set. As a result, the
guest could remain blocked after I/O completion during FIO tests.
This patch replaces set_ind_atomic() with set_ind_bit_atomic(), which
returns true if the bit was set by this function, and false if it was
already set or mapping failed. Interrupts are now blocked only when
the device's own summary bit was not previously set, avoiding
unintended blocking when multiple PCI summary bits exist within the
same byte.
Signed-off-by: Jaehoon Kim <[email protected]>
Reviewed-by: Halil Pasic <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Reviewed-by: Christian Borntraeger <[email protected]>
Reviewed-by: Matthew Rosato <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: d24ac20c6a86b32d64b90a90693c97086eba0f33
https://github.com/qemu/qemu/commit/d24ac20c6a86b32d64b90a90693c97086eba0f33
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/tcg/excp_helper.c
Log Message:
-----------
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (1/3)
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace the *_map() / *_unmap() methods in mchk_store_vregs().
No behavioral change expected.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: c35b166c1dc2d0332d2199ea8f36cf4eaa9eda35
https://github.com/qemu/qemu/commit/c35b166c1dc2d0332d2199ea8f36cf4eaa9eda35
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/helper.c
M target/s390x/s390x-internal.h
M target/s390x/tcg/excp_helper.c
M target/s390x/tcg/misc_helper.c
Log Message:
-----------
target/s390x: Propagate CPUS390XState to cpu_unmap_lowcore()
To be able to access the CPU state in cpu_unmap_lowcore()
in the next commit, propagate it as argument.
cpu_map_lowcore() already takes it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 64321858d0735191b6160ba78f2282a67df6d9d9
https://github.com/qemu/qemu/commit/64321858d0735191b6160ba78f2282a67df6d9d9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/helper.c
Log Message:
-----------
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (2/3)
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace the *_map() / *_unmap() methods in cpu_[un]map_lowcore().
No behavioral change expected.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 1819902285177c8781ab4ef92cc44e0882c0dec5
https://github.com/qemu/qemu/commit/1819902285177c8781ab4ef92cc44e0882c0dec5
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/helper.c
M target/s390x/s390x-internal.h
M target/s390x/sigp.c
Log Message:
-----------
target/s390x: Reduce s390_store_adtl_status() scope
s390_store_adtl_status() is only called within sigp.c,
move it and the SigpAdtlSaveArea structure definition
there where it belongs, with other SIGP handling code.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: db7721857b3033222a521acc2ace7d3ed9529cb6
https://github.com/qemu/qemu/commit/db7721857b3033222a521acc2ace7d3ed9529cb6
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/helper.c
M target/s390x/s390x-internal.h
M target/s390x/sigp.c
Log Message:
-----------
target/s390x: Reduce s390_store_status() scope
s390_store_status() is only called within sigp.c,
move it and the SigpSaveArea structure definition
there where it belongs, with other SIGP handling
code.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 00457aed51a240d6478e0870cd17fdcaa5f6a0ab
https://github.com/qemu/qemu/commit/00457aed51a240d6478e0870cd17fdcaa5f6a0ab
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/s390x/sigp.c
Log Message:
-----------
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (3/3)
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace the *_map() / *_unmap() methods in s390_store_status()
and s390_store_adtl_status(). In s390_store_status(), replace
cpu_physical_memory_write() by address_space_stb(), restricting
@ar_id scope. No behavioral change expected.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 47ea7263701e85ea03270d34c9a90f3971597e06
https://github.com/qemu/qemu/commit/47ea7263701e85ea03270d34c9a90f3971597e06
Author: Matthew Rosato <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M hw/s390x/s390-pci-bus.c
M include/hw/s390x/s390-pci-kvm.h
Log Message:
-----------
s390x/pci: set kvm_msi_via_irqfd_allowed
Allow irqfd to be used for virtio-pci on s390x if the kernel supports
it. This improves s390x virtio-pci performance when using kvm
acceleration by allowing kvm to deliver interrupts instead of QEMU.
Signed-off-by: Matthew Rosato <[email protected]>
Reviewed-by: Farhan Ali <[email protected]>
Reviewed-by: Eric Farman <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 5d7148ae8c0f881425badb9b624e2d44efcdc0be
https://github.com/qemu/qemu/commit/5d7148ae8c0f881425badb9b624e2d44efcdc0be
Author: Pierrick Bouvier <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_device_passthrough.py
M tests/functional/aarch64/test_rme_sbsaref.py
M tests/functional/aarch64/test_rme_virt.py
Log Message:
-----------
tests/functional: update tests using TF-A/TF-RMM to support FEAT_GCS
Signed-off-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: c817b325c16bee80a130e30c756021da95745b9e
https://github.com/qemu/qemu/commit/c817b325c16bee80a130e30c756021da95745b9e
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu-features.h
Log Message:
-----------
target/arm: Add isar feature test for FEAT_S1PIE, FEAT_S2PIE
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 48669f526deae089f23f75638819e7bb90c57d32
https://github.com/qemu/qemu/commit/48669f526deae089f23f75638819e7bb90c57d32
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Enable TCR2_ELx.PIE
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0277e0652b663770bb42113ed3fea1ea0dfeaf19
https://github.com/qemu/qemu/commit/0277e0652b663770bb42113ed3fea1ea0dfeaf19
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 26c7b95eb1342907c569cc6da7e27ded0959e4fe
https://github.com/qemu/qemu/commit/26c7b95eb1342907c569cc6da7e27ded0959e4fe
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/ptw.c
Log Message:
-----------
target/arm: Force HPD for stage2 translations
Stage2 translations do not have hierarchial permissions.
Setting HPD means we can eliminate an extra check against
regime_is_stage2.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 67f3eda009d9af5afb64886cbadc01454fd987a5
https://github.com/qemu/qemu/commit/67f3eda009d9af5afb64886cbadc01454fd987a5
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Cache NV1 early in get_phys_addr_lpae
We were not using the correct security space in the existing call
to nv_nv1_enabled, because it may have been modified for NSTable.
Cache it early, as we will shortly need it elsewhere as well.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1952f58f984a36bb30b9780ed0257e6879252fcd
https://github.com/qemu/qemu/commit/1952f58f984a36bb30b9780ed0257e6879252fcd
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Populate PIE in aa64_va_parameters
Select the PIE bit for the translation regime.
With PIE, the PTE layout changes, forcing HPD.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1cbaf63a109db8529589b0660df06ea69fd07b05
https://github.com/qemu/qemu/commit/1cbaf63a109db8529589b0660df06ea69fd07b05
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Implement get_S1prot_indirect
This approximately corresponds to AArch64.S1IndirectBasePermissions
and the tail of AArch64.S1ComputePermissions which applies WXN.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a811c5dafb728087fa6f222ad1322ec26d080fdd
https://github.com/qemu/qemu/commit/a811c5dafb728087fa6f222ad1322ec26d080fdd
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Implement get_S2prot_indirect
Move the stage2 permissions for normal accesses to
GetPhysAddrResult.s2prot. Put the stage2 permissions
for page table walking in CPUTLBEntryFull.prot.
This allows the permission checks in S1_ptw_translate
and arm_casq_ptw to see the right permission.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5a3197bc73040e657017d08445918c88c542f7d4
https://github.com/qemu/qemu/commit/5a3197bc73040e657017d08445918c88c542f7d4
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/machine.c
Log Message:
-----------
target/arm: Expand CPUARMState.exception.syndrome to 64 bits
This will be used for storing the ISS2 portion of the
ESR_ELx registers in aarch64 state. Re-order the fsr
member to eliminate two structure holes.
Drop the comment about "if we implement EL2" since we
have already done so.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9190d68e83dc13c08b50b538f6473894b1b7b024
https://github.com/qemu/qemu/commit/9190d68e83dc13c08b50b538f6473894b1b7b024
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/tcg-stubs.c
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Expand syndrome parameter to raise_exception*
Prepare for raising exceptions with 64-bit syndromes.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: cfd363ca4c374ba34673e34467d973255ca009e5
https://github.com/qemu/qemu/commit/cfd363ca4c374ba34673e34467d973255ca009e5
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/tlb_helper.c
Log Message:
-----------
target/arm: Implement dirtybit check for PIE
Both S1PIE and S2PIE have a bit to make software tracking
of dirty pages easier.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4983e3ccc9c384c7ae12822945943a0d8bce6537
https://github.com/qemu/qemu/commit/4983e3ccc9c384c7ae12822945943a0d8bce6537
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d182123974c4377757d50ce93108daef687a8951
https://github.com/qemu/qemu/commit/d182123974c4377757d50ce93108daef687a8951
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M include/exec/memopidx.h
Log Message:
-----------
include/exec/memopidx: Adjust for 32 mmu indexes
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e1e2f08b431890c757e8dffc760c2719e9577f86
https://github.com/qemu/qemu/commit/e1e2f08b431890c757e8dffc760c2719e9577f86
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M accel/tcg/cputlb.c
M include/hw/core/cpu.h
Log Message:
-----------
include/hw/core/cpu: Widen MMUIdxMap
Widen MMUIdxMap to 32 bits. Do not yet expand NB_MMU_MODES,
but widen the map type in preparation.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e886dccc8276f22296582338c30c639a24e45ea3
https://github.com/qemu/qemu/commit/e886dccc8276f22296582338c30c639a24e45ea3
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.h
A target/arm/mmuidx.h
Log Message:
-----------
target/arm: Split out mmuidx.h from cpu.h
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 65ef0f2b33621fcc24ca54936475a00604e9a62e
https://github.com/qemu/qemu/commit/65ef0f2b33621fcc24ca54936475a00604e9a62e
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/meson.build
A target/arm/mmuidx-internal.h
A target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert arm_mmu_idx_to_el from switch to table
In an effort to keep all ARMMMUIdx data in one place, begin construction
of an info table describing all of the properties of the mmu_idx. Begin
with the access EL.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5dccad96b1f089a2d97262565a26960cf04e1579
https://github.com/qemu/qemu/commit/5dccad96b1f089a2d97262565a26960cf04e1579
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
M target/arm/tcg/mte_helper.c
Log Message:
-----------
target/arm: Remove unused env argument from regime_el
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9fe4b77afef948acfee1681ae7c0c2860c48dd5d
https://github.com/qemu/qemu/commit/9fe4b77afef948acfee1681ae7c0c2860c48dd5d
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert regime_el from switch to table
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: bb39dd76d7f66eb4e5d513cdc2ed0179f5c1cc7f
https://github.com/qemu/qemu/commit/bb39dd76d7f66eb4e5d513cdc2ed0179f5c1cc7f
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert regime_has_2_ranges from switch to table
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 59af12841b749c15d2a26a8f4222bc7627d00d01
https://github.com/qemu/qemu/commit/59af12841b749c15d2a26a8f4222bc7627d00d01
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Remove unused env argument from regime_is_pan
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ceab42c677484b9d6c97c91e59f8263685e891f5
https://github.com/qemu/qemu/commit/ceab42c677484b9d6c97c91e59f8263685e891f5
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert regime_is_pan from switch to table
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: b1af3bb87a808270bd6a0a48833e71a6ba506829
https://github.com/qemu/qemu/commit/b1af3bb87a808270bd6a0a48833e71a6ba506829
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/ptw.c
Log Message:
-----------
target/arm: Remove unused env argument from regime_is_user
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 38e5e7018b9d3dbce30999b38d10cc5d7315da8c
https://github.com/qemu/qemu/commit/38e5e7018b9d3dbce30999b38d10cc5d7315da8c
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert regime_is_user from switch to table
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 346feee01c87713230e5f3da7b1126da1b43027f
https://github.com/qemu/qemu/commit/346feee01c87713230e5f3da7b1126da1b43027f
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert arm_mmu_idx_is_stage1_of_2 from switch to table
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 35ba9340114dc6122f5e7b65565a85795c2dc7d7
https://github.com/qemu/qemu/commit/35ba9340114dc6122f5e7b65565a85795c2dc7d7
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/internals.h
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Convert regime_is_stage2 to table
This wasn't using a switch, but two comparisons.
Convert it to arm_mmuidx_table for consistency.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f76cee647cb4b2057d45d315ae73e89fa6d6f336
https://github.com/qemu/qemu/commit/f76cee647cb4b2057d45d315ae73e89fa6d6f336
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M include/hw/core/cpu.h
M target/arm/helper.c
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
M target/arm/mmuidx.h
M target/arm/ptw.c
M target/arm/tcg/tlb-insns.c
Log Message:
-----------
target/arm: Introduce mmu indexes for GCS
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0fe292fadb4d1886ad57bb14abcfb4130901b0f6
https://github.com/qemu/qemu/commit/0fe292fadb4d1886ad57bb14abcfb4130901b0f6
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/mmuidx-internal.h
M target/arm/mmuidx.c
Log Message:
-----------
target/arm: Introduce regime_to_gcs
Add a lookup from any a64 mmu index to the gcs mmu index
within the same translation regime.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 4c14265b8092a250edaef62891ee2d55fcfac92d
https://github.com/qemu/qemu/commit/4c14265b8092a250edaef62891ee2d55fcfac92d
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/ptw.c
Log Message:
-----------
target/arm: Support page protections for GCS mmu indexes
Take read and write from the s1perms.gcs bit computed
by the Arm pseudocode.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8a0dda3e6b2394d0e96c16b80f44db97f9cc3e6e
https://github.com/qemu/qemu/commit/8a0dda3e6b2394d0e96c16b80f44db97f9cc3e6e
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/tlb_helper.c
Log Message:
-----------
target/arm: Implement gcs bit for data abort
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d8bf1761efa7aa0cbda765c153357079b1e0bd3f
https://github.com/qemu/qemu/commit/d8bf1761efa7aa0cbda765c153357079b1e0bd3f
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
A target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
M target/arm/meson.build
Log Message:
-----------
target/arm: Add GCS cpregs
Add isar_feature_aa64_gcs.
Enable SCR_GCSEN in scr_write.
Enable HCRX_GCSEN in hcrx_write.
Default HCRX_GCSEN on if EL2 disabled.
Add the GCSCR* and GCSPR* registers.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e5c79193ec92dca13e6eccc60c2a6a77bb8f2fb9
https://github.com/qemu/qemu/commit/e5c79193ec92dca13e6eccc60c2a6a77bb8f2fb9
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/tcg/hflags.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Add GCS enable and trap levels to DisasContext
Pipe GCSEnabled, GCSReturnValueCheckEnabled, and CheckGCSSTREnabled
through hflags to the translator.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 2b6c55fb032967629d07f2ba096f66d3b83a14bd
https://github.com/qemu/qemu/commit/2b6c55fb032967629d07f2ba096f66d3b83a14bd
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement FEAT_CHK
This feature contains only the CHKFEAT instruction. It has
no ID enable, being back-allocated into the hint nop space.
Reviewed-by: Gustavo Romero <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3476d935c3f17f937c7939d91f79cd3bdffc6209
https://github.com/qemu/qemu/commit/3476d935c3f17f937c7939d91f79cd3bdffc6209
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Make helper_exception_return system-only
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 38f8b024d80d276429dad0adadc67789aa89730a
https://github.com/qemu/qemu/commit/38f8b024d80d276429dad0adadc67789aa89730a
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
M target/arm/internals.h
M target/arm/tcg/helper-a64.c
Log Message:
-----------
target/arm: Export cpsr_{read_for, write_from}_spsr_elx
Move cpsr_write_from_spsr_elx from tcg/helper-a64.c to
helper.c, so that it's present with --disable-tcg.
Declare both in internals.h.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: de83d60a84f25b9518a91bcb996f60a911d03e48
https://github.com/qemu/qemu/commit/de83d60a84f25b9518a91bcb996f60a911d03e48
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/machine.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Expand pstate to 64 bits
The ARM now defines 36 bits in SPSR_ELx in aarch64 mode, so
it's time to bite the bullet and extend PSTATE to match.
Most changes are straightforward, adjusting printf formats,
changing local variable types. More complex is migration,
where to maintain backward compatibility a new pstate64
record is introduced, and only when one of the extensions
that sets bits 32-35 are active.
The fate of gdbstub is left undecided for the moment.
Reviewed-by: Peter Maydell <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f0fdbfae973de21344706c5fdd9588b24e2395b7
https://github.com/qemu/qemu/commit/f0fdbfae973de21344706c5fdd9588b24e2395b7
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/syndrome.h
Log Message:
-----------
target/arm: Add syndrome data for EC_GCS
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9e703a01f00a156f7944b8150bfb787ce273a4a0
https://github.com/qemu/qemu/commit/9e703a01f00a156f7944b8150bfb787ce273a4a0
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.h
M target/arm/helper.c
Log Message:
-----------
target/arm: Add arm_hcr_el2_nvx_eff
Implement the pseudocode function EffectiveHCR_EL2_NVx.
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3a6a957b89ffcdeed3a39ae9eb268dfbda926a63
https://github.com/qemu/qemu/commit/3a6a957b89ffcdeed3a39ae9eb268dfbda926a63
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Use arm_hcr_el2_nvx_eff in access_nv1
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 399d40b985032ec1364f9906ef6596264a53f2db
https://github.com/qemu/qemu/commit/399d40b985032ec1364f9906ef6596264a53f2db
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Split out access_nv1_with_nvx
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 766c99beabd5a15ec2f4d2b1372926d8e1b03717
https://github.com/qemu/qemu/commit/766c99beabd5a15ec2f4d2b1372926d8e1b03717
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs.h
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/tcg/op_helper.c
Log Message:
-----------
target/arm: Implement EXLOCKException for ELR_ELx and SPSR_ELx
If PSTATE.EXLOCK is set, and the GCS EXLOCK enable bit is set,
and nested virt is in the appropriate state, then we need to
raise an EXLOCK exception.
Since PSTATE.EXLOCK cannot be set without GCS being present
and enabled, no explicit check for GCS is required.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 49b49214f346da81a79961e7f89225200da274e6
https://github.com/qemu/qemu/commit/49b49214f346da81a79961e7f89225200da274e6
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Split {full,core}_a64_user_mem_index
Separate get_a64_user_mem_index into two separate functions, one which
returns the full ARMMMUIdx and one which returns the core mmu_idx.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 609f5d7692d97ea260eee9236d5741c46d07ff8d
https://github.com/qemu/qemu/commit/609f5d7692d97ea260eee9236d5741c46d07ff8d
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
Log Message:
-----------
target/arm: Introduce delay_exception{_el}
Add infrastructure to raise an exception out of line.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 923e7c432ec0fdee97b746f529f238dde2ba78f0
https://github.com/qemu/qemu/commit/923e7c432ec0fdee97b746f529f238dde2ba78f0
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Emit HSTR trap exception out of line
Use delay_exception_el to move the exception out of line.
Use TCG_COND_TSTNE instead of separate AND+NE.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0e15a9a53c56f8ddd6a8c6f691a0507429387d91
https://github.com/qemu/qemu/commit/0e15a9a53c56f8ddd6a8c6f691a0507429387d91
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate.c
Log Message:
-----------
target/arm: Emit v7m LTPSIZE exception out of line
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6a5596bad37e62800e9d8ed8d35cb6a1af1030ba
https://github.com/qemu/qemu/commit/6a5596bad37e62800e9d8ed8d35cb6a1af1030ba
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSSTR, GCSSTTR
Note that CreateAccDescGCS() does not enable tagchecked,
and Data Aborts from GCS instructions do not set iss.isv.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d383c43d6d510638adc69043a92572bec3840515
https://github.com/qemu/qemu/commit/d383c43d6d510638adc69043a92572bec3840515
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/a64.decode
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSB
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3afe6037e728f74be092027b4d24201a6ddc092f
https://github.com/qemu/qemu/commit/3afe6037e728f74be092027b4d24201a6ddc092f
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSPUSHM
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 0982f58db61277ff3babf1ac36c5eaceaadcb598
https://github.com/qemu/qemu/commit/0982f58db61277ff3babf1ac36c5eaceaadcb598
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSPOPM
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 6fb1678f90d028b0252699c66e99d6f6ff8127c8
https://github.com/qemu/qemu/commit/6fb1678f90d028b0252699c66e99d6f6ff8127c8
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSPUSHX
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 75c8d645b970ab083ce2ee06aa31c90028441983
https://github.com/qemu/qemu/commit/75c8d645b970ab083ce2ee06aa31c90028441983
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSPOPX
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a94b6aab8e522825b745dfedc4f4b641d7f22be0
https://github.com/qemu/qemu/commit/a94b6aab8e522825b745dfedc4f4b641d7f22be0
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSPOPCX
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 22d20e38044bdebd217ad0339d3765933ef16143
https://github.com/qemu/qemu/commit/22d20e38044bdebd217ad0339d3765933ef16143
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSSS1
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: e85fc2c62321201222d3e30191f376760978ccca
https://github.com/qemu/qemu/commit/e85fc2c62321201222d3e30191f376760978ccca
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Implement GCSSS2
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: a664ba1fc65ee84c9353cb2f0d2187f580b8e6bb
https://github.com/qemu/qemu/commit/a664ba1fc65ee84c9353cb2f0d2187f580b8e6bb
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Add gcs record for BL
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 978bad65f84aa4780ed586ef588ddb68a5d0532f
https://github.com/qemu/qemu/commit/978bad65f84aa4780ed586ef588ddb68a5d0532f
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Add gcs record for BLR
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d28bb06dc8ad5667c26d00765c442ca9cf7f1aa1
https://github.com/qemu/qemu/commit/d28bb06dc8ad5667c26d00765c442ca9cf7f1aa1
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Add gcs record for BLR with PAuth
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 488fab6fc9470515309ca405ece3c8ae4bf8c37c
https://github.com/qemu/qemu/commit/488fab6fc9470515309ca405ece3c8ae4bf8c37c
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Load gcs record for RET
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3d366bb67ff2eab40052bc09983328b06c394e12
https://github.com/qemu/qemu/commit/3d366bb67ff2eab40052bc09983328b06c394e12
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/translate-a64.c
Log Message:
-----------
target/arm: Load gcs record for RET with PAuth
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d77ed960164490d4daeaa3e1a3532ea53477538a
https://github.com/qemu/qemu/commit/d77ed960164490d4daeaa3e1a3532ea53477538a
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/helper.c
Log Message:
-----------
target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL
Per R_WTXBY, PSTATE.EXLOCK is 0 on an exception to a higher EL,
and copied from EXLOCKEn otherwise.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 70440a58589baa9d77428573f146a0ceaa5aa3ef
https://github.com/qemu/qemu/commit/70440a58589baa9d77428573f146a0ceaa5aa3ef
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/tcg/helper-a64.c
Log Message:
-----------
target/arm: Implement EXLOCK check during exception return
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 9c5dfe8b568b1b5265044f9f1dbc57345656e342
https://github.com/qemu/qemu/commit/9c5dfe8b568b1b5265044f9f1dbc57345656e342
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_GCS with -cpu max
Tested-by: Thiago Jung Bauermann <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d0e16dcad9b7a95367be91ddd2e74779c47ebf8a
https://github.com/qemu/qemu/commit/d0e16dcad9b7a95367be91ddd2e74779c47ebf8a
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
A linux-user/aarch64/gcs-internal.h
M linux-user/aarch64/target_prctl.h
M linux-user/qemu.h
M linux-user/syscall.c
Log Message:
-----------
linux-user/aarch64: Implement prctls for GCS
This is PR_GET_SHADOW_STACK_STATUS, PR_SET_SHADOW_STACK_STATUS,
and PR_LOCK_SHADOW_STACK_STATUS.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: f57359b3f0c85482c35f6668b0815c350ff5d451
https://github.com/qemu/qemu/commit/f57359b3f0c85482c35f6668b0815c350ff5d451
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/aarch64: Allocate new gcs stack on clone
Allocate the new stack early, so that error reporting need
not clean up other objects.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 1c9448037758277eb3dae71f98be3bbfdc91f467
https://github.com/qemu/qemu/commit/1c9448037758277eb3dae71f98be3bbfdc91f467
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/aarch64: Release gcs stack on thread exit
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ad1afe433fa18691306451cf0f79bd2568ef9709
https://github.com/qemu/qemu/commit/ad1afe433fa18691306451cf0f79bd2568ef9709
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/syscall.c
Log Message:
-----------
linux-user/aarch64: Implement map_shadow_stack syscall
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 5149287e10c903f2c629f127ec90415b2d1703d5
https://github.com/qemu/qemu/commit/5149287e10c903f2c629f127ec90415b2d1703d5
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu.c
Log Message:
-----------
target/arm: Enable GCSPR_EL0 for read in user-mode
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 37897b29b3a55fd60bb75ab12ff52d0b1bf72bef
https://github.com/qemu/qemu/commit/37897b29b3a55fd60bb75ab12ff52d0b1bf72bef
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/target_signal.h
Log Message:
-----------
linux-user/aarch64: Inject SIGSEGV for GCS faults
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: ef110c3070aff0994c3c5601a6e37c43ac793834
https://github.com/qemu/qemu/commit/ef110c3070aff0994c3c5601a6e37c43ac793834
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/aarch64/signal.c
Log Message:
-----------
linux-user/aarch64: Generate GCS signal records
Here we must push and pop a cap on the GCS stack as
well as the gcs record on the normal stack.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: d2687ad312f4ec776398d4badad287b421c8fbc0
https://github.com/qemu/qemu/commit/d2687ad312f4ec776398d4badad287b421c8fbc0
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M linux-user/aarch64/elfload.c
Log Message:
-----------
linux-user/aarch64: Enable GCS in HWCAP
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 3f3cc39b7d263faf453b6a165f56425e46a2f44e
https://github.com/qemu/qemu/commit/3f3cc39b7d263faf453b6a165f56425e46a2f44e
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gcs.h
A tests/tcg/aarch64/gcsstr.c
Log Message:
-----------
tests/tcg/aarch64: Add gcsstr
Add some infrastructure for testing gcs in userspace.
Validate successful and trapped executions of GCSSTR.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
[PMM: fixed hardcoded tabs]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8f278acdce11cce89e5599bde0de76692ae1b1d6
https://github.com/qemu/qemu/commit/8f278acdce11cce89e5599bde0de76692ae1b1d6
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gcspushm.c
Log Message:
-----------
tests/tcg/aarch64: Add gcspushm
Validate successful and trapped executions of GCSPUSHM, GCSPOPM.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: af0bd678df72f6c5a00484ed6acccfcfc91577d4
https://github.com/qemu/qemu/commit/af0bd678df72f6c5a00484ed6acccfcfc91577d4
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M tests/tcg/aarch64/Makefile.target
M tests/tcg/aarch64/gcs.h
A tests/tcg/aarch64/gcsss.c
Log Message:
-----------
tests/tcg/aarch64: Add gcsss
Validate stack switching and recursion depth.
Reviewed-by: Pierrick Bouvier <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-id: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Commit: 8f6dd8f78aa961dbc9a02b01b6abe316f37d2766
https://github.com/qemu/qemu/commit/8f6dd8f78aa961dbc9a02b01b6abe316f37d2766
Author: Gustavo Romero <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpregs.h
Log Message:
-----------
target/arm: Add a cpreg flag to indicate no trap in NV
Add a new flag, ARM_CP_NV_NO_TRAP, to indicate that a CP register, even
though it has opc1 == 4 or 5, does not trap when nested virtualization
is enabled (FEAT_NV/FEAT_NV2).
Signed-off-by: Gustavo Romero <[email protected]>
Message-id: [email protected]
[PMM: tweaked comment text]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 700f08d5829f3736fdfafe92d8223254ffc9c495
https://github.com/qemu/qemu/commit/700f08d5829f3736fdfafe92d8223254ffc9c495
Author: Gustavo Romero <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/helper.c
M target/arm/internals.h
Log Message:
-----------
target/arm: Implement FEAT_MEC registers
Add all FEAT_MEC registers. Enable access to the registers via the
SCTLR2 and TCR2 control bits. Add the two new cache management
instructions, which are nops in QEMU because we do not model caches.
Message-ID: <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Gustavo Romero <[email protected]>
Message-id: [email protected]
[rth: Squash 3 patches to add all registers at once.]
Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Gustavo Romero <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: 00936783abf77ebb47a78312a2e6500c6a13d938
https://github.com/qemu/qemu/commit/00936783abf77ebb47a78312a2e6500c6a13d938
Author: Gustavo Romero <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M docs/system/arm/emulation.rst
M target/arm/tcg/cpu64.c
Log Message:
-----------
target/arm: Enable FEAT_MEC in -cpu max
Advertise FEAT_MEC in AA64MMFR3 ID register for the Arm64 cpu max as a
first step to fully support FEAT_MEC.
The FEAT_MEC is an extension to FEAT_RME that implements multiple
Memory Encryption Contexts (MEC) so the memory in a realm can be
encrypted and accessing it from the wrong encryption context is not
possible. An encryption context allow the selection of a memory
encryption engine.
At this point, no real memory encryption is supported, but software
stacks that rely on FEAT_MEC should work properly.
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Gustavo Romero <[email protected]>
Message-id: [email protected]
Message-ID: <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Signed-off-by: Gustavo Romero <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>
Commit: ed26056d90ddff21351f3efd2cb47fea4f0e1d45
https://github.com/qemu/qemu/commit/ed26056d90ddff21351f3efd2cb47fea4f0e1d45
Author: Richard W.M. Jones <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M block/curl.c
M contrib/elf2dmp/download.c
Log Message:
-----------
block/curl.c: Use explicit long constants in curl_easy_setopt calls
curl_easy_setopt takes a variable argument that depends on what
CURLOPT you are setting. Some require a long constant. Passing a
plain int constant is potentially wrong on some platforms.
With warnings enabled, multiple warnings like this were printed:
../block/curl.c: In function ‘curl_init_state’:
../block/curl.c:474:13: warning: call to ‘_curl_easy_setopt_err_long’ declared
with attribute warning: curl_easy_setopt expects a long argument
[-Wattribute-warning]
474 | curl_easy_setopt(state->curl, CURLOPT_AUTOREFERER, 1) ||
| ^
Signed-off-by: Richard W.M. Jones <[email protected]>
Signed-off-by: Chenxi Mao <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Akihiko Odaki <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Richard Henderson <[email protected]>
Message-ID: <[email protected]>
Commit: 4ea22762d0c043bc66f3877e5d01692880848bf7
https://github.com/qemu/qemu/commit/4ea22762d0c043bc66f3877e5d01692880848bf7
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M hw/s390x/s390-pci-bus.c
M include/hw/s390x/s390-pci-kvm.h
M target/s390x/helper.c
M target/s390x/s390x-internal.h
M target/s390x/sigp.c
M target/s390x/tcg/excp_helper.c
M target/s390x/tcg/misc_helper.c
M tests/functional/qemu_test/asset.py
Log Message:
-----------
Merge tag 'pull-request-2025-10-10' of https://gitlab.com/thuth/qemu into
staging
* Improves s390x virtio-pci performance when using kvm
* Fix a problem with losing interrupts on s390x in certain cases
* Replace legacy cpu_physical_memory_[un]map() calls in s390x code
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# gpg: Signature made Fri 10 Oct 2025 01:19:54 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "[email protected]"
# gpg: Good signature from "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-10-10' of https://gitlab.com/thuth/qemu:
s390x/pci: set kvm_msi_via_irqfd_allowed
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (3/3)
target/s390x: Reduce s390_store_status() scope
target/s390x: Reduce s390_store_adtl_status() scope
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (2/3)
target/s390x: Propagate CPUS390XState to cpu_unmap_lowcore()
target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (1/3)
s390x/pci: fix interrupt blocking by returning only the device's summary bit
tests/functional: Drop the "Attempting to cache ..." log text
Signed-off-by: Richard Henderson <[email protected]>
Commit: f3f2ad119347e8c086b72282febcaac5d731b343
https://github.com/qemu/qemu/commit/f3f2ad119347e8c086b72282febcaac5d731b343
Author: Richard Henderson <[email protected]>
Date: 2025-10-10 (Fri, 10 Oct 2025)
Changed paths:
M accel/tcg/cputlb.c
M docs/system/arm/emulation.rst
M include/exec/memopidx.h
M include/hw/core/cpu.h
M linux-user/aarch64/cpu_loop.c
M linux-user/aarch64/elfload.c
A linux-user/aarch64/gcs-internal.h
M linux-user/aarch64/signal.c
M linux-user/aarch64/target_prctl.h
M linux-user/aarch64/target_signal.h
M linux-user/qemu.h
M linux-user/syscall.c
A target/arm/cpregs-gcs.c
M target/arm/cpregs.h
M target/arm/cpu-features.h
M target/arm/cpu.c
M target/arm/cpu.h
M target/arm/gdbstub64.c
M target/arm/helper.c
M target/arm/internals.h
M target/arm/machine.c
M target/arm/meson.build
A target/arm/mmuidx-internal.h
A target/arm/mmuidx.c
A target/arm/mmuidx.h
M target/arm/ptw.c
M target/arm/syndrome.h
M target/arm/tcg-stubs.c
M target/arm/tcg/a64.decode
M target/arm/tcg/cpu64.c
M target/arm/tcg/helper-a64.c
M target/arm/tcg/helper-a64.h
M target/arm/tcg/hflags.c
M target/arm/tcg/mte_helper.c
M target/arm/tcg/op_helper.c
M target/arm/tcg/tlb-insns.c
M target/arm/tcg/tlb_helper.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/arm/tcg/translate.h
M tests/functional/aarch64/test_device_passthrough.py
M tests/functional/aarch64/test_rme_sbsaref.py
M tests/functional/aarch64/test_rme_virt.py
M tests/tcg/aarch64/Makefile.target
A tests/tcg/aarch64/gcs.h
A tests/tcg/aarch64/gcspushm.c
A tests/tcg/aarch64/gcsss.c
A tests/tcg/aarch64/gcsstr.c
Log Message:
-----------
Merge tag 'pull-target-arm-20251010' of https://gitlab.com/pm215/qemu into
staging
target-arm queue:
* Implement FEAT_GCS
* Implement FEAT_MEC
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# qNn7eFEG80roh+lykTe7BroQSQ+pIAxOXM/ouwr+59fsXtnCKrdFG+96WdS+yhsC
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# s2MWF0xy8CnhPBJwyK4iOg==
# =yKgg
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 10 Oct 2025 06:04:32 AM PDT
# gpg: using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg: issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# gpg: aka "Peter Maydell <[email protected]>"
[unknown]
# gpg: aka "Peter Maydell <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83 15CF 3C25 25ED 1436 0CDE
* tag 'pull-target-arm-20251010' of https://gitlab.com/pm215/qemu: (76 commits)
target/arm: Enable FEAT_MEC in -cpu max
target/arm: Implement FEAT_MEC registers
target/arm: Add a cpreg flag to indicate no trap in NV
tests/tcg/aarch64: Add gcsss
tests/tcg/aarch64: Add gcspushm
tests/tcg/aarch64: Add gcsstr
linux-user/aarch64: Enable GCS in HWCAP
linux-user/aarch64: Generate GCS signal records
linux-user/aarch64: Inject SIGSEGV for GCS faults
target/arm: Enable GCSPR_EL0 for read in user-mode
linux-user/aarch64: Implement map_shadow_stack syscall
linux-user/aarch64: Release gcs stack on thread exit
linux-user/aarch64: Allocate new gcs stack on clone
linux-user/aarch64: Implement prctls for GCS
target/arm: Enable FEAT_GCS with -cpu max
target/arm: Implement EXLOCK check during exception return
target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL
target/arm: Load gcs record for RET with PAuth
target/arm: Load gcs record for RET
target/arm: Add gcs record for BLR with PAuth
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/94474a7733a5...f3f2ad119347
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