Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 2e9ff01a912997c4af066aab5e43a52db6c68aaf
https://github.com/qemu/qemu/commit/2e9ff01a912997c4af066aab5e43a52db6c68aaf
Author: Bibo Mao <[email protected]>
Date: 2025-10-15 (Wed, 15 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Add missing TLB flush with different asid
If asid is changed in function helper_csrwr_asid(), qemu TLB is flushed,
however loongArch TLB is still valid. So loongArch TLB need be invalidated
in function invalidate_tlb() with different asid and bit effective need
be cleared.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: f72848e31fbe30377ce8ed3b1ce9be7346933d34
https://github.com/qemu/qemu/commit/f72848e31fbe30377ce8ed3b1ce9be7346933d34
Author: Bibo Mao <[email protected]>
Date: 2025-10-15 (Wed, 15 Oct 2025)
Changed paths:
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Skip global TLB when calculating replaced TLB
When new TLB entry is added, TLB index is calculated from invalid
entry at first and then from different ASID, and randomly at last.
With different ASID, global TLB should be skipped since ASID is not
useful when global TLB is added.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 52d90741637e498042269f17925b500f4ffe3ef8
https://github.com/qemu/qemu/commit/52d90741637e498042269f17925b500f4ffe3ef8
Author: Bibo Mao <[email protected]>
Date: 2025-10-15 (Wed, 15 Oct 2025)
Changed paths:
M MAINTAINERS
M hw/intc/loongarch_pic_kvm.c
M hw/loongarch/virt-acpi-build.c
M hw/loongarch/virt-fdt-build.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_pic_common.h
M include/hw/loongarch/virt.h
M include/hw/pci-host/ls7a.h
Log Message:
-----------
hw/loongarch/virt: Remove header file ls7a.h
LoongArch virt machine uses GPEX PCIE host bridge rather than 7A host
bridge. Remove header file ls7a.h and put hardware information to file
include/hw/loongarch/virt.h
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: a9c5e0ed9b63becde7a6188bf71f95e31a132b19
https://github.com/qemu/qemu/commit/a9c5e0ed9b63becde7a6188bf71f95e31a132b19
Author: Bibo Mao <[email protected]>
Date: 2025-10-15 (Wed, 15 Oct 2025)
Changed paths:
M hw/loongarch/virt.c
M include/hw/loongarch/virt.h
Log Message:
-----------
hw/loongarch/virt: Sort order by hardware device base address
With header file include/hw/loongarch/virt.h, hardware device definition
order is sorted by its base address. Add remove unused macro
VIRT_IOAPIC_REG_BASE and VIRT_MISC_REG_BASE.
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Commit: 8109ebdb95c45d9062c7e6e7beae0ee571fca4f8
https://github.com/qemu/qemu/commit/8109ebdb95c45d9062c7e6e7beae0ee571fca4f8
Author: Richard Henderson <[email protected]>
Date: 2025-10-15 (Wed, 15 Oct 2025)
Changed paths:
M MAINTAINERS
M hw/intc/loongarch_pic_kvm.c
M hw/loongarch/virt-acpi-build.c
M hw/loongarch/virt-fdt-build.c
M hw/loongarch/virt.c
M include/hw/intc/loongarch_pic_common.h
M include/hw/loongarch/virt.h
M include/hw/pci-host/ls7a.h
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
Merge tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu into
staging
loongarch queue
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# gpg: Signature made Tue 14 Oct 2025 08:08:53 PM PDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20251015' of https://github.com/bibo-mao/qemu:
hw/loongarch/virt: Sort order by hardware device base address
hw/loongarch/virt: Remove header file ls7a.h
target/loongarch: Skip global TLB when calculating replaced TLB
target/loongarch: Add missing TLB flush with different asid
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/3bf5c57a1182...8109ebdb95c4
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