Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 482869ca84a33c4d407f580400033fa5f146c1a7
https://github.com/qemu/qemu/commit/482869ca84a33c4d407f580400033fa5f146c1a7
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/alpha/translate.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/avr/translate.c
M target/hexagon/translate.c
M target/loongarch/tcg/translate.c
M target/microblaze/translate.c
M target/mips/tcg/translate.c
M target/ppc/translate.c
M target/riscv/translate.c
M target/rx/translate.c
M target/sh4/translate.c
M target/sparc/translate.c
M target/tricore/translate.c
Log Message:
-----------
accel/tcg: Name gen_goto_tb()'s TB slot index as @tb_slot_idx
tcg_gen_goto_tb() takes an unsigned index to the TB slot (0 or 1).
Declare the argument as unsigned and rename it as @tb_slot_idx
(which is more descriptive than @n) on all targets.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-Id: <[email protected]>
Commit: a6a5f0b4644ed41878936d264bc23dd72532771f
https://github.com/qemu/qemu/commit/a6a5f0b4644ed41878936d264bc23dd72532771f
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/alpha/helper.h
M target/alpha/sys_helper.c
M target/alpha/translate.c
Log Message:
-----------
target/alpha: Access CPUState::cpu_index via helper
CPUState::cpu_index is a target agnostic field, meant
for common code (i.e. accel/ and system/ folders).
Target specific code should use the CPUClass::get_arch_id()
helper, even if there is a 1:1 mapping.
In preparation of generic changes around CPU indexing,
introduce the whoami helper to access the generic
CPUState::cpu_index field.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 5940712ed0f770cae4d5e5999dc46b6675db8120
https://github.com/qemu/qemu/commit/5940712ed0f770cae4d5e5999dc46b6675db8120
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/alpha/machine.c
Log Message:
-----------
target/alpha: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
All these CPUAlphaState fields are of uint64_t type (except
the @fir[] array which uses float64, expanded to the same
type definition). Use the appropriate VMSTATE_UINT64() macro.
There is no functional change (the migration stream is not
modified), because the Alpha targets are only built as 64-bit:
$ git grep TARGET_LONG_BITS configs/targets/alpha*
configs/targets/alpha-linux-user.mak:4:TARGET_LONG_BITS=64
configs/targets/alpha-softmmu.mak:2:TARGET_LONG_BITS=64
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 152820a991e6b0b4cbbdb594f87e43252626c0da
https://github.com/qemu/qemu/commit/152820a991e6b0b4cbbdb594f87e43252626c0da
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/i386/monitor.c
Log Message:
-----------
target/i386/monitor: Propagate CPU address space to 'info mem' handlers
We want to replace the cpu_physical_memory_read() calls by
address_space_read() equivalents. Since the latter requires
an address space, and these commands are run in the context
of a vCPU, propagate its first address space. Next commit
will do the replacements.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-Id: <[email protected]>
Commit: 17db4d61d148aa87b84907e3aa6bee95d29955a3
https://github.com/qemu/qemu/commit/17db4d61d148aa87b84907e3aa6bee95d29955a3
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/i386/monitor.c
Log Message:
-----------
target/i386/monitor: Replace legacy cpu_physical_memory_read() calls
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace:
- cpu_physical_memory_read(len=4) -> address_space_ldl()
- cpu_physical_memory_read(len=8) -> address_space_ldq()
inlining the little endianness conversion via the '_le' suffix.
As with the previous implementation, ignore whether the memory
read succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-Id: <[email protected]>
Commit: e9f173cd51b8b0a877553ab77bed879f09afd61e
https://github.com/qemu/qemu/commit/e9f173cd51b8b0a877553ab77bed879f09afd61e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/cpu.h
M target/hppa/trace-events
Log Message:
-----------
target/hppa: Use hwaddr type for HPPATLBEntry::pa
HPPATLBEntry::@pa is a physical address, use the appropriate type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4fe2763a904a16197b5de5375e6779b81d363d03
https://github.com/qemu/qemu/commit/4fe2763a904a16197b5de5375e6779b81d363d03
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/cpu.h
M target/hppa/helper.c
M target/hppa/mem_helper.c
Log Message:
-----------
target/hppa: Have hppa_form_gva*() return vaddr type
Return a 'vaddr' type for "guest virtual address".
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 714dd08fed17b4c091bd59d46b61e923552a7358
https://github.com/qemu/qemu/commit/714dd08fed17b4c091bd59d46b61e923552a7358
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Explode MO_TExx -> MO_TE | MO_xx
Extract the implicit MO_TE definition in order to replace
it in a commits.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/openrisc); \
done
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4eef4dab502f555c4609bcd3606ea076544d5c90
https://github.com/qemu/qemu/commit/4eef4dab502f555c4609bcd3606ea076544d5c90
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Conceal MO_TE within do_load()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: e3da43671179afb09e55b4ba3d0352b4276dc4cb
https://github.com/qemu/qemu/commit/e3da43671179afb09e55b4ba3d0352b4276dc4cb
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Conceal MO_TE within do_load_32/64()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0807994a0cca7ee512975523ecaef4926a5632f9
https://github.com/qemu/qemu/commit/0807994a0cca7ee512975523ecaef4926a5632f9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Conceal MO_TE within do_store()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 64d1c178513c77172d4917fa03e3a9c332050c73
https://github.com/qemu/qemu/commit/64d1c178513c77172d4917fa03e3a9c332050c73
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Conceal MO_TE within do_store_32/64()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6c1c734f786f8279c3b0c4bf57063bc79cc5c828
https://github.com/qemu/qemu/commit/6c1c734f786f8279c3b0c4bf57063bc79cc5c828
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Introduce mo_endian() helper
mo_endian() returns the target endianness.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 7307ff955818d9e4eec2b155e501e360acf6eaf9
https://github.com/qemu/qemu/commit/7307ff955818d9e4eec2b155e501e360acf6eaf9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/translate.c
Log Message:
-----------
target/hppa: Replace MO_TE -> MO_BE
We only build the PA-RISC targets using big endianness order:
$ git grep TARGET_BIG_ENDIAN configs/targets/hppa-*
configs/targets/hppa-linux-user.mak:5:TARGET_BIG_ENDIAN=y
configs/targets/hppa-softmmu.mak:2:TARGET_BIG_ENDIAN=y
Therefore the MO_TE definition always expands to MO_BE. Use the
latter to simplify.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: cea82f8cdd07697a48ae1c4e026707463f432a45
https://github.com/qemu/qemu/commit/cea82f8cdd07697a48ae1c4e026707463f432a45
Author: Gabriel Brookman <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/hppa/insns.decode
Log Message:
-----------
target/hppa: correct size bit parity for fmpyadd
For the fmpyadd instruction on the hppa architecture, there is a bit
used to specify whether the instruction is operating on a 32 bit or
64 bit floating point register. For most instructions, such a bit is 0
when operating on the smaller register and 1 when operating on the
larger register. However, according to page 6-57 of the PA-RISC 1.1
Architecture and Instruction Set Reference Manual, this convention is
reversed for the fmpyadd instruction specifically, meaning the bit is
1 for operations on 32 bit registers and 0 for 64 bit registers. See
also page 6-18 (fig. 6-8) and 6-19 (table 6-16), where the f field
for FMPYADD and FMPYSUB is documented. Previously, QEMU decoded this
operation as operating on the other size of register, leading to bugs
when translating the fmpyadd instruction. This patch fixes that issue.
Reported-by: Andreas Hüttel <[email protected]>
Signed-off-by: Gabriel Brookman <[email protected]>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3096
Reviewed-by: Richard Henderson <[email protected]>
Acked-by: Helge Deller <[email protected]>
Message-ID:
<20251009-hppa-correct-fmpyadd-size-bit-decoding-v1-1-f63bb6c32...@gmail.com>
[PMD: Add documentation refs mentioned by Andreas K. Huettel]
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 108773e700075a6dab8e4ae8d1330f6dfccba1d4
https://github.com/qemu/qemu/commit/108773e700075a6dab8e4ae8d1330f6dfccba1d4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/loongarch/machine.c
Log Message:
-----------
target/loongarch: Replace VMSTATE_UINTTL() -> VMSTATE_UINT64()
All LoongArchCPU::pc and LoongArchCPU::gpr[] fields are of
uint64_t type. Use the appropriate VMSTATE_UINT64() macro.
There is no functional change (the migration stream is not
modified), because the LoongArch targets are only built as 64-bit:
$ git grep TARGET_LONG_BITS configs/targets/loongarch64*
configs/targets/loongarch64-linux-user.mak:7:TARGET_LONG_BITS=64
configs/targets/loongarch64-softmmu.mak:7:TARGET_LONG_BITS=64
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Commit: 656940971f253412a565da9f21cf6f05a284c3d1
https://github.com/qemu/qemu/commit/656940971f253412a565da9f21cf6f05a284c3d1
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/loongarch/tcg/translate.c
Log Message:
-----------
target/loongarch: Remove target_ulong use in gen_goto_tb()
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Commit: 7f306758fb83f1b64d02647171d5f65fc157ac25
https://github.com/qemu/qemu/commit/7f306758fb83f1b64d02647171d5f65fc157ac25
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/loongarch/gdbstub.c
Log Message:
-----------
target/loongarch: Remove target_ulong use in gdb_write_register handler
ldq_le_p() returns a uint64_t type, big enough to also hold
ldl_le_p() return value. If we were building for a 32-bit
LoongArch target, ldq_le_p() would not fit in target_ulong.
Better stick to plain uint64_t.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Commit: f756b7745a16a20815449099004076e3587e0448
https://github.com/qemu/qemu/commit/f756b7745a16a20815449099004076e3587e0448
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
M target/loongarch/tcg/tlb_helper.c
Log Message:
-----------
target/loongarch: Do not use target_ulong type for LDDIR level
The LDDIR level page table is a 5-bit immediate. Using the
uint32_t type for it is sufficient. Avoid the target_ulong type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Reviewed-by: Song Gao <[email protected]>
Message-Id: <[email protected]>
Commit: eefee97c4ca386ff82691417846fd252d90d978e
https://github.com/qemu/qemu/commit/eefee97c4ca386ff82691417846fd252d90d978e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Remove unused @cpu_exception_index TCGv
When moving the @exception_index from each target ArchCPU
to the global CPUState in commit 27103424c40 ("cpu: Move
exception_index field from CPU_COMMON to CPUState"), the
@cpu_exception_index TCGv has been created for m68k target.
For years, no code ever used this register. Simply remove it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: cb4ca3b358660646db62c256f360598e92c65b97
https://github.com/qemu/qemu/commit/cb4ca3b358660646db62c256f360598e92c65b97
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/m68k/translate.c
Log Message:
-----------
target/m68k: Remove pointless @cpu_halted TCGv
Avoid registering a TCGv to write the generic CPUState::halted
field. Access it directly via @env in both STOP / HALT opcodes.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 1f097e46a38ed3b699dcac56c8adf6113c9278b8
https://github.com/qemu/qemu/commit/1f097e46a38ed3b699dcac56c8adf6113c9278b8
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/mmu.c
M target/microblaze/mmu.h
Log Message:
-----------
target/microblaze: Remove target_ulong use in cpu_handle_mmu_fault()
cpu_handle_mmu_fault() -- renamed in commit f429d607c71 -- expects
a vaddr type for its address argument since commit 7510454e3e7
("cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0651ea17e89903789d11dc601dc5ecd7c8e810c7
https://github.com/qemu/qemu/commit/0651ea17e89903789d11dc601dc5ecd7c8e810c7
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/helper.c
Log Message:
-----------
target/microblaze: Remove target_ulong uses in get_phys_page_attrs_debug
The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
and return a 'hwaddr' type since commit 00b941e581b ("cpu: Turn
cpu_get_phys_page_debug() into a CPUClass hook").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: dc693a4a88a4c02b490378a7dc05c8e83f59cf97
https://github.com/qemu/qemu/commit/dc693a4a88a4c02b490378a7dc05c8e83f59cf97
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Remove target_ulong use in gen_goto_tb()
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 92035b7b0dd9fd40527a58479c9865a6dce104b9
https://github.com/qemu/qemu/commit/92035b7b0dd9fd40527a58479c9865a6dce104b9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/helper.h
M target/microblaze/op_helper.c
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Remove target_ulong use in helper_stackprot()
Since commit 36a9529e60e ("target/microblaze: Simplify
compute_ldst_addr_type{a,b}"), helper_stackprot() takes
a TCGv_i32 argument.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 1bf79694bc09995e805bb017515ef3cd5720fd04
https://github.com/qemu/qemu/commit/1bf79694bc09995e805bb017515ef3cd5720fd04
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Have compute_ldst_addr_type[ab] return TCGv_i32
Both compute_ldst_addr_typea() and compute_ldst_addr_typeb()
bodies use a TCGv_i32, so return the same type.
Suggested-by: Anton Johansson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2c12ba4d8bdd309359d1072594f5a317e09da78b
https://github.com/qemu/qemu/commit/2c12ba4d8bdd309359d1072594f5a317e09da78b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Have do_load/store() take a TCGv_i32 address argument
All callers of do_load() and do_store() pass a TCGv_i32 address
type, have both functions take a TCGv_i32.
Suggested-by: Anton Johansson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 5dfe024f9e2d97bb5b2e8f7bd520e8a55e39a725
https://github.com/qemu/qemu/commit/5dfe024f9e2d97bb5b2e8f7bd520e8a55e39a725
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/microblaze/cpu.h
M target/microblaze/machine.c
M target/microblaze/translate.c
Log Message:
-----------
target/microblaze: Convert CPUMBState::res_addr field to uint32_t type
CPUMBState::@res_addr field is used as u32 since commit
cfeea807e5a ("target-microblaze: Tighten up TCGv_i32 vs
TCGv type usage"). Convert it as such, bumping the migration
version. Use the RES_ADDR_NONE definition when appropriate.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2795bc52af4949aa7c7d900f897e5fc81c6c9b24
https://github.com/qemu/qemu/commit/2795bc52af4949aa7c7d900f897e5fc81c6c9b24
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/machine.c
Log Message:
-----------
target/openrisc: Replace VMSTATE_UINTTL() -> VMSTATE_UINT32()
Both OpenRISCTLBEntry fields are of uint32_t type. Use the
appropriate VMSTATE_UINT32() macro.
There is no functional change (the migration stream is not
modified), because the OpenRISC targets are only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/or1k-*
configs/targets/or1k-linux-user.mak:5:TARGET_LONG_BITS=32
configs/targets/or1k-softmmu.mak:5:TARGET_LONG_BITS=32
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: a3c4facd395b9d39996ed60d42b1f448d3f727cc
https://github.com/qemu/qemu/commit/a3c4facd395b9d39996ed60d42b1f448d3f727cc
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/sys_helper.c
Log Message:
-----------
target/openrisc: Do not use target_ulong for @mr in MTSPR helper
OpenRISCTLBEntry::@mr field is a uint32_t type since its
introduction in commit 726fe045720 ("target-or32: Add MMU support").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 1843e89bec5f8551a9a554aca9f51d76e6ae9493
https://github.com/qemu/qemu/commit/1843e89bec5f8551a9a554aca9f51d76e6ae9493
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/cpu.h
Log Message:
-----------
target/openrisc: Remove unused cpu_openrisc_map_address_*() handlers
Commit 23d45ebdb19 ("target/openrisc: Remove indirect
function calls for mmu") removed the last uses of both
cpu_openrisc_map_address_code() and
cpu_openrisc_map_address_data() helpers.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2367c94cbb1876b789ff91f78fd7daf2c1d6fb93
https://github.com/qemu/qemu/commit/2367c94cbb1876b789ff91f78fd7daf2c1d6fb93
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/mmu.c
Log Message:
-----------
target/openrisc: Remove target_ulong use in raise_mmu_exception()
TCGCPUOps::tlb_fill() handler provides a vaddr type (since commit
7510454e3e7 "cpu: Turn cpu_handle_mmu_fault() into a CPUClass hook").
Do not inline get_phys_nommu(), rely on the linker to optimize at
linking time.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 9dc4862dc4ae95f4f5b94052b95699a83e1d197c
https://github.com/qemu/qemu/commit/9dc4862dc4ae95f4f5b94052b95699a83e1d197c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Use vaddr type for $pc jumps
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 81e2fb236b702c7e172b64be4fd11aacebe50e4c
https://github.com/qemu/qemu/commit/81e2fb236b702c7e172b64be4fd11aacebe50e4c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Remove 'TARGET_LONG_BITS != 32' dead code
The OpenRISC targets are only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/or1k-*
configs/targets/or1k-linux-user.mak:5:TARGET_LONG_BITS=32
configs/targets/or1k-softmmu.mak:5:TARGET_LONG_BITS=32
Remove the dead code guarded within TARGET_LONG_BITS != 32.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: ef797ac00257ed31f534058fc43b8ae7c0019ea0
https://github.com/qemu/qemu/commit/ef797ac00257ed31f534058fc43b8ae7c0019ea0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Explode MO_TExx -> MO_TE | MO_xx
Extract the implicit MO_TE definition in order to replace
it in the next commit.
Mechanical change using:
$ for n in UW UL UQ UO SW SL SQ; do \
sed -i -e "s/MO_TE$n/MO_TE | MO_$n/" \
$(git grep -l MO_TE$n target/openrisc); \
done
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 22c36c0a20ce7bccbfe61ff7ee676c7a0e6b7c51
https://github.com/qemu/qemu/commit/22c36c0a20ce7bccbfe61ff7ee676c7a0e6b7c51
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Conceal MO_TE within do_load()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2f737e19a4dbb72596c29656cec07f26198161d5
https://github.com/qemu/qemu/commit/2f737e19a4dbb72596c29656cec07f26198161d5
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Conceal MO_TE within do_store()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 73cd283e58d4a8f03ed8786e148ceedf676bee40
https://github.com/qemu/qemu/commit/73cd283e58d4a8f03ed8786e148ceedf676bee40
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Introduce mo_endian() helper
mo_endian() returns the target endianness.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4f6c60683f2033dd9177ca0bf1299ffea1c07dd9
https://github.com/qemu/qemu/commit/4f6c60683f2033dd9177ca0bf1299ffea1c07dd9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Replace MO_TE -> MO_BE
We only build the OpenRISC targets using big endianness order:
$ git grep TARGET_BIG_ENDIAN configs/targets/or1k-*
configs/targets/or1k-linux-user.mak:2:TARGET_BIG_ENDIAN=y
configs/targets/or1k-softmmu.mak:2:TARGET_BIG_ENDIAN=y
Therefore the MO_TE definition always expands to MO_BE. Use the
latter to simplify.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 500708331e3f0c856270c14d836c79fcc65bdfde
https://github.com/qemu/qemu/commit/500708331e3f0c856270c14d836c79fcc65bdfde
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Inline tcg_gen_trunc_i64_tl()
The OpenRISC targets are only built as 32-bit, so tcg_gen_trunc_i64_tl
expands to tcg_gen_extrl_i64_i32(). Use the latter to simplify the
next commit mechanical change.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 5b67dbf1dc3caa6992576725a0783fa68fe6990c
https://github.com/qemu/qemu/commit/5b67dbf1dc3caa6992576725a0783fa68fe6990c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/openrisc/cpu.h
M target/openrisc/fpu_helper.c
M target/openrisc/helper.h
M target/openrisc/machine.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
Log Message:
-----------
target/openrisc: Replace target_ulong -> uint32_t
The OpenRISC targets are only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/or1k-*
configs/targets/or1k-linux-user.mak:5:TARGET_LONG_BITS=32
configs/targets/or1k-softmmu.mak:5:TARGET_LONG_BITS=32
Therefore target_ulong always expands to uint32_t. Replace and
adapt the API uses mechanically:
target_ulong -> uint32_t
target_long -> int32_t
tl -> i32
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
tcg_global_mem_new -> tcg_global_mem_new_i32
VMSTATE_UINTTL -> VMSTATE_UINT32
There is no functional change (the migration stream is not modified).
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: b4c93258a9d4e567d6e74d47cfcbbac0ff542bfa
https://github.com/qemu/qemu/commit/b4c93258a9d4e567d6e74d47cfcbbac0ff542bfa
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/riscv/kvm/kvm-cpu.c
Log Message:
-----------
target/riscv/kvm: Replace legacy cpu_physical_memory_read/write() calls
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Since the SBI DBCN is handled within a vCPU context, use its
default address space. Replace using the address space API.
As with the previous implementation, ignore whether the memory
accesses succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-Id: <[email protected]>
Commit: d936261844f68a07a3c51db08278eda273457d94
https://github.com/qemu/qemu/commit/d936261844f68a07a3c51db08278eda273457d94
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/riscv/monitor.c
Log Message:
-----------
target/riscv/monitor: Replace legacy cpu_physical_memory_read() call
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Propagate the address space to walk_pte(), then replace the
cpu_physical_memory_read() by address_space_read(). Since the
monitor command are run with a vCPU context, use its default
address space. As with the previous implementation, ignore
whether the memory read succeeded or failed.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Message-Id: <[email protected]>
Commit: 89e1cd7363e0a066a6b7a6059998efa3a89cc1b9
https://github.com/qemu/qemu/commit/89e1cd7363e0a066a6b7a6059998efa3a89cc1b9
Author: Anton Johansson <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Use 32 bits for misa extensions
uint32_t is already in use in most places storing misa extensions such
as CPUArchState::misa_exts, RISCVCPUProfile::misa_exts,
RISCVImpliedExtsRule::implied_misa_exts. Additionally. the field is
already migrated as uint32_t.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 886b0cea411691d6fd75fae97ab40ff833fdb9ed
https://github.com/qemu/qemu/commit/886b0cea411691d6fd75fae97ab40ff833fdb9ed
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/vector_helper.c
Log Message:
-----------
target/riscv: Replace HOST_BIG_ENDIAN #ifdef with if() check
Replace preprocessor-time #ifdef with a compile-time check
to ensure all code paths are built and tested. This reduces
build-time configuration complexity and simplifies code
maintainability.
No functional change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-Id: <[email protected]>
Commit: 2982b948a9faa8edd0c8a9366fab77cc1094e0a2
https://github.com/qemu/qemu/commit/2982b948a9faa8edd0c8a9366fab77cc1094e0a2
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Replace target_ulong -> vaddr for translator API uses
Since commit b1c09220b4c ("accel/tcg: Replace target_ulong with
vaddr in translator_*()") the API takes vaddr argument, not
target_ulong. Update the 2 callers.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0f4af4e2672040e505c7b337d48ec7cf2c1687bf
https://github.com/qemu/qemu/commit/0f4af4e2672040e505c7b337d48ec7cf2c1687bf
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Use MemOp type in gen_ld[u]() and gen_st()
The @size argument is of MemOp type. All callers respect that.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2062fa663c00927b4bfe63bd1d3f4614af3f0b9c
https://github.com/qemu/qemu/commit/2062fa663c00927b4bfe63bd1d3f4614af3f0b9c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Propagate DisasContext to generated helpers
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 8b71fd6ffec8787f0685ccce5f4dd9db50fea792
https://github.com/qemu/qemu/commit/8b71fd6ffec8787f0685ccce5f4dd9db50fea792
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Propagate DisasContext to push() / pop()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 363fff6d1b1f71b4f41c490076127ce3021bffc0
https://github.com/qemu/qemu/commit/363fff6d1b1f71b4f41c490076127ce3021bffc0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Propagate DisasContext to gen_ld[u]() and gen_st()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: cb8e4556d584c89e58fcff1757df7e2bf2553a3e
https://github.com/qemu/qemu/commit/cb8e4556d584c89e58fcff1757df7e2bf2553a3e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Factor mo_endian() helper out
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f9903a8a23ec14a8bef1d9af908e505c44b977af
https://github.com/qemu/qemu/commit/f9903a8a23ec14a8bef1d9af908e505c44b977af
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Replace MO_TE -> MO_LE
We only build the RX targets using little endianness order:
$ git grep TARGET_BIG_ENDIAN configs/targets/rx-*
$
Therefore the MO_TE definition always expands to MO_LE.
Use the latter to simplify.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 86114e43ffda717c0ed4225e5d5ddf315e930835
https://github.com/qemu/qemu/commit/86114e43ffda717c0ed4225e5d5ddf315e930835
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Expand TCG register definitions for 32-bit target
The RX target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/rx-*
configs/targets/rx-softmmu.mak:5:TARGET_LONG_BITS=32
Therefore target_ulong always expands to uint32_t.
Replace and adapt the API uses mechanically:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
There is no functional change.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: bec018f122677a2e53b7f914c20663986faf2cf0
https://github.com/qemu/qemu/commit/bec018f122677a2e53b7f914c20663986faf2cf0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/rx/translate.c
Log Message:
-----------
target/rx: Un-inline various helpers
Rely on the linker to optimize at linking time.
Suggested-by: Richard Henderson <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6d9dad71265cda5888d4779681977c5b389730a2
https://github.com/qemu/qemu/commit/6d9dad71265cda5888d4779681977c5b389730a2
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/s390x/tcg/translate.c
M target/s390x/tcg/translate_vx.c.inc
Log Message:
-----------
target/s390x: Replace HOST_BIG_ENDIAN #ifdef with if() check
Replace preprocessor-time #ifdef with a compile-time check
to ensure all code paths are built and tested. This reduces
build-time configuration complexity and simplifies code
maintainability.
No functional change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: David Hildenbrand <[email protected]>
Message-Id: <[email protected]>
Commit: 82a1e739010b3134862b27123684c26cd3b471e7
https://github.com/qemu/qemu/commit/82a1e739010b3134862b27123684c26cd3b471e7
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/cpu.h
Log Message:
-----------
target/sh4: Convert CPUSH4State::sr register to uint32_t type
Since its introduction in commit fdf9b3e831e the %SR register
is a uint32_t type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: c954994968f8bb38087dcc6401560100ee3fc78c
https://github.com/qemu/qemu/commit/c954994968f8bb38087dcc6401560100ee3fc78c
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/cpu.h
M target/sh4/helper.c
Log Message:
-----------
target/sh4: Remove target_ulong use in cpu_sh4_is_cached()
Since commit 852d481faf7 ("SH: Improve movca.l/ocbi emulation")
helper_movcal() pass a uint32_t type to cpu_sh4_is_cached().
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: b0469ec667cf8d507dd4b23b6ed9e7e7082abbeb
https://github.com/qemu/qemu/commit/b0469ec667cf8d507dd4b23b6ed9e7e7082abbeb
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/helper.c
Log Message:
-----------
target/sh4: Use hwaddr type for hardware addresses
The CPUClass::get_phys_page_debug() handler returns a 'hwaddr' type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 0edd1789c738af6ce825106d7f331fedf546ee77
https://github.com/qemu/qemu/commit/0edd1789c738af6ce825106d7f331fedf546ee77
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/helper.c
Log Message:
-----------
target/sh4: Remove target_ulong uses in superh_cpu_get_phys_page_debug
The CPUClass::get_phys_page_debug() handler takes a 'vaddr' address
type since commit 00b941e581b ("cpu: Turn cpu_get_phys_page_debug()
into a CPUClass hook").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 42c90609b8fd405b34e1d05fb8495068521759b7
https://github.com/qemu/qemu/commit/42c90609b8fd405b34e1d05fb8495068521759b7
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/helper.c
Log Message:
-----------
target/sh4: Use vaddr type for TLB virtual addresses
tlb_flush_page() expects a vaddr type since commit 732d548732e
("accel: Replace target_ulong in tlb_*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 90470a5fcc57b29703fbab5e3ff9c05d420e39f0
https://github.com/qemu/qemu/commit/90470a5fcc57b29703fbab5e3ff9c05d420e39f0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sh4/translate.c
Log Message:
-----------
target/sh4: Remove target_ulong use in gen_goto_tb()
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 7b2325470ebf9f1414ef4782f7560156e8241f7d
https://github.com/qemu/qemu/commit/7b2325470ebf9f1414ef4782f7560156e8241f7d
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/sparc/cpu.h
M target/sparc/helper.c
M target/sparc/int64_helper.c
Log Message:
-----------
target/sparc: Reduce inclusions of 'exec/cpu-common.h'
Only 2 files require declarations from "exec/cpu-common.h".
Include it there once, instead than polluting all files
including "cpu.h".
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Commit: 809b460f30501fac008c13f23e6c0c127b8260bd
https://github.com/qemu/qemu/commit/809b460f30501fac008c13f23e6c0c127b8260bd
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Remove target_ulong use in gen_goto_tb()
translator_use_goto_tb() expects a vaddr type since commit
b1c09220b4c ("accel/tcg: Replace target_ulong with vaddr in
translator_*()").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 0d5f95425614ba5281177f76ab438756d8213317
https://github.com/qemu/qemu/commit/0d5f95425614ba5281177f76ab438756d8213317
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/helper.c
Log Message:
-----------
target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
tlb_fill() provides a vaddr type since commit 68d6eee73c
("target/tricore: Convert to CPUClass::tlb_fill").
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: a15e899626893b5201b7b307090148ca7ff25e66
https://github.com/qemu/qemu/commit/a15e899626893b5201b7b307090148ca7ff25e66
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Remove target_ulong use in translate_insn() handler
Since commit 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase
for virtual addresses") the DisasContextBase::pc_first field is a
vaddr type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 44e2b68d275340c23f21f37f7c44e25c1b7543c9
https://github.com/qemu/qemu/commit/44e2b68d275340c23f21f37f7c44e25c1b7543c9
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Remove target_ulong use in gen_addi_d()
Callers pass either int32_t or int16_t.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 30257dcd2b0b8aeefc0c4b8ee10524037111a0f4
https://github.com/qemu/qemu/commit/30257dcd2b0b8aeefc0c4b8ee10524037111a0f4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/cpu.c
Log Message:
-----------
target/tricore: Remove unnecessary cast to target_ulong
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: c558aa942119afb0c1a852a85be81b8f6e2c8b5b
https://github.com/qemu/qemu/commit/c558aa942119afb0c1a852a85be81b8f6e2c8b5b
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/op_helper.c
Log Message:
-----------
target/tricore: Replace target_ulong -> uint32_t in op_helper.c
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore target_ulong type always expands to uint32_t.
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 6b2e4fcb836cdd4b770086db03e07d0ff93f9612
https://github.com/qemu/qemu/commit/6b2e4fcb836cdd4b770086db03e07d0ff93f9612
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Declare registers as TCGv_i32
CPUTriCoreState register are declared as uint32_t since the
target introduction in commit 48e06fe0ed8 ("target-tricore:
Add target stubs and qom-cpu").
Mechanical replacement of:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: f30c8aa229da11b40eb3a2e696e7e79d639c21fd
https://github.com/qemu/qemu/commit/f30c8aa229da11b40eb3a2e696e7e79d639c21fd
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Inline tcg_gen_ld32u_tl()
The TriCore target is only built as 32-bit, so tcg_gen_ld32u_tl()
expands to tcg_gen_ld_i32(). Use the latter to simplify the next
commit mechanical change.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 4f08815467e5cfbd3f117f34b11da1beb613b775
https://github.com/qemu/qemu/commit/4f08815467e5cfbd3f117f34b11da1beb613b775
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Expand TCG helpers for 32-bit target
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Therefore tcg_FOO_tl() always expands to tcg_FOO_i32().
This is a mechanical replacement.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: e843ef2bbace2cac9e9b92869c4b69c175d6ca72
https://github.com/qemu/qemu/commit/e843ef2bbace2cac9e9b92869c4b69c175d6ca72
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Pass DisasContext as first argument
Unify style, always pass DisasContext as the first argument.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 8a2235dd077b4715b635628a0cdde835a732ea51
https://github.com/qemu/qemu/commit/8a2235dd077b4715b635628a0cdde835a732ea51
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Un-inline various helpers
Rely on the linker to optimize at linking time.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: cd08bcaa36b4c0437b2d61f9906bf78b99aa3684
https://github.com/qemu/qemu/commit/cd08bcaa36b4c0437b2d61f9906bf78b99aa3684
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/tricore/translate.c
Log Message:
-----------
target/tricore: Expand TCGv type for 32-bit target
The TriCore target is only built as 32-bit:
$ git grep TARGET_LONG_BITS configs/targets/tricore-*
configs/targets/tricore-softmmu.mak:2:TARGET_LONG_BITS=32
Replace:
TCGv -> TCGv_i32
tcg_temp_new -> tcg_temp_new_i32
This is a mechanical replacement, adapting style to pass
the checkpatch.pl script.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 2b6cea17be35d46021ecd9b9dcceaed7b6200dbe
https://github.com/qemu/qemu/commit/2b6cea17be35d46021ecd9b9dcceaed7b6200dbe
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/xtensa/xtensa-semi.c
Log Message:
-----------
target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
Commit b7ecba0f6f6 ("docs/devel/loads-stores.rst: Document our
various load and store APIs") mentioned cpu_physical_memory_*()
methods are legacy, the replacement being address_space_*().
Replace the *_map() / *_unmap() methods in the SIMCALL helper,
using the vCPU default address space. No behavioral change expected.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-Id: <[email protected]>
Reviewed-by: Manos Pitsidianakis <[email protected]>
Commit: fead65d20513f005fcc589eab744f6aa88c60f37
https://github.com/qemu/qemu/commit/fead65d20513f005fcc589eab744f6aa88c60f37
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/xtensa/translate.c
Log Message:
-----------
target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
Since commit 85c19af63e7 ("include/exec: Use vaddr in DisasContextBase
for virtual addresses") the DisasContextBase::pc_first field is a
vaddr type.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 91edb16601da768dc443a46fb8bcb77900f18864
https://github.com/qemu/qemu/commit/91edb16601da768dc443a46fb8bcb77900f18864
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/xtensa/cpu.c
Log Message:
-----------
target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
Since commit bb5de52524c ("target: Widen pc/cs_base in
cpu_get_tb_cpu_state"), cpu_get_tb_cpu_state() expects
a uint64_t type for cs_base.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Message-Id: <[email protected]>
Commit: 91fc6d8101de97c588e0a4263cf4f6148b3e702a
https://github.com/qemu/qemu/commit/91fc6d8101de97c588e0a4263cf4f6148b3e702a
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M linux-user/microblaze/elfload.c
Log Message:
-----------
linux-user/microblaze: Fix little-endianness binary
MicroBlaze CPU model has a "little-endian" property, pointing to
the @endi internal field. Commit c36ec3a9655 ("hw/microblaze:
Explicit CPU endianness") took care of having all MicroBlaze
boards with an explicit default endianness, so later commit
415aae543ed ("target/microblaze: Consider endianness while
translating code") could infer the endianness at runtime from
the @endi field, and not a compile time via the TARGET_BIG_ENDIAN
definition. Doing so, we forgot to make the endianness explicit
on user emulation, so there all CPUs are started with the default
"little-endian=off" value, leading to breaking support for little
endian binaries:
$ readelf -h ./hello-world-mbel
ELF Header:
Magic: 7f 45 4c 46 01 01 01 00 00 00 00 00 00 00 00 00
Class: ELF32
Data: 2's complement, little endian
$ qemu-microblazeel ./hello-world-mbel
qemu: uncaught target signal 11 (Segmentation fault) - core dumped
Segmentation fault (core dumped)
Fix by restoring the previous behavior of starting with the
builtin endianness of the binary:
$ qemu-microblazeel ./hello-world-mbel
Hello World
Cc: [email protected]
Fixes: 415aae543ed ("target/microblaze: Consider endianness while translating
code")
Reported-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
Message-Id: <[email protected]>
Commit: 8dd133fa85bb49e2e61c489a566ab8460478dc24
https://github.com/qemu/qemu/commit/8dd133fa85bb49e2e61c489a566ab8460478dc24
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .mailmap
Log Message:
-----------
mailmap: Unify Clément Mathieu--Drif emails
Do not let git-shortlog make distinction between:
. Clément Mathieu--Drif
. Clement Mathieu--Drif
. CLEMENT MATHIEU--DRIF
as this is the same person.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Clément Mathieu--Drif <[email protected]>
Message-Id: <[email protected]>
Commit: 9b03e9cf06b33192d550564169f36eee07cf9fd0
https://github.com/qemu/qemu/commit/9b03e9cf06b33192d550564169f36eee07cf9fd0
Author: Thomas Huth <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M python/qemu/machine/README.rst
M python/qemu/utils/README.rst
Log Message:
-----------
python/qemu: Replace some remaining "avocados" with "functional tests"
The avocado tests have been replaced by the new functional tests,
so also update this in the README.rst files in the python directory
accordingly.
Reviewed-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Michael Tokarev <[email protected]>
Reviewed-by: Alex Bennée <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: dadd7419d361f8f9f012cbc1413993132cd55b7a
https://github.com/qemu/qemu/commit/dadd7419d361f8f9f012cbc1413993132cd55b7a
Author: Thomas Huth <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_sbsaref_alpine.py
Log Message:
-----------
tests/functional/aarch64: Drop some sbsaref_alpine tests
test_sbsaref_alpine is one of the longest running test in our testsuite,
because it does a full Linux boot a couple of times, for various different
CPU configurations. That's quite a lot of testing each time, for a rather
small additional test coverage. Thus let's drop some of the tests that don't
provide much in addition to the other ones.
Suggested-by: Alex Bennée <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: 1d7fdee97b8959871d4093d89a79192155ca674f
https://github.com/qemu/qemu/commit/1d7fdee97b8959871d4093d89a79192155ca674f
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .gitlab-ci.d/windows.yml
Log Message:
-----------
gitlab: purge msys pacman cache
For the Windows msys2 CI job we install many packages using pacman
and use the GitLab cache to preserve the pacman cache across CI
runs. While metadata still needs downloading, this avoids pacman
re-downloading packages from msys2 if they have not changed.
The problem is that pacman never automatically purges anything
from its package cache. Thus the GitLab cache is growing without
bound and packing/unpacking the cache is consuming an increasing
amount of time in the CI job.
If we run 'pacman -Sc' /after/ installing our desired package set,
it will purge any cached downloaded packages that are not matching
any installed package.
This will (currently) cap the pacman download cache at approx
256 MB.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Reviewed-by: Yonggang Luo <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: cb1379ce646e9f41b096c4d7590e558393e6e960
https://github.com/qemu/qemu/commit/cb1379ce646e9f41b096c4d7590e558393e6e960
Author: Thomas Huth <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M tests/functional/qemu_test/asset.py
Log Message:
-----------
tests/functional: Set current time stamp of assets when using them
We are going to remove obsolete assets from the cache, so keep
the time stamps of the assets that we use up-to-date to have a way
to detect stale assets later.
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: dd10dbe61751dc85a4d84ffde73f341ab027eb73
https://github.com/qemu/qemu/commit/dd10dbe61751dc85a4d84ffde73f341ab027eb73
Author: Thomas Huth <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M MAINTAINERS
A scripts/clean_functional_cache.py
M tests/Makefile.include
Log Message:
-----------
tests: Evict stale files in the functional download cache after a while
The download cache of the functional tests is currently only growing.
But sometimes tests get removed or changed to use different assets,
thus we should clean up the stale old assets after a while when they
are not in use anymore. So add a script that looks at the time stamps
of the assets and removes them if they haven't been touched for more
than half of a year. Since there might also be some assets around that
have been added to the cache before we added the time stamp files,
assume a default time stamp that is close to the creation date of this
patch, so that we don't delete these files too early (so we still have
all assets around in case we have to bisect an issue in the recent past
of QEMU).
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: 420f6c041705ebc9a7faf3cc0fd6deba865694ae
https://github.com/qemu/qemu/commit/420f6c041705ebc9a7faf3cc0fd6deba865694ae
Author: Thomas Huth <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M tests/functional/alpha/test_clipper.py
Log Message:
-----------
tests/functional/alpha: Remove superfluous fetch() line from the clipper test
The kernel asset is retrieved automatically via the uncompress()
line below the fetch(), so the fetch() is simply not necessary here.
Reviewed-by: Richard Henderson <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Commit: 5c2a4b59fad21a3e71b7a8c155d374af952b585f
https://github.com/qemu/qemu/commit/5c2a4b59fad21a3e71b7a8c155d374af952b585f
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M tests/functional/reverse_debugging.py
Log Message:
-----------
tests/functional: remove use of getLogger in reverse debuging
This fixes the gap left by
commit 8a44d8c2ac0921c8064fbfd00ef28e3a2588918e
Author: Daniel P. Berrangé <[email protected]>
Date: Fri Sep 12 19:22:00 2025 +0100
tests/functional: use self.log for all logging
ensuring that log message from the reverse debugging test actually
make it into the logfile on disk.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Tested-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 03ec40942d678ef1e98439508d1cdb2c05ff3e72
https://github.com/qemu/qemu/commit/03ec40942d678ef1e98439508d1cdb2c05ff3e72
Author: Daniel P. Berrangé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M tests/functional/reverse_debugging.py
Log Message:
-----------
tests/functional: ensure GDB client is stopped on error
If the reverse_debugging_run method fails, the GDB client will not
be closed resulting in python complaining about resource leaks.
Hoisting the GDB client creation into the caller allows this to
be cleaned up easily. While doing this, also move the VM shutdown
call to match.
Signed-off-by: Daniel P. Berrangé <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 02cf15e9bbe902523f5a1deb1dd48aef50e26e41
https://github.com/qemu/qemu/commit/02cf15e9bbe902523f5a1deb1dd48aef50e26e41
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/s390x/mmu_helper.c
Log Message:
-----------
target/s390x/mmu_helper: Simplify s390_cpu_virt_mem_rw() logic
In order to simplify the next commit, move the
trigger_access_exception() call after the address_space_rw()
calls. No logical change intended.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: d6f7f9254e333c56226bb7051e74ea57daea2fff
https://github.com/qemu/qemu/commit/d6f7f9254e333c56226bb7051e74ea57daea2fff
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M target/s390x/mmu_helper.c
Log Message:
-----------
target/s390x/mmu_helper: Do not ignore address_space_rw() errors
If a address_space_rw() call ever fails, break the loop and
return the PGM_ADDRESSING error (after triggering an access
exception).
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Signed-off-by: Thomas Huth <[email protected]>
Commit: 3ad3326bd658dd3bb210d5f2997e6b9a913ccb95
https://github.com/qemu/qemu/commit/3ad3326bd658dd3bb210d5f2997e6b9a913ccb95
Author: Richard Henderson <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .mailmap
M linux-user/microblaze/elfload.c
M target/alpha/helper.h
M target/alpha/machine.c
M target/alpha/sys_helper.c
M target/alpha/translate.c
M target/arm/tcg/translate-a64.c
M target/arm/tcg/translate.c
M target/avr/translate.c
M target/hexagon/translate.c
M target/hppa/cpu.h
M target/hppa/helper.c
M target/hppa/insns.decode
M target/hppa/mem_helper.c
M target/hppa/trace-events
M target/hppa/translate.c
M target/i386/monitor.c
M target/loongarch/cpu-mmu.h
M target/loongarch/cpu_helper.c
M target/loongarch/gdbstub.c
M target/loongarch/machine.c
M target/loongarch/tcg/helper.h
M target/loongarch/tcg/insn_trans/trans_privileged.c.inc
M target/loongarch/tcg/tlb_helper.c
M target/loongarch/tcg/translate.c
M target/m68k/translate.c
M target/microblaze/cpu.h
M target/microblaze/helper.c
M target/microblaze/helper.h
M target/microblaze/machine.c
M target/microblaze/mmu.c
M target/microblaze/mmu.h
M target/microblaze/op_helper.c
M target/microblaze/translate.c
M target/mips/tcg/translate.c
M target/openrisc/cpu.h
M target/openrisc/fpu_helper.c
M target/openrisc/helper.h
M target/openrisc/machine.c
M target/openrisc/mmu.c
M target/openrisc/sys_helper.c
M target/openrisc/translate.c
M target/ppc/translate.c
M target/riscv/cpu.h
M target/riscv/insn_trans/trans_rvv.c.inc
M target/riscv/kvm/kvm-cpu.c
M target/riscv/monitor.c
M target/riscv/translate.c
M target/riscv/vector_helper.c
M target/rx/translate.c
M target/s390x/tcg/translate.c
M target/s390x/tcg/translate_vx.c.inc
M target/sh4/cpu.h
M target/sh4/helper.c
M target/sh4/translate.c
M target/sparc/cpu.h
M target/sparc/helper.c
M target/sparc/int64_helper.c
M target/sparc/translate.c
M target/tricore/cpu.c
M target/tricore/helper.c
M target/tricore/op_helper.c
M target/tricore/translate.c
M target/xtensa/cpu.c
M target/xtensa/translate.c
M target/xtensa/xtensa-semi.c
Log Message:
-----------
Merge tag 'single-binary-20251016' of https://github.com/philmd/qemu into
staging
Various patches related to single binary work:
- Remove some VMSTATE_UINTTL() uses
- Replace target_ulong by vaddr / hwaddr / uint[32,64]_t
- Expand TCGv to TCGv_i32 for 32-bit targets
- Remove some unnecessary checks on TARGET_LONG_BITS
- Replace few HOST_BIG_ENDIAN preprocessor #ifdef by compile-time if() check
- Expand MO_TE to either MO_BE or MO_LE
Also:
- Remove legacy cpu_physical_memory_*() calls
- Fix HPPA FMPYADD opcode
- Unify Clément Mathieu--Drif email addresses
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# gpg: Signature made Thu 16 Oct 2025 08:09:22 AM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'single-binary-20251016' of https://github.com/philmd/qemu: (79 commits)
mailmap: Unify Clément Mathieu--Drif emails
linux-user/microblaze: Fix little-endianness binary
target/xtensa: Remove target_ulong use in xtensa_get_tb_cpu_state()
target/xtensa: Remove target_ulong use in xtensa_tr_translate_insn()
target/xtensa: Replace legacy cpu_physical_memory_[un]map() calls
target/tricore: Expand TCGv type for 32-bit target
target/tricore: Un-inline various helpers
target/tricore: Pass DisasContext as first argument
target/tricore: Expand TCG helpers for 32-bit target
target/tricore: Inline tcg_gen_ld32u_tl()
target/tricore: Declare registers as TCGv_i32
target/tricore: Replace target_ulong -> uint32_t in op_helper.c
target/tricore: Remove unnecessary cast to target_ulong
target/tricore: Remove target_ulong use in gen_addi_d()
target/tricore: Remove target_ulong use in translate_insn() handler
target/tricore: Replace target_ulong -> vaddr with tlb_fill() callees
target/tricore: Remove target_ulong use in gen_goto_tb()
target/sparc: Reduce inclusions of 'exec/cpu-common.h'
target/sh4: Remove target_ulong use in gen_goto_tb()
target/sh4: Use vaddr type for TLB virtual addresses
...
Signed-off-by: Richard Henderson <[email protected]>
Commit: 18f6f30b0089b470f3e737637a86dfb81ebd6eae
https://github.com/qemu/qemu/commit/18f6f30b0089b470f3e737637a86dfb81ebd6eae
Author: Richard Henderson <[email protected]>
Date: 2025-10-16 (Thu, 16 Oct 2025)
Changed paths:
M .gitlab-ci.d/windows.yml
M MAINTAINERS
M python/qemu/machine/README.rst
M python/qemu/utils/README.rst
A scripts/clean_functional_cache.py
M target/s390x/mmu_helper.c
M tests/Makefile.include
M tests/functional/aarch64/test_sbsaref_alpine.py
M tests/functional/alpha/test_clipper.py
M tests/functional/qemu_test/asset.py
M tests/functional/reverse_debugging.py
Log Message:
-----------
Merge tag 'pull-request-2025-10-16' of https://gitlab.com/thuth/qemu into
staging
* Improve cache handling for the msys2 CI and the functional asset cache
* Clean ups for some minor issues in functional tests
* Don't ignore errors of address_space_rw in s390x MMU code
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# gpg: Signature made Thu 16 Oct 2025 09:25:16 AM PDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "[email protected]"
# gpg: Good signature from "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: aka "Thomas Huth <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-10-16' of https://gitlab.com/thuth/qemu:
target/s390x/mmu_helper: Do not ignore address_space_rw() errors
target/s390x/mmu_helper: Simplify s390_cpu_virt_mem_rw() logic
tests/functional: ensure GDB client is stopped on error
tests/functional: remove use of getLogger in reverse debuging
tests/functional/alpha: Remove superfluous fetch() line from the clipper test
tests: Evict stale files in the functional download cache after a while
tests/functional: Set current time stamp of assets when using them
gitlab: purge msys pacman cache
tests/functional/aarch64: Drop some sbsaref_alpine tests
python/qemu: Replace some remaining "avocados" with "functional tests"
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/8109ebdb95c4...18f6f30b0089
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