Branch: refs/heads/master
Home: https://github.com/qemu/qemu
Commit: 18beee5c6bb875ec5a1455e5e7118338701e2a16
https://github.com/qemu/qemu/commit/18beee5c6bb875ec5a1455e5e7118338701e2a16
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-09 (Thu, 09 Oct 2025)
Changed paths:
M rust/hw/char/pl011/src/registers.rs
Log Message:
-----------
rust: pl011: fix warning with new clippy
Newer versions of clippy are able to see that all the variants in
the PL011 word length enum end with "Bits", and complain about it.
Allow it.
Reported-by: Richard Henderson <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2dc5298d31d7ee86b9204de0b3b9c9fda294c3ae
https://github.com/qemu/qemu/commit/2dc5298d31d7ee86b9204de0b3b9c9fda294c3ae
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_aspeed_ast2700.py
M tests/functional/aarch64/test_aspeed_ast2700fc.py
Log Message:
-----------
tests/functional/aarch64/aspeed_ast2700: Add PCIe and network tests
Extend the AST2700 and AST2700fc functional tests with PCIe and network
checks.
This patch introduces a helper "do_ast2700_pcie_test()" that runs "lspci"
on the emulated system and verifies the expected PCIe devices:
- 0002:00:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
- 0002:01:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
Connection
Additional changes:
- Add `-device e1000e,netdev=net1,bus=pcie.2 -netdev user,id=net1` to the
AST2700 and AST2700fc test machines.
- In the AST2700 vbootrom test, assign an IP address to the e1000e
interface and verify it using `ip addr`.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 4fcb15ebc262b767743ca97e42cc4041b00b9193
https://github.com/qemu/qemu/commit/4fcb15ebc262b767743ca97e42cc4041b00b9193
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Don't set 'auto_create_sdcard'
The Aspeed machines inherited from a 'no_sdcard' attribute when first
introduced in QEMU. This attribute was later renamed to
'auto_create_sdcard' by commit cdc8d7cadaac ("hw/boards: Rename
no_sdcard -> auto_create_sdcard") and set to 'true'. This has the
indesirable efect to automatically create SD cards at init time.
Remove 'auto_create_sdcard' to avoid creating a SD card device.
Cc: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c0c05762804f33f3c5edbde77ecadbc315dfee3a
https://github.com/qemu/qemu/commit/c0c05762804f33f3c5edbde77ecadbc315dfee3a
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast1030.py
Log Message:
-----------
tests/functional/arm/test_aspeed_ast1030: Update test ASPEED SDK v03.03
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 47105ec4dca077d0c535a02adb40645205106da5
https://github.com/qemu/qemu/commit/47105ec4dca077d0c535a02adb40645205106da5
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast2500.py
Log Message:
-----------
tests/functional/arm/test_aspeed_ast2500: Update test ASPEED SDK v09.08
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c4a9ecac40b360d1ebfc381981052d9e5024df16
https://github.com/qemu/qemu/commit/c4a9ecac40b360d1ebfc381981052d9e5024df16
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast2600.py
Log Message:
-----------
tests/functional/arm/test_aspeed_ast2600: Update test ASPEED SDK v09.08
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: fecf7b8e4cb6c23f5c7f1a12d511c26fb61756bf
https://github.com/qemu/qemu/commit/fecf7b8e4cb6c23f5c7f1a12d511c26fb61756bf
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_aspeed_ast2700.py
Log Message:
-----------
tests/functional/aarch64/test_aspeed_ast2700: Update test ASPEED SDK v09.08
for A1
Support for AST2700 A0 was dropped starting from SDK v09.07.
The new SDK v09.08 only updates support for AST2700 A1.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 783559aece0c0e59c35a8c63954f841d89a661b5
https://github.com/qemu/qemu/commit/783559aece0c0e59c35a8c63954f841d89a661b5
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_aspeed_ast2700.py
Log Message:
-----------
tests/functional/aarch64/test_aspeed_ast2700: Move eth2 IP check into common
function
The eth2 IP address check was previously only performed in
test_aarch64_ast2700a1_evb_sdk_vbootrom_v09_08. This patch moves the
check into do_ast2700_pcie_test(), ensuring it is executed consistently
across all AST2700 PCIe test runs. This avoids code duplication.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 511ea9a865f7da820bea5dc22c9340e5d4fc32f5
https://github.com/qemu/qemu/commit/511ea9a865f7da820bea5dc22c9340e5d4fc32f5
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/arm/meson.build
R tests/functional/arm/test_aspeed_ast2600.py
A tests/functional/arm/test_aspeed_ast2600_buildroot.py
A tests/functional/arm/test_aspeed_ast2600_sdk.py
Log Message:
-----------
tests/functional/arm: Split the ast2600 tests in two files
The ast2600 test file currently includes tests for both the Buildroot
and SDK images. Since the SDK image tests can take long to run, split
them into a separate file to clearly distinguish the two sets of
tests, improve parallelism and allow for different CI timeouts.
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Jamin Lin <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: acd290b01726294d12f93d64e9ff1dd14f524d61
https://github.com/qemu/qemu/commit/acd290b01726294d12f93d64e9ff1dd14f524d61
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M docs/about/deprecated.rst
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Deprecate the sonorapass-bmc machine
The 'sonorapass-bmc' machine represents a lab server that never
entered production. There are no functional tests for this machine
which makes harder to determine when something becomes deprecated or
unused.
Since the machine does not rely on any specific device models, it can
be replaced by the 'ast2500-evb' machine using the 'fmc-model' option
to specify the flash type. The I2C devices connected to the board can
be defined via the QEMU command line.
Cc: Patrick Williams <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b3b3b5be9cca7741bdf195d6ea7d39e5926b8c5c
https://github.com/qemu/qemu/commit/b3b3b5be9cca7741bdf195d6ea7d39e5926b8c5c
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M docs/about/deprecated.rst
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Deprecate the qcom-dc-scm-v1-bmc and qcom-firework-bmc machines
There are no functional tests for the 'qcom-dc-scm-v1-bmc' and
'qcom-firework-bmc' machines which makes harder to determine when
something becomes deprecated or unused.
Since the machines do not rely on any specific device models, they can
be replaced by the 'ast2600-evb' machine using the 'fmc-model' option
to specify the flash type. The I2C devices connected to the board can
be defined via the QEMU command line.
Cc: Jae Hyun Yoo <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a7fd1fd7b3b19fb1a597d62d9c01edfc5ff483aa
https://github.com/qemu/qemu/commit/a7fd1fd7b3b19fb1a597d62d9c01edfc5ff483aa
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M docs/about/deprecated.rst
M hw/arm/aspeed.c
Log Message:
-----------
aspeed: Deprecate the fp5280g2-bmc machine
There are no functional tests for the 'fp5280g2-bmc' machine which
makes harder to determine when something becomes deprecated or unused.
Since the machine does not rely on any specific device models, it can
be replaced by the 'ast2500-evb' machine using the 'fmc-model' option
to specify the flash type. The I2C devices connected to the board can
be defined via the QEMU command line.
Cc: John Wang <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 3c17823e2940c0a7756246eb57b5971ecfe197b6
https://github.com/qemu/qemu/commit/3c17823e2940c0a7756246eb57b5971ecfe197b6
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_aspeed_ast2700.py
Log Message:
-----------
test/functional/aarch64: Remove test for the ast2700a0-evb machine
The 'ast2700a0-evb' machine was deprecated in commit 6888a4a9c860 and
removal is scheduled in the QEMU 11.0 release. This change removes
the corresponding tests ahead of time to save CI resources.
Cc: Thomas Huth <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Jamin Lin <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 1f993447cf432cf1d2bf12284e80b395518ea0bc
https://github.com/qemu/qemu/commit/1f993447cf432cf1d2bf12284e80b395518ea0bc
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M tests/functional/aarch64/test_aspeed_ast2700.py
Log Message:
-----------
test/functional/aarch64: Split the ast2700a1-evb OpenBMC boot test
The 'ast2700a1-evb' machine has two functional tests: one loading
firmware components into memory and another using a vbootrom
image. Both tests perform a full OpenBMC boot and run checks on I2C
and PCIe devices, which is redundant and time-consuming.
To save CI resources, the vbootrom test is refactored to focus on the
firmware boot process only. The OpenBMC boot verification logic is
split and a new verify_openbmc_boot_start() helper is introduced to
only wait for the kernel to start.
The vbootrom test now uses this function and the less essential I2C
and PCIe checks have been removed from this test case.
Cc: Thomas Huth <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Jamin Lin <[email protected]>
Link: https://lore.kernel.org/qemu-devel/[email protected]
[ clg: Changed pattern from 'Starting kernel ...' to 'Linux version ' ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 03c9c22f9019a98973227bc49db8819a35e78680
https://github.com/qemu/qemu/commit/03c9c22f9019a98973227bc49db8819a35e78680
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API
Refactor the aspeed_uart_first() helper to remove its dependency on
AspeedSoCState and make the UART helper APIs more generic.
The function now takes uarts_base as an integer parameter instead of
requiring a full SoC class instance. Corresponding call sites in
aspeed.c and aspeed_soc_common.c are updated accordingly.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 37d2e4b5339ac3d584f8c9b0396c9060f52f12a0
https://github.com/qemu/qemu/commit/37d2e4b5339ac3d584f8c9b0396c9060f52f12a0
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API
Refactor the aspeed_uart_last() helper to remove its dependency on
AspeedSoCClass and make the UART helper APIs more generic.
The function now takes uarts_base and uarts_num as integer
parameters instead of requiring a full SoC class instance.
All related call sites in aspeed.c are updated accordingly.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8f1ceec735cb3b44b68ee7dd129d8844f81e39c3
https://github.com/qemu/qemu/commit/8f1ceec735cb3b44b68ee7dd129d8844f81e39c3
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_soc_common.c
M hw/arm/fby35.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_soc_uart_set_chr() API
Refactor the aspeed_soc_uart_set_chr() helper to remove its dependency
on AspeedSoCState and make the UART character device binding more
generic.
The function now takes SerialMM *uart, uarts_base, and uarts_num
as arguments instead of relying on AspeedSoCState. All affected call
sites in aspeed.c, aspeed_ast27x0-fc.c, and fby35.c are updated
to use the new parameter format.
This improves API flexibility and enables reuse across different Aspeed
SoC variants without requiring access to internal SoC state.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: bb3219345aa195b1ac3d0c91ab30d90d2fc85c16
https://github.com/qemu/qemu/commit/bb3219345aa195b1ac3d0c91ab30d90d2fc85c16
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API
Refactor the aspeed_soc_cpu_type() helper to remove its dependency on
AspeedSoCClass and make CPU type retrieval more generic.
The function now takes valid_cpu_types as a const char * const *
parameter instead of requiring a full AspeedSoCClass instance.
All corresponding call sites in various Aspeed SoC initialization files
(aspeed_ast10x0.c, aspeed_ast2400.c, aspeed_ast2600.c,
aspeed_ast27x0.c, and related variants) are updated accordingly.
This change simplifies the API, eliminates unnecessary type coupling,
and improves code reusability across different SoC families.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 448c4502a50bc4fc056726d5953eb873a2794486
https://github.com/qemu/qemu/commit/448c4502a50bc4fc056726d5953eb873a2794486
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API
Refactor aspeed_mmio_map() to take MemoryRegion * instead of
AspeedSoCState *, making the MMIO mapping helper more generic and
decoupled from SoC state.
Update all call sites to pass s->memory (or equivalent) explicitly.
Touched files include: headers, aspeed_soc_common.c, and SoC realize
paths in AST10x0/2400/2600/27x0 (SSP/TSP) and AST2700.
This reduces coupling, improves reuse across variants, and clarifies the
API boundary between SoC state and memory mapping.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 68f915b91cbf697b5f65a6aca72f260c6c29d00f
https://github.com/qemu/qemu/commit/68f915b91cbf697b5f65a6aca72f260c6c29d00f
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_mmio_map_unimplemented() API
Refactor aspeed_mmio_map_unimplemented() to take MemoryRegion *
instead of AspeedSoCState *, removing its dependency on SoC state and
aligning it with the updated aspeed_mmio_map() interface.
All related call sites are updated to explicitly pass s->memory.
Affected files include headers, aspeed_soc_common.c, and SoC realize
functions in AST10x0, AST2400, AST2600, AST27x0 (SSP/TSP), and AST2700.
This change simplifies the MMIO mapping helpers, improves API
consistency, and reduces coupling between SoC logic and memory
operations.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 15f26071bf424a564e177ab1ac746b85feda5286
https://github.com/qemu/qemu/commit/15f26071bf424a564e177ab1ac746b85feda5286
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_soc_uart_realize() API
Refactor aspeed_soc_uart_realize() to take MemoryRegion *, SerialMM *,
and MMIO base addr instead of AspeedSoCState *, decoupling the helper
from SoC state and making it reusable per-UART.
The helper now realizes a single UART instance and maps its MMIO.
IRQ wiring and iteration over all UARTs are moved to callers.
Update call sites in AST1030, AST2400, AST2600, AST27x0 SSP/TSP, and
AST2700 to loop over UARTs, call the new helper, and connect IRQ via
aspeed_soc_get_irq().
This simplifies the UART realize path and reduces cross-module coupling.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 21b3898a6984d0bc08c5a8b3f498ddfe4ff95e44
https://github.com/qemu/qemu/commit/21b3898a6984d0bc08c5a8b3f498ddfe4ff95e44
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Remove the aspeed_soc_get_irq and class get_irq hook
Remove the the common aspeed_soc_get_irq. Call sites are updated to use the
SoC-specific get_irq helpers directly (aspeed_soc_ast1030_get_irq(),
_aspeed2400_get_irq(), _ast2600_get_irq(), _ast27x0ssp_get_irq(),
_ast27x0tsp_get_irq(), and _ast2700_get_irq())
This makes the IRQ lookup explicit per-SoC and drops the exported
API that depended on AspeedSoCState, reducing cross-module coupling
in the common layer.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d183ef19a80867b6a1906417eda00f4ef17ffb77
https://github.com/qemu/qemu/commit/d183ef19a80867b6a1906417eda00f4ef17ffb77
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
A hw/arm/aspeed_coprocessor_common.c
M hw/arm/meson.build
A include/hw/arm/aspeed_coprocessor.h
Log Message:
-----------
hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
Add a new AspeedCoprocessor class that defines the foundational structure for
ASPEED coprocessor models. This class encapsulates a base DeviceState with
links to system memory, clock, and peripheral components such as SCU, SCUIO,
Timer Controller, and UARTs.
Introduce the corresponding implementation file
aspeed_coprocessor_common.c, which provides the aspeed_coprocessor_realize()
method, property registration, and QOM type registration. The class is marked
as abstract and intended to serve as a common base for specific coprocessor
variants (e.g. SSP/TSP subsystems).
This establishes a reusable and extensible framework for modeling ASPEED
coprocessor devices.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 860204de8a49bc687b11b98fff460a984d9321ce
https://github.com/qemu/qemu/commit/860204de8a49bc687b11b98fff460a984d9321ce
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/meson.build
M include/hw/arm/aspeed_coprocessor.h
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor
instead of AspeedSoC
Refactor the AST27x0 SSP implementation to derive from the newly introduced
AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class
contains many SoC-level fields and behaviors that are not applicable to
coprocessor subsystems like SSP, leading to unnecessary coupling and code size.
This change moves the Aspeed27x0SSPSoCState structure definition into
aspeed_coprocessor.h and updates related references in
aspeed_ast27x0-ssp.c and aspeed_ast27x0-fc.c to use
AspeedCoprocessorState and AspeedCoprocessorClass.
Key updates include:
- Replace inheritance from AspeedSoC -> AspeedCoprocessor.
- Replace type casts and class access macros (ASPEED_SOC_*) with
ASPEED_COPROCESSOR_*.
This refactor improves modularity, reduces memory footprint, and prepares
for future coprocessor variants to share a lighter-weight common base.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: bbdd4167fa7ab8b27527e00214c3b903cf30a737
https://github.com/qemu/qemu/commit/bbdd4167fa7ab8b27527e00214c3b903cf30a737
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/meson.build
M include/hw/arm/aspeed_coprocessor.h
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP inherit from AspeedCoprocessor
instead of AspeedSoC
Refactor the AST27x0 TSP implementation to derive from the newly introduced
AspeedCoprocessor base class rather than AspeedSoC. The AspeedSoC class
includes SoC-level infrastructure and peripheral definitions that are not
applicable to lightweight coprocessor subsystems such as TSP, resulting in
unnecessary coupling and complexity.
This change moves the Aspeed27x0TSPSoCState structure definition into
aspeed_coprocessor.h and updates all related references in
aspeed_ast27x0-tsp.c and aspeed_ast27x0-fc.c to use
AspeedCoprocessorState and AspeedCoprocessorClass.
Key updates include:
- Replace inheritance from AspeedSoC -> AspeedCoprocessor.
- Update type casts and macros from ASPEED_SOC_* to ASPEED_COPROCESSOR_*
This refactor improves modularity, reduces memory footprint, and prepares
for future coprocessor variants to share a lighter-weight common base.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9a255419e90c4ba4d68fd45ff4e962197a94304c
https://github.com/qemu/qemu/commit/9a255419e90c4ba4d68fd45ff4e962197a94304c
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-ssp.c
M include/hw/arm/aspeed_coprocessor.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState
Refactor the AST27x0 SSP implementation to use the unified
Aspeed27x0CoprocessorState structure shared between SSP and TSP.
Previously, SSP and TSP each defined separate state structures
(Aspeed27x0SSPSoCState and Aspeed27x0TSPSoCState), which contained
identical members and caused unnecessary code duplication.
This change removes Aspeed27x0SSPSoCState and replaces it with
Aspeed27x0CoprocessorState, consolidating shared coprocessor state fields
into a single definition in aspeed_coprocessor.h.
This refactor unifies SSP and TSP under the same coprocessor state type,
improving code maintainability and consistency across Aspeed coprocessor
implementations.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 012d952c20b254bad8cac51fb6b7f8d2af0c56db
https://github.com/qemu/qemu/commit/012d952c20b254bad8cac51fb6b7f8d2af0c56db
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-tsp.c
M include/hw/arm/aspeed_coprocessor.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-tsp: Change to use Aspeed27x0CoprocessorState
Refactor the AST27x0 TSP implementation to use the unified
Aspeed27x0CoprocessorState, matching the prior SSP change and removing the
duplicated Aspeed27x0TSPSoCState.
Key updates:
- Delete Aspeed27x0TSPSoCState and reuse Aspeed27x0CoprocessorState.
Update Ast2700FCState to declare tsp as Aspeed27x0CoprocessorState.
This aligns TSP with SSP on a single coprocessor state type, reducing code
duplication and simplifying maintenance.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f063ec2a5f8d89099b8b8d084b32020e9cda9280
https://github.com/qemu/qemu/commit/f063ec2a5f8d89099b8b8d084b32020e9cda9280
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-ssp.c
M include/hw/arm/aspeed_coprocessor.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR
Rename the AST27x0 SSP type from TYPE_ASPEED27X0SSP_SOC to
TYPE_ASPEED27X0SSP_COPROCESSOR to better reflect its role as a coprocessor
rather than a standalone SoC. This aligns naming conventions with the
coprocessor-based design introduced in earlier refactors.
This change improves naming consistency across SSP and TSP coprocessor
implementations and clarifies their relationship to the unified
Aspeed27x0CoprocessorState.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a6366527e35ad3125fc9fcf7f7d88b19e221b695
https://github.com/qemu/qemu/commit/a6366527e35ad3125fc9fcf7f7d88b19e221b695
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-tsp.c
M include/hw/arm/aspeed_coprocessor.h
Log Message:
-----------
hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR
Rename the AST27x0 TSP type from TYPE_ASPEED27X0TSP_SOC to
TYPE_ASPEED27X0TSP_COPROCESSOR to align with the naming convention used
for the SSP coprocessor (TYPE_ASPEED27X0SSP_COPROCESSOR).
This change clarifies that TSP is implemented as a coprocessor rather than
a full SoC.
This ensures consistent terminology between SSP and TSP components and
improves clarity within the coprocessor subsystem code.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 0cf9761b0ae6dd04815b54eb785301f35015246d
https://github.com/qemu/qemu/commit/0cf9761b0ae6dd04815b54eb785301f35015246d
Author: Jamin Lin <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
Log Message:
-----------
hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style
Fix coding style warnings in aspeed_ast27x0-ssp.c and aspeed_ast27x0-tsp.c
reported by checkpatch.pl regarding line length exceeding 80 characters.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 6a9d1ccd39bf0305c94691ce0ca228599d4719f3
https://github.com/qemu/qemu/commit/6a9d1ccd39bf0305c94691ce0ca228599d4719f3
Author: Markus Armbruster <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/display/xenfb.c
Log Message:
-----------
hw/display/xenfb: Replace unreachable code by g_assert_not_reached()
xenfb_mouse_event() has a switch statement whose controlling
expression move->axis is an enum InputAxis. The enum values are
INPUT_AXIS_X and INPUT_AXIS_Y, encoded as 0 and 1. The switch has a
case for both axes. In addition, it has an unreachable default label.
This convinces Coverity that move->axis can be greater than 1. It
duly reports a buffer overrun when it is used to subscript an array
with two elements.
Replace the unreachable code by g_assert_not_reached().
Resolves: Coverity CID 1613906
Signed-off-by: Markus Armbruster <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
[PMD: s/abort/g_assert_not_reached/]
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 9df035ecf735a41a0dd7686bf1d81e1b2f30eff8
https://github.com/qemu/qemu/commit/9df035ecf735a41a0dd7686bf1d81e1b2f30eff8
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/ppc/ppce500_spin.c
Log Message:
-----------
hw/ppc: Do not open-code cpu_resume() in spin_kick()
In order to make the code easier to follow / review,
use the cpu_resume() helper instead of open-coding it.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 18727804c06575e6a69566c593e79bfa4a197adb
https://github.com/qemu/qemu/commit/18727804c06575e6a69566c593e79bfa4a197adb
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/xtensa/xtfpga.c
Log Message:
-----------
hw/xtensa/xtfpga: Have xtfpga_init() only initialize MMU
cpu_reset() should not be used with an unrealized CPU.
Here we simply want to initialize the MMU, not the CPU,
so just call reset_mmu().
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Max Filippov <[email protected]>
Message-Id: <[email protected]>
Commit: 525e1c9908704377007e1cef2bbc4e2bef7e5197
https://github.com/qemu/qemu/commit/525e1c9908704377007e1cef2bbc4e2bef7e5197
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/sparc/leon3.c
Log Message:
-----------
hw/sparc/leon3: Remove unnecessary CPU() QOM cast
env_cpu() already returns a CPUState type, no need to cast.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Clément Chigot <[email protected]>
Message-Id: <[email protected]>
Commit: 1b2a50cc003962f42ce0bc91fbd4b8b380036ac2
https://github.com/qemu/qemu/commit/1b2a50cc003962f42ce0bc91fbd4b8b380036ac2
Author: Luc Michel <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/net/can/xlnx-versal-canfd.c
Log Message:
-----------
hw/net/can/xlnx-versal-canfd: remove unused include directives
Drop unecessary include directives in xlnx-versal-canfd.c.
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Francisco Iglesias <[email protected]>
Reviewed-by: Edgar E. Iglesias <[email protected]>
Signed-off-by: Luc Michel <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: fc08d5f699c53ad46a3d8b8e5159e3ab6a1124ed
https://github.com/qemu/qemu/commit/fc08d5f699c53ad46a3d8b8e5159e3ab6a1124ed
Author: Cédric Le Goater <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/arm/aspeed.c
Log Message:
-----------
hw/arm/aspeed: Don't set 'auto_create_sdcard'
The Aspeed machines inherited from a 'no_sdcard' attribute when first
introduced in QEMU. This attribute was later renamed to
'auto_create_sdcard' by commit cdc8d7cadaac ("hw/boards: Rename
no_sdcard -> auto_create_sdcard") and set to 'true'. This has the
indesirable efect to automatically create SD cards at init time.
Remove 'auto_create_sdcard' to avoid creating a SD card device.
Cc: Philippe Mathieu-Daudé <[email protected]>
Signed-off-by: Cédric Le Goater <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: d39ac36fe298400eac7e9272c950bedca29490c0
https://github.com/qemu/qemu/commit/d39ac36fe298400eac7e9272c950bedca29490c0
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/s390x/sclp.c
Log Message:
-----------
hw/s390x/sclp: Do not ignore address_space_read/write() errors
If address_space_read() fails, return PGM_ADDRESSING. In the
unlikely case address_space_write() fails (we already checked
the address is readable), return PGM_PROTECTION.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Reviewed-by: Jason J. Herne <[email protected]>
Message-Id: <[email protected]>
Commit: fe5d03c4a3ec7edfe0a9bf4d232b04aca4d72fc9
https://github.com/qemu/qemu/commit/fe5d03c4a3ec7edfe0a9bf4d232b04aca4d72fc9
Author: Mohamed Mediouni <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/vmapple/vmapple.c
Log Message:
-----------
hw/vmapple: include missing headers
Disablement by default led to:
../hw/vmapple/vmapple.c:276:39: error: use of undeclared identifier
'GTIMER_VIRT'
276 | qdev_connect_gpio_out(cpudev, GTIMER_VIRT,
| ^
../hw/vmapple/vmapple.c:479:54: error: use of undeclared identifier
'QEMU_PSCI_CONDUIT_HVC'
479 | object_property_set_int(cpu, "psci-conduit",
QEMU_PSCI_CONDUIT_HVC,
| ^
../hw/vmapple/vmapple.c:556:13: error: call to undeclared function
'arm_build_mp_affinity'; ISO C99 and later do not support implicit function
declarations [-Wimplicit-function-declaration]
556 | arm_build_mp_affinity(n, GICV3_TARGETLIST_BITS);
| ^
3 errors generated.
pretty quickly.
Signed-off-by: Mohamed Mediouni <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Tested-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Commit: faf1fae7645303180b1404716cb2e9d740f0eb2e
https://github.com/qemu/qemu/commit/faf1fae7645303180b1404716cb2e9d740f0eb2e
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/loongarch/boot.c
Log Message:
-----------
hw/loongarch/boot: Remove unnecessary cast to target_ulong
Reduce initrd_size scope. It is already of signed type (ssize_t),
no need to cast to unsigned for the comparison.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: b73cf656b7222971de75172ee6e037c98f05bec4
https://github.com/qemu/qemu/commit/b73cf656b7222971de75172ee6e037c98f05bec4
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Convert type_init() -> DEFINE_TYPES()
Prefer DEFINE_TYPES() macro over type_init() to register
multiple QOM types.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 9ccf5f38114d397802452cdf2e794fa26ed457f2
https://github.com/qemu/qemu/commit/9ccf5f38114d397802452cdf2e794fa26ed457f2
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Factor QOM HPPA_COMMON_MACHINE out
B160L and C3700 share a lot of common code. Factor it out
as an abstract HPPA_COMMON_MACHINE QOM parent.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 9fedc11ff127636900cc7a0a3e7214e5cb60a313
https://github.com/qemu/qemu/commit/9fedc11ff127636900cc7a0a3e7214e5cb60a313
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-13 (Mon, 13 Oct 2025)
Changed paths:
M hw/hppa/machine.c
Log Message:
-----------
hw/hppa: Reduce variables scope in common_init()
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Message-Id: <[email protected]>
Commit: 194dfadd6625504438107e3e740cd9dde158b335
https://github.com/qemu/qemu/commit/194dfadd6625504438107e3e740cd9dde158b335
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/qemu-macros/src/lib.rs
Log Message:
-----------
rust: bits: disable double_parens check
It is showing in the output of the bits! macro when using the nightly
toolchain, though it's not clear if it is intentional or a bug.
Shut it up for now.
Link: https://github.com/rust-lang/rust-clippy/issues/15852
Reported-by: Richard Henderson <[email protected]>
Suggested-by: Manos Pitsidianakis <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: ceda1563d6d347647419f61508856e5236069e02
https://github.com/qemu/qemu/commit/ceda1563d6d347647419f61508856e5236069e02
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: hide more warnings from call_func_with_field!
The call_func_with_field! macro uses dead code willingly to infer
the appropriate type. This has started adding a new warning:
error: unused variable: `value__`
79 | break phantom__(&{ let value__: $typ; value__.$($field).+ })
So shut it up together with the existing unreachable_code warning.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 414ac7e057047706914232142d7a7d38440b3f9b
https://github.com/qemu/qemu/commit/414ac7e057047706914232142d7a7d38440b3f9b
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/hw/timer/hpet/src/fw_cfg.rs
Log Message:
-----------
rust: hpet: fix fw_cfg handling
HPET ids for fw_cfg are not assigned correctly, because there
is a read but no write. This is caught by nightly Rust as
an unused-assignments warning, so fix it.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: c79a35acadee784610aed40134a12738381b4fba
https://github.com/qemu/qemu/commit/c79a35acadee784610aed40134a12738381b4fba
Author: Babu Moger <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add TSA attack variants TSA-SQ and TSA-L1
Transient Scheduler Attacks (TSA) are new speculative side channel attacks
related to the execution timing of instructions under specific
microarchitectural conditions. In some cases, an attacker may be able to
use this timing information to infer data from other contexts, resulting in
information leakage.
AMD has identified two sub-variants two variants of TSA.
CPUID Fn8000_0021 ECX[1] (TSA_SQ_NO).
If this bit is 1, the CPU is not vulnerable to TSA-SQ.
CPUID Fn8000_0021 ECX[2] (TSA_L1_NO).
If this bit is 1, the CPU is not vulnerable to TSA-L1.
Add the new feature word FEAT_8000_0021_ECX and corresponding bits to
detect TSA variants.
Link:
https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
Co-developed-by: Borislav Petkov (AMD) <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Signed-off-by: Babu Moger <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Link:
https://lore.kernel.org/r/12881b2c03fa351316057ddc5f39c011074b4549.1752176771.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: d8ec0baf4a15082cdc4abe1de28face9a26f0dc9
https://github.com/qemu/qemu/commit/d8ec0baf4a15082cdc4abe1de28face9a26f0dc9
Author: Babu Moger <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/cpu.c
M target/i386/cpu.h
Log Message:
-----------
target/i386: Add TSA feature flag verw-clear
Transient Scheduler Attacks (TSA) are new speculative side channel attacks
related to the execution timing of instructions under specific
microarchitectural conditions. In some cases, an attacker may be able to
use this timing information to infer data from other contexts, resulting in
information leakage
CPUID Fn8000_0021 EAX[5] (VERW_CLEAR). If this bit is 1, the memory form of
the VERW instruction may be used to help mitigate TSA.
Link:
https://www.amd.com/content/dam/amd/en/documents/resources/bulletin/technical-guidance-for-mitigating-transient-scheduler-attacks.pdf
Co-developed-by: Borislav Petkov (AMD) <[email protected]>
Signed-off-by: Borislav Petkov (AMD) <[email protected]>
Signed-off-by: Babu Moger <[email protected]>
Reviewed-by: Xiaoyao Li <[email protected]>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Link:
https://lore.kernel.org/r/e6362672e3a67a9df661a8f46598335a1a2d2754.1752176771.git.babu.mo...@amd.com
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: df9a3372ddebfcfc135861fa2d53cef6f98065f9
https://github.com/qemu/qemu/commit/df9a3372ddebfcfc135861fa2d53cef6f98065f9
Author: Mathias Krause <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/tcg/system/excp_helper.c
Log Message:
-----------
target/i386: Fix CR2 handling for non-canonical addresses
Commit 3563362ddfae ("target/i386: Introduce structures for mmu_translate")
accidentally modified CR2 for non-canonical address exceptions while these
should lead to a #GP / #SS instead -- without changing CR2.
Fix that.
A KUT test for this was submitted as [1].
[1] https://lore.kernel.org/kvm/[email protected]/
Fixes: 3563362ddfae ("target/i386: Introduce structures for mmu_translate")
Signed-off-by: Mathias Krause <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 00001a22d183ce96c110690987bf9dd6a8548552
https://github.com/qemu/qemu/commit/00001a22d183ce96c110690987bf9dd6a8548552
Author: Jon Kohler <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/kvm/kvm.c
Log Message:
-----------
i386/kvm: Expose ARCH_CAP_FB_CLEAR when invulnerable to MDS
Newer Intel hardware (Sapphire Rapids and higher) sets multiple MDS
immunity bits in MSR_IA32_ARCH_CAPABILITIES but lacks the hardware-level
MSR_ARCH_CAP_FB_CLEAR (bit 17):
ARCH_CAP_MDS_NO
ARCH_CAP_TAA_NO
ARCH_CAP_PSDP_NO
ARCH_CAP_FBSDP_NO
ARCH_CAP_SBDR_SSDP_NO
This prevents VMs with fb-clear=on from migrating from older hardware
(Cascade Lake, Ice Lake) to newer hardware, limiting live migration
capabilities. Note fb-clear was first introduced in v8.1.0 [1].
Expose MSR_ARCH_CAP_FB_CLEAR for MDS-invulnerable systems to enable
seamless migration between hardware generations.
Note: There is no impact when a guest migrates to newer hardware as
the existing bit combinations already mark the host as MMIO-immune and
disable FB_CLEAR operations in the kernel (see Linux's
arch_cap_mmio_immune() and vmx_update_fb_clear_dis()). See kernel side
discussion for [2] for additional context.
[1] 22e1094ca82 ("target/i386: add support for FB_CLEAR feature")
[2]
https://patchwork.kernel.org/project/kvm/patch/[email protected]/
Cc: Pawan Gupta <[email protected]>
Suggested-by: Sean Christopherson <[email protected]>
Signed-off-by: Jon Kohler <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: df32e5c568c9cf68c15a9bbd98d0c3aff19eab63
https://github.com/qemu/qemu/commit/df32e5c568c9cf68c15a9bbd98d0c3aff19eab63
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M hw/intc/apic.c
M target/i386/helper.c
M target/i386/tcg/system/seg_helper.c
Log Message:
-----------
i386/cpu: Prevent delivering SIPI during SMM in TCG mode
[commit message by YiFei Zhu]
A malicious kernel may control the instruction pointer in SMM in a
multi-processor VM by sending a sequence of IPIs via APIC:
CPU0 CPU1
IPI(CPU1, MODE_INIT)
x86_cpu_exec_reset()
apic_init_reset()
s->wait_for_sipi = true
IPI(CPU1, MODE_SMI)
do_smm_enter()
env->hflags |= HF_SMM_MASK;
IPI(CPU1, MODE_STARTUP, vector)
do_cpu_sipi()
apic_sipi()
/* s->wait_for_sipi check passes */
cpu_x86_load_seg_cache_sipi(vector)
A different sequence, SMI INIT SIPI, is also buggy in TCG because
INIT is not blocked or latched during SMM. However, it is not
vulnerable to an instruction pointer control in the same way because
x86_cpu_exec_reset clears env->hflags, exiting SMM.
Fixes: a9bad65d2c1f ("target-i386: wake up processors that receive an SMI")
Analyzed-by: YiFei Zhu <[email protected]>
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: cdba90ac1b0ac789b10c0b5f6ef7e9558237ec66
https://github.com/qemu/qemu/commit/cdba90ac1b0ac789b10c0b5f6ef7e9558237ec66
Author: YiFei Zhu <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/tcg/system/smm_helper.c
Log Message:
-----------
i386/tcg/smm_helper: Properly apply DR values on SMM entry / exit
do_smm_enter and helper_rsm sets the env->dr, but does not sync the
values with cpu_x86_update_dr7. A malicious kernel may control the
instruction pointer in SMM by setting a breakpoint on the SMI
entry point, and after do_smm_enter cpu->breakpoints contains the
stale breakpoint; and because IDT is not reloaded upon SMI entry,
the debug exception handler controlled by the malicious kernel
is invoked.
Fixes: 01df040b5247 ("x86: Debug register emulation (Jan Kiszka)")
Reported-by: [email protected]
Signed-off-by: YiFei Zhu <[email protected]>
Link:
https://lore.kernel.org/r/2bacb9b24e9d337dbe48791aa25d349eb9c52c3a.1758794468.git.zhuyi...@google.com
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5a2faa0a0a2cbdad4a108a0e122b0e51b9bc94fd
https://github.com/qemu/qemu/commit/5a2faa0a0a2cbdad4a108a0e122b0e51b9bc94fd
Author: Thomas Ogrisegg <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/tcg/decode-new.c.inc
Log Message:
-----------
target/i386: fix x86_64 pushw op
For x86_64 a 16 bit push op (pushw) of a memory address would generate
a 64 bit store on the stack instead of a 16 bit store.
For example:
pushw (%rax)
behaves like
pushq (%rax)
which is incorrect.
This patch fixes that.
Signed-off-by: Thomas Ogrisegg <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0d22b621b7969eefde3535a0805977a334936fd7
https://github.com/qemu/qemu/commit/0d22b621b7969eefde3535a0805977a334936fd7
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/tcg/seg_helper.c
Log Message:
-----------
target/i386: fix access to the T bit of the TSS
The T bit is bit 0 of the 16-bit word at offset 100 of the TSS. However,
accessing it with a 32-bit word is not really correct, because bytes
102-103 contain the I/O map base address (relative to the base of the
TSS) and bits 1-15 are reserved. In particular, any task switch to a TSS that
has a nonzero I/O map base address is broken.
This fixes the eventinj and taskswitch tests in kvm-unit-tests.
Cc: [email protected]
Fixes: ad441b8b791 ("target/i386: implement TSS trap bit", 2025-05-12)
Reported-by: Thomas Huth <[email protected]>
Closes: https://gitlab.com/qemu-project/qemu/-/issues/3101
Tested-by: Thomas Huth <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5142397c79330aab9bef3230991c8ac0c251110f
https://github.com/qemu/qemu/commit/5142397c79330aab9bef3230991c8ac0c251110f
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M util/async.c
Log Message:
-----------
async: access bottom half flags with qatomic_read
Running test-aio-multithread under TSAN reveals data races on bh->flags.
Because bottom halves may be scheduled or canceled asynchronously,
without taking a lock, adjust aio_compute_bh_timeout() and aio_ctx_check()
to use a relaxed read to access the flags.
Use an acquire load to ensure that anything that was written prior to
qemu_bh_schedule() is visible.
Closes: https://gitlab.com/qemu-project/qemu/-/issues/2749
Closes: https://gitlab.com/qemu-project/qemu/-/issues/851
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 58aa1d08bbc406ba3982f32ffb1bef0ff4f8f369
https://github.com/qemu/qemu/commit/58aa1d08bbc406ba3982f32ffb1bef0ff4f8f369
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M target/i386/cpu.c
Log Message:
-----------
target/i386: user: do not set up a valid LDT on reset
In user-mode emulation, QEMU uses the default setting of the LDT base
and limit, which places it at the bottom 64K of virtual address space.
However, by default there is no LDT at all in Linux processes, and
therefore the limit should be 0.
This is visible as a NULL pointer dereference in LSL and LAR instructions
when they try to read the LDT at an unmapped address.
Resolves: #1376
Cc: [email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 2808652b4fae100dd1a46344c686db6e6136784e
https://github.com/qemu/qemu/commit/2808652b4fae100dd1a46344c686db6e6136784e
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M hmp-commands-info.hx
Log Message:
-----------
monitor: clarify "info accel" help message
In preparation for adding "info accelerators", explain that this command
is about runtime statistics.
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 71d5babbd6fffc7def1ecbf29f9753e3a2807761
https://github.com/qemu/qemu/commit/71d5babbd6fffc7def1ecbf29f9753e3a2807761
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M hmp-commands-info.hx
M hw/core/machine-hmp-cmds.c
M hw/core/machine-qmp-cmds.c
M include/monitor/hmp.h
M qapi/accelerator.json
Log Message:
-----------
monitor: generalize query-mshv/"info mshv" to query-accelerators/"info
accelerators"
The recently-introduced query-mshv command is a duplicate of query-kvm,
and neither provides a full view of which accelerators are supported
by a particular binary of QEMU and which is in use.
KVM was the first accelerator added to QEMU, predating QOM and TYPE_ACCEL,
so it got a pass. But now, instead of adding a badly designed copy, solve
the problem completely for all accelerators with a command that provides
the whole picture:
>> {"execute": "query-accelerators"}
<< {"return": {"enabled": "tcg", "present": ["kvm", "mshv", "qtest", "tcg",
"xen"]}}
Cc: Praveen K Paladugu <[email protected]>
Cc: Magnus Kulke <[email protected]>
Suggested-by: Markus Armbruster <[email protected]>
Reviewed-by: Daniel P. Berrangé <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 665a8035b7e65f5dcb5cdacb3a31c9087cff8684
https://github.com/qemu/qemu/commit/665a8035b7e65f5dcb5cdacb3a31c9087cff8684
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M include/system/kvm.h
M target/arm/kvm.c
M target/i386/kvm/kvm.c
M target/loongarch/kvm/kvm.c
M target/mips/kvm.c
M target/ppc/kvm.c
M target/riscv/kvm/kvm-cpu.c
M target/s390x/kvm/kvm.c
Log Message:
-----------
accel/kvm: Introduce KvmPutState enum
Join the 3 KVM_PUT_*_STATE definitions in a single enum.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Harsh Prateek Bora <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 0de36ecb2b0e21a4bf610c2934b250a577490c38
https://github.com/qemu/qemu/commit/0de36ecb2b0e21a4bf610c2934b250a577490c38
Author: Philippe Mathieu-Daudé <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M accel/kvm/kvm-all.c
Log Message:
-----------
accel/kvm: Factor kvm_cpu_synchronize_put() out
The same code is duplicated 3 times: factor a common method.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Richard Henderson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 818231bc6d24859fde179d1ab022bd932f409d10
https://github.com/qemu/qemu/commit/818231bc6d24859fde179d1ab022bd932f409d10
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/bql/src/cell.rs
Log Message:
-----------
rust: bql: add BqlRefCell::get_mut()
This method is rarely useful in QEMU due to the pervasiveness of
shared references, but add it for when a &mut BqlRefCell<> is used.
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5c776a767703f9f6cd6ee87752e794d2cbab1165
https://github.com/qemu/qemu/commit/5c776a767703f9f6cd6ee87752e794d2cbab1165
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: do not pass raw pointer to VMStateDescription::fields
Pass a slice instead; a function that accepts a raw pointer should
arguably be declared as unsafe.
But since it is now much easier to forget vmstate_fields!, validate the
value (at least to some extent) before passing it to C. (Unfortunately,
doing the same for subsections would require const ptr::is_null(), which
is only stable in Rust 1.84).
Suggested-by: Zhao Liu <[email protected]>
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 64bce66d6f142272415de5807f38c2b8a884c4c2
https://github.com/qemu/qemu/commit/64bce66d6f142272415de5807f38c2b8a884c4c2
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: do not store raw pointers into VMStateSubsectionsWrapper
Raw pointers were used to insert a NULL one at the end of the array.
However, Option<&...> has the same layout and does not remove Sync
from the type of the array.
As an extra benefit, this enables validation of the terminator of the
subsection array, because is_null() in const context would not be stable
until Rust 1.84.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 5b4fa9780728ba526f0529199ef90d6132a3faf2
https://github.com/qemu/qemu/commit/5b4fa9780728ba526f0529199ef90d6132a3faf2
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: validate termination of subsection arrays
For consistency with fields(), validate the value (at least to some extent)
before passing it to C.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 8999ca00a4b69b0b7332bf3ae2fc17d473923793
https://github.com/qemu/qemu/commit/8999ca00a4b69b0b7332bf3ae2fc17d473923793
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: extract vmstate_fields_ref
This is useful when building a VMState for generic structs, because you have
to avoid nested statics. Using vmstate_fields! will fail in the likely case
where the _FIELDS static uses Self from an outer item, because that is
forbidden.
The separate macros are needed because you cannot just do
.fields(vmstate_fields_ref! {
vmstate_of!(PL011State, clock),
})
The value returned by vmstate_fields_ref! is not promoted to static, which is
unfortunate but intentional (https://github.com/rust-lang/rust/issues/60502):
error[E0716]: temporary value dropped while borrowed
--> rust/hw/char/pl011/libpl011.rlib.p/structured/device.rs:743:17
|
738 | / VMStateDescriptionBuilder::<PL011State>::new()
739 | | .name(c"pl011/clock")
740 | | .version_id(1)
741 | | .minimum_version_id(1)
742 | | .needed(&PL011State::clock_needed)
743 | | .fields(vmstate_fields_ref! {
| | _________________^
744 | || vmstate_of!(PL011State, clock),
745 | || })
| ||_________^- argument requires that borrow lasts for `'static`
| |_________|
| creates a temporary value which is freed while still in use
746 | .build();
| - temporary value is freed at the end of this statement
Thus it is necessary to use the "static", whether explicitly or hidden by
vmstate_fields.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 4526418affcd536748a344bdba9a6913a5f7e135
https://github.com/qemu/qemu/commit/4526418affcd536748a344bdba9a6913a5f7e135
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/Cargo.lock
M rust/bql/Cargo.toml
M rust/bql/meson.build
M rust/bql/src/cell.rs
M rust/meson.build
M rust/migration/Cargo.toml
M rust/migration/meson.build
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: move VMState from bql to migration
The high-level wrapper Migratable<T> will contain a BqlCell,
which would introduce a circular dependency betwen the bql and
migration crates. Move the implementation of VMState for cells
to "migration", together with the implementation for std types.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 44a9d1b86c06ea955e4720ae5de8c130ff5719bc
https://github.com/qemu/qemu/commit/44a9d1b86c06ea955e4720ae5de8c130ff5719bc
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M docs/devel/rust.rst
M rust/migration/meson.build
M rust/migration/src/lib.rs
A rust/migration/src/migratable.rs
Log Message:
-----------
rust: migration: add high-level migration wrappers
Instead of dealing with pre/post callbacks, allow devices to
implement a snapshot/restore mechanism; this has two main
advantages:
- it can be easily implemented via procedural macros
- there can be generic implementations to deal with various
kinds of interior-mutable containers, from BqlRefCell to Mutex,
so that C code does not see Rust concepts such as Mutex<>.
Using it is easy; you can implement the snapshot/restore trait
ToMigrationState and declare your state like:
regs: Migratable<Mutex<MyDeviceRegisters>>
Migratable<> allows dereferencing to the underlying object with
no run-time cost.
Note that Migratable<> actually does not accept ToMigrationState,
only the similar ToMigrationStateShared trait that the user will mostly
not care about. This is required by the fact that pre/post callbacks
take a &self, and ensures that the argument is a Mutex or BqlRefCell
(including an array or Arc<> thereof).
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 29cf500e3b489021219dfdb90c2abc6f275c5775
https://github.com/qemu/qemu/commit/29cf500e3b489021219dfdb90c2abc6f275c5775
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/Cargo.lock
M rust/migration/Cargo.toml
M rust/migration/meson.build
M rust/migration/src/lib.rs
M rust/migration/src/migratable.rs
M rust/qemu-macros/src/lib.rs
A rust/qemu-macros/src/migration_state.rs
M rust/qemu-macros/src/tests.rs
Log Message:
-----------
rust: qemu-macros: add ToMigrationState derive macro
Add a macro that recursively builds the "migrated" version
of a struct.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 67913e95bf7e9fb3c9e904055d7021b243ff1674
https://github.com/qemu/qemu/commit/67913e95bf7e9fb3c9e904055d7021b243ff1674
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M include/qemu/timer.h
M util/qemu-timer.c
Log Message:
-----------
timer: constify some functions
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: 7ee5875d423598ac55a0b55881d9a1ee5c3c7daf
https://github.com/qemu/qemu/commit/7ee5875d423598ac55a0b55881d9a1ee5c3c7daf
Author: Paolo Bonzini <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M rust/migration/src/vmstate.rs
Log Message:
-----------
rust: migration: implement ToMigrationState as part of impl_vmstate_bitsized
This is most likely desirable, and is the easiest way to migrate
a bit-sized value without peeking at the innards of the bilge crate.
Reviewed-by: Zhao Liu <[email protected]>
Signed-off-by: Paolo Bonzini <[email protected]>
Commit: b905ac657b6a156c83593294c3667e47a2d775ca
https://github.com/qemu/qemu/commit/b905ac657b6a156c83593294c3667e47a2d775ca
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M docs/about/deprecated.rst
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2400.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0-ssp.c
M hw/arm/aspeed_ast27x0-tsp.c
M hw/arm/aspeed_ast27x0.c
A hw/arm/aspeed_coprocessor_common.c
M hw/arm/aspeed_soc_common.c
M hw/arm/fby35.c
M hw/arm/meson.build
A include/hw/arm/aspeed_coprocessor.h
M include/hw/arm/aspeed_soc.h
M tests/functional/aarch64/test_aspeed_ast2700.py
M tests/functional/aarch64/test_aspeed_ast2700fc.py
M tests/functional/arm/meson.build
M tests/functional/arm/test_aspeed_ast1030.py
M tests/functional/arm/test_aspeed_ast2500.py
R tests/functional/arm/test_aspeed_ast2600.py
A tests/functional/arm/test_aspeed_ast2600_buildroot.py
A tests/functional/arm/test_aspeed_ast2600_sdk.py
Log Message:
-----------
Merge tag 'pull-aspeed-20251013' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Introduce AspeedCoprocessor class and base implementation
* Remove redudant functional tests to optimize for CI resources
* Deprecate fp5280g2-bmc, qcom-dc-scm-v1-bmc, qcom-firework-bmc and
sonorapass-bmc machines
* Bump ASPEED SDK to v09.08
* Add PCIe and network tests
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# gpg: Signature made Mon 13 Oct 2025 05:43:34 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
* tag 'pull-aspeed-20251013' of https://github.com/legoater/qemu: (29 commits)
hw/arm/aspeed_ast27x0-{ssp,tsp}: Fix coding style
hw/arm/aspeed_ast27x0-tsp: Rename type to TYPE_ASPEED27X0TSP_COPROCESSOR
hw/arm/aspeed_ast27x0-ssp: Rename type to TYPE_ASPEED27X0SSP_COPROCESSOR
hw/arm/aspeed_ast27x0-tsp: Change to use Aspeed27x0CoprocessorState
hw/arm/aspeed_ast27x0-ssp: Change to use Aspeed27x0CoprocessorState
hw/arm/aspeed_ast27x0-tsp: Make AST27x0 TSP inherit from AspeedCoprocessor
instead of AspeedSoC
hw/arm/aspeed_ast27x0-ssp: Make AST27x0 SSP inherit from AspeedCoprocessor
instead of AspeedSoC
hw/arm/aspeed: Introduce AspeedCoprocessor class and base implementation
hw/arm/aspeed: Remove the aspeed_soc_get_irq and class get_irq hook
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_soc_uart_realize() API
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_mmio_map_unimplemented() API
hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_mmio_map() API
hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_soc_cpu_type() API
hw/arm/aspeed: Remove AspeedSoCState dependency from
aspeed_soc_uart_set_chr() API
hw/arm/aspeed: Remove AspeedSoCClass dependency from aspeed_uart_last() API
hw/arm/aspeed: Remove AspeedSoCState dependency from aspeed_uart_first() API
test/functional/aarch64: Split the ast2700a1-evb OpenBMC boot test
test/functional/aarch64: Remove test for the ast2700a0-evb machine
aspeed: Deprecate the fp5280g2-bmc machine
aspeed: Deprecate the qcom-dc-scm-v1-bmc and qcom-firework-bmc machines
...
Signed-off-by: Richard Henderson <[email protected]>
Commit: 2953fba3bace819b836beeffd4a84ff0653a9aed
https://github.com/qemu/qemu/commit/2953fba3bace819b836beeffd4a84ff0653a9aed
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M hw/display/xenfb.c
M hw/hppa/machine.c
M hw/loongarch/boot.c
M hw/net/can/xlnx-versal-canfd.c
M hw/ppc/ppce500_spin.c
M hw/s390x/sclp.c
M hw/sparc/leon3.c
M hw/vmapple/vmapple.c
M hw/xtensa/xtfpga.c
Log Message:
-----------
Merge tag 'hw-misc-20251013' of https://github.com/philmd/qemu into staging
Misc HW patches
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# gpg: Signature made Mon 13 Oct 2025 12:17:15 PM PDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <[email protected]>"
[unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20251013' of https://github.com/philmd/qemu:
hw/hppa: Reduce variables scope in common_init()
hw/hppa: Factor QOM HPPA_COMMON_MACHINE out
hw/hppa: Convert type_init() -> DEFINE_TYPES()
hw/loongarch/boot: Remove unnecessary cast to target_ulong
hw/vmapple: include missing headers
hw/s390x/sclp: Do not ignore address_space_read/write() errors
hw/arm/aspeed: Don't set 'auto_create_sdcard'
hw/net/can/xlnx-versal-canfd: remove unused include directives
hw/sparc/leon3: Remove unnecessary CPU() QOM cast
hw/xtensa/xtfpga: Have xtfpga_init() only initialize MMU
hw/ppc: Do not open-code cpu_resume() in spin_kick()
hw/display/xenfb: Replace unreachable code by g_assert_not_reached()
Signed-off-by: Richard Henderson <[email protected]>
Commit: b2d86f1c5429979d9ecaf43a7973cc129da1b135
https://github.com/qemu/qemu/commit/b2d86f1c5429979d9ecaf43a7973cc129da1b135
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M accel/kvm/kvm-all.c
M docs/devel/rust.rst
M hmp-commands-info.hx
M hw/core/machine-hmp-cmds.c
M hw/core/machine-qmp-cmds.c
M hw/intc/apic.c
M include/monitor/hmp.h
M include/qemu/timer.h
M include/system/kvm.h
M qapi/accelerator.json
M rust/Cargo.lock
M rust/bql/Cargo.toml
M rust/bql/meson.build
M rust/bql/src/cell.rs
M rust/hw/char/pl011/src/registers.rs
M rust/hw/timer/hpet/src/fw_cfg.rs
M rust/meson.build
M rust/migration/Cargo.toml
M rust/migration/meson.build
M rust/migration/src/lib.rs
A rust/migration/src/migratable.rs
M rust/migration/src/vmstate.rs
M rust/qemu-macros/src/lib.rs
A rust/qemu-macros/src/migration_state.rs
M rust/qemu-macros/src/tests.rs
M target/arm/kvm.c
M target/i386/cpu.c
M target/i386/cpu.h
M target/i386/helper.c
M target/i386/kvm/kvm.c
M target/i386/tcg/decode-new.c.inc
M target/i386/tcg/seg_helper.c
M target/i386/tcg/system/excp_helper.c
M target/i386/tcg/system/seg_helper.c
M target/i386/tcg/system/smm_helper.c
M target/loongarch/kvm/kvm.c
M target/mips/kvm.c
M target/ppc/kvm.c
M target/riscv/kvm/kvm-cpu.c
M target/s390x/kvm/kvm.c
M util/async.c
M util/qemu-timer.c
Log Message:
-----------
Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging
* rust: fix nightly warnings
* target/i386: a smattering of fixes
* monitor: add "info accelerators"
* kvm: cleanups to kvm_cpu_synchronize_put()
* target/i386: Add TSA attack variants and verw-clear feature flag
* async: tsan bottom half fixes
* rust: migration state wrappers with support for BQL-free devices
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# gpg: Signature made Tue 14 Oct 2025 05:44:06 AM PDT
# gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg: issuer "[email protected]"
# gpg: Good signature from "Paolo Bonzini <[email protected]>" [unknown]
# gpg: aka "Paolo Bonzini <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1
# Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83
* tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (28 commits)
rust: migration: implement ToMigrationState as part of impl_vmstate_bitsized
timer: constify some functions
rust: qemu-macros: add ToMigrationState derive macro
rust: migration: add high-level migration wrappers
rust: move VMState from bql to migration
rust: migration: extract vmstate_fields_ref
rust: migration: validate termination of subsection arrays
rust: migration: do not store raw pointers into VMStateSubsectionsWrapper
rust: migration: do not pass raw pointer to VMStateDescription::fields
rust: bql: add BqlRefCell::get_mut()
accel/kvm: Factor kvm_cpu_synchronize_put() out
accel/kvm: Introduce KvmPutState enum
monitor: generalize query-mshv/"info mshv" to query-accelerators/"info
accelerators"
monitor: clarify "info accel" help message
target/i386: user: do not set up a valid LDT on reset
async: access bottom half flags with qatomic_read
target/i386: fix access to the T bit of the TSS
target/i386: fix x86_64 pushw op
i386/tcg/smm_helper: Properly apply DR values on SMM entry / exit
i386/cpu: Prevent delivering SIPI during SMM in TCG mode
...
Signed-off-by: Richard Henderson <[email protected]>
Commit: f55fc1c0929d0ecdaad089f40e087f2c81ed6614
https://github.com/qemu/qemu/commit/f55fc1c0929d0ecdaad089f40e087f2c81ed6614
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M accel/tcg/user-exec.c
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M include/exec/page-protection.h
M include/user/page-protection.h
M linux-user/arm/elfload.c
M linux-user/hppa/elfload.c
M linux-user/mmap.c
M linux-user/x86_64/elfload.c
M target/arm/cpu.h
Log Message:
-----------
accel/tcg: Add clear_flags argument to page_set_flags
Expand the interface of page_set_flags to separate the
set of flags to be set and the set of flags to be cleared.
This allows us to replace PAGE_RESET with the PAGE_VALID
bit within clear_flags.
Replace PAGE_TARGET_STICKY with TARGET_PAGE_NOTSTICKY;
aarch64-linux-user is the only user.
Signed-off-by: Richard Henderson <[email protected]>
Commit: a79fbb6988f6aad36a64ef9fd1a5fc226a8e4130
https://github.com/qemu/qemu/commit/a79fbb6988f6aad36a64ef9fd1a5fc226a8e4130
Author: Jon Wilson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M include/exec/page-protection.h
M linux-user/elfload.c
M linux-user/mmap.c
Log Message:
-----------
linux-user: Support MADV_DONTDUMP, MADV_DODUMP
Set and clear PAGE_DONTDUMP, and honor that in vma_dump_size.
Signed-off-by: Jon Wilson <[email protected]>
[rth: Use new page_set_flags semantics; also handle DODUMP]
Signed-off-by: Richard Henderson <[email protected]>
Commit: ec03dd9723781c7e9d4b4f70c7f54d12da9459d5
https://github.com/qemu/qemu/commit/ec03dd9723781c7e9d4b4f70c7f54d12da9459d5
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M accel/tcg/cputlb.c
Log Message:
-----------
accel/tcg: Hoist first page lookup above pointer_wrap
For strict alignment targets we registered cpu_pointer_wrap_notreached,
but generic code used it before recognizing the alignment exception.
Hoist the first page lookup, so that the alignment exception happens first.
Cc: [email protected]
Buglink: https://bugs.debian.org/1112285
Fixes: a4027ed7d4be ("target: Use cpu_pointer_wrap_notreached for strict align
targets")
Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Commit: 3bf5c57a11827d9fa706524d57ee3e5af68a429e
https://github.com/qemu/qemu/commit/3bf5c57a11827d9fa706524d57ee3e5af68a429e
Author: Richard Henderson <[email protected]>
Date: 2025-10-14 (Tue, 14 Oct 2025)
Changed paths:
M accel/tcg/cputlb.c
M accel/tcg/user-exec.c
M bsd-user/bsd-mem.h
M bsd-user/mmap.c
M include/exec/page-protection.h
M include/user/page-protection.h
M linux-user/arm/elfload.c
M linux-user/elfload.c
M linux-user/hppa/elfload.c
M linux-user/mmap.c
M linux-user/x86_64/elfload.c
M target/arm/cpu.h
Log Message:
-----------
Merge tag 'pull-tcg-20251014' of https://gitlab.com/rth7680/qemu into staging
linux-user: Support MADV_DONTDUMP, MADV_DODUMP
accel/tcg: Hoist first page lookup above pointer_wrap
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# gpg: Signature made Tue 14 Oct 2025 10:22:30 AM PDT
# gpg: using RSA key 7A481E78868B4DB6A85A05C064DF38E8AF7E215F
# gpg: issuer "[email protected]"
# gpg: Good signature from "Richard Henderson <[email protected]>"
[ultimate]
* tag 'pull-tcg-20251014' of https://gitlab.com/rth7680/qemu:
accel/tcg: Hoist first page lookup above pointer_wrap
linux-user: Support MADV_DONTDUMP, MADV_DODUMP
accel/tcg: Add clear_flags argument to page_set_flags
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/f3f2ad119347...3bf5c57a1182
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