Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: 688a3dae7828ca5ee6f45d510eed083420d72d8a
https://github.com/qemu/qemu/commit/688a3dae7828ca5ee6f45d510eed083420d72d8a
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
A hw/nvram/aspeed_otp.c
M hw/nvram/meson.build
A include/hw/nvram/aspeed_otp.h
Log Message:
-----------
hw/nvram/aspeed_otp: Add ASPEED OTP memory device model
Introduce a QEMU device model for ASPEED's One-Time Programmable (OTP)
memory.
This model simulates a word-addressable OTP region used for secure
fuse storage. The OTP memory can operate with an internal memory
buffer.
The OTP model provides a memory-like interface through a dedicated
AddressSpace, allowing other device models (e.g., SBC) to issue
transactions as if accessing a memory-mapped region.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9f58dd0a8c30a6b84016db30949fe2f86f8bc38b
https://github.com/qemu/qemu/commit/9f58dd0a8c30a6b84016db30949fe2f86f8bc38b
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/misc/aspeed_sbc.c
M hw/misc/trace-events
M include/hw/misc/aspeed_sbc.h
Log Message:
-----------
hw/misc/aspeed_sbc: Connect ASPEED OTP memory device to SBC
This patch connects the aspeed.otp device to the ASPEED Secure Boot
Controller (SBC) model. It implements OTP memory access via the SBC's
command interface and enables emulation of secure fuse programming
flows.
The following OTP commands are supported:
- READ: reads a 32-bit word from OTP memory into internal registers
- PROG: programs a 32-bit word value to the specified OTP address
Trace events are added to observe read/program operations and command
handling flow.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: fe4159cb34f36a63a1759b907f51f8d458f5c940
https://github.com/qemu/qemu/commit/fe4159cb34f36a63a1759b907f51f8d458f5c940
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast2600.c
M hw/misc/aspeed_sbc.c
Log Message:
-----------
hw/arm: Integrate ASPEED OTP memory support into AST2600 SoCs
The has_otp attribute is enabled in the SBC subclasses for AST2600 to
control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: c6b4279a9240a838632e2d689a138da96545c540
https://github.com/qemu/qemu/commit/c6b4279a9240a838632e2d689a138da96545c540
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/nvram/aspeed_otp.c
Log Message:
-----------
hw/nvram/aspeed_otp: Add 'drive' property to support block backend
This patch introduces a 'drive' property to the Aspeed OTP device,
allowing it to be backed by a block device. Users can now preload
OTP data via QEMU CLI using a block backend.
Example usage:
./qemu-system-arm \
-blockdev driver=file,filename=otpmem.img,node-name=otp \
-global aspeed-otp.drive=otp \
...
If the drive is provided, its content will be loaded as the initial OTP
state. Otherwise, an internal memory buffer will be used.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8970c95c4db99dd44ff463acc14c69510776cdee
https://github.com/qemu/qemu/commit/8970c95c4db99dd44ff463acc14c69510776cdee
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/nvram/aspeed_otp.c
M hw/nvram/trace-events
Log Message:
-----------
hw/nvram/aspeed_otp: Add OTP programming semantics and tracing
Implement correct OTP programming behavior for Aspeed OTP:
- Support read-modify-write flow with one-way bit programming:
* prog_bit uses 0s as the "to-be-programmed" mask.
* Even-indexed words: 0->1, odd-indexed words: 1->0.
* Reject non-programmable requests and log conflicts.
- Enable unaligned accesses in MemoryRegionOps.
Since each OTP address maps to a 1DW (4B) or 2DW (8B) block in the
backing store, upper-layer accesses may be unaligned to block
boundaries.
This matches the irreversible, word-parity-dependent programming rules
of Aspeed SoCs and exposes changes via QEMU trace events.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
[ clg: Fixed PRIx64 format in aspeed_otp_write() ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: fdad6ec30dfb87df0980887a4c22e55ccf65f9c3
https://github.com/qemu/qemu/commit/fdad6ec30dfb87df0980887a4c22e55ccf65f9c3
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast10x0.c
M hw/misc/aspeed_sbc.c
M include/hw/misc/aspeed_sbc.h
Log Message:
-----------
hw/arm: Integrate ASPEED OTP memory support into AST1030 SoCs
The has_otp attribute is enabled in the SBC subclasses for AST1030 to
control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 02cebef5a140a0008a8bb0d3db6e33a4e7e4a9d2
https://github.com/qemu/qemu/commit/02cebef5a140a0008a8bb0d3db6e33a4e7e4a9d2
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/misc/aspeed_sbc.c
Log Message:
-----------
hw/misc/aspeed_sbc: Add CAMP2 support for OTP data reads
The OTP space contains three types of entries: data, conf, and strap.
Data entries consist of two DWORDs, while the other types contain
only one DWORD. This change adds the R_CAMP2 register (0x024 / 4) to
store the second DWORD when reading from the OTP data region.
With this enhancement, OTP reads now correctly return both DWORDs for
data entries via the CAMP registers, along with improved address
validation and error handling.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 61dcc2c2db0236fde878d053028c39fe27dc8f36
https://github.com/qemu/qemu/commit/61dcc2c2db0236fde878d053028c39fe27dc8f36
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/misc/aspeed_sbc.c
M hw/misc/trace-events
Log Message:
-----------
hw/misc/aspeed_sbc: Handle OTP write command for voltage mode registers
Extend OTP command handling to recognize specific voltage mode register
addresses and emulate the expected hardware behavior. Without this
change, legitimate voltage mode change requests would be incorrectly
reported as "Unknown command" and logged as an error.
This implementation does not perform actual mode changes, but ensures
that valid requests are accepted and ignored as per hardware behavior.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ea82822b7962df7846fc71a387e0c44867a66e39
https://github.com/qemu/qemu/commit/ea82822b7962df7846fc71a387e0c44867a66e39
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M docs/system/arm/aspeed.rst
Log Message:
-----------
docs/system/arm/aspeed: Document OTP memory options
Add documentation for the OTP memory module used by AST2600 and AST1030
SoCs, and describe options for using a pre-generated image or an
internal buffer. Include example commands for configuration and image
generation.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: b28103bb52161e2d240be3e03bf0e8680cb873c9
https://github.com/qemu/qemu/commit/b28103bb52161e2d240be3e03bf0e8680cb873c9
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed.c
M tests/functional/aarch64/test_aspeed_ast2700.py
Log Message:
-----------
hw/arm/aspeed Move ast2700-evb alias to ast2700a1-evb
This patch moves the "ast2700-evb" alias from the A0 to A1.
The A0 machine remains available via its explicit name
("ast2700a0-evb"), while functional tests are updated to
target A0 by name instead of relying on the generic alias.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 54623e94623cd75aec87ebd1e49b538033676c3f
https://github.com/qemu/qemu/commit/54623e94623cd75aec87ebd1e49b538033676c3f
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M tests/functional/aspeed.py
Log Message:
-----------
tests/functional/arm: Add helper to generate OTP images
Add a small helper that generates OTP images at test time. This lets
multiple test cases create default OTP contents without shipping prebuilt
fixtures and keeps the tests self-contained.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: fb89ceac92012d154f1113190e24e45a42f396fc
https://github.com/qemu/qemu/commit/fb89ceac92012d154f1113190e24e45a42f396fc
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast1030.py
Log Message:
-----------
tests/functional/arm: Add AST1030 boot test with generated OTP image
Add a functional test that boots an AST1030 machine with a generated
OTP image. The test verifies that OTP contents are read during early
boot and that the system reaches the expected console prompt.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2057685f0b02f06ae2aec0627489421f06bc7796
https://github.com/qemu/qemu/commit/2057685f0b02f06ae2aec0627489421f06bc7796
Author: Kane-Chen-AS <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast2600.py
Log Message:
-----------
tests/functional/arm: Add AST2600 boot test with generated OTP image
Add a functional test that boots an AST2600 machine with a generated
OTP image. The test verifies that OTP contents are read during early
boot and that the system reaches the expected console prompt.
Signed-off-by: Kane-Chen-AS <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
[ clg: checkpath fixes ]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 42dd3c4f7dbceb6ea374b3fbe104781f68008e1f
https://github.com/qemu/qemu/commit/42dd3c4f7dbceb6ea374b3fbe104781f68008e1f
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M include/hw/pci/pci_ids.h
Log Message:
-----------
hw/pci/pci_ids: Add PCI vendor ID for ASPEED
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 303e8dc29ffe6dc2417a0240cea604f18371ea12
https://github.com/qemu/qemu/commit/303e8dc29ffe6dc2417a0240cea604f18371ea12
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/Kconfig
M hw/pci-host/Kconfig
A hw/pci-host/aspeed_pcie.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
A include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
This patch introduces an initial ASPEED PCIe PHY/host controller model to
support the AST2600 SoC. It provides a simple register block with MMIO
read/write callbacks, integration into the build system, and trace events
for debugging.
Key changes:
1. PCIe PHY MMIO read/write callbacks
Implemented aspeed_pcie_phy_read() and aspeed_pcie_phy_write() to
handle 32-bit register accesses.
2. Build system and Kconfig integration
Added CONFIG_PCI_EXPRESS_ASPEED in hw/pci-host/Kconfig and meson
rules.
Updated ASPEED_SOC in hw/arm/Kconfig to imply PCI_DEVICES and select
PCI_EXPRESS_ASPEED.
3. Trace events for debug
New tracepoints aspeed_pcie_phy_read and aspeed_pcie_phy_write allow
monitoring MMIO accesses.
4. Register space and defaults (AST2600 reference)
Expose a 0x100 register space, as documented in the AST2600 datasheet.
On reset, set default values:
PEHR_ID: Vendor ID = ASPEED, Device ID = 0x1150
PEHR_CLASS_CODE = 0x06040006
PEHR_DATALINK = 0xD7040022
PEHR_LINK: bit[5] set to 1 to indicate link up.
This provides a skeleton device for the AST2600 platform. It enables
firmware to detect the PCIe link as up by default and allows future
extension.
This commit is the starting point of the series to introduce ASPEED PCIe
Root Complex (RC) support. Based on previous work from Cédric Le Goater,
the following commits in this series extend and refine the implementation:
- Add a PCIe Root Port so that devices can be attached without requiring an
extra bridge.
- Restrict the Root Port device instantiation to the AST2600 platform.
- Integrate aspeed_cfg_translate_write() to support both AST2600 and AST2700.
- Add MSI support and a preliminary RC IOMMU address space.
- Fix issues with MSI interrupt clearing.
- Extend support to the AST2700 SoC.
- Drop the AST2600 RC_L support.
- Introduce PCIe RC functional tests covering both AST2600 and AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f002aa35f3205d55bbe4a68670ba19a6dcf1d6a8
https://github.com/qemu/qemu/commit/f002aa35f3205d55bbe4a68670ba19a6dcf1d6a8
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M hw/pci-host/trace-events
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller
with a 0x100 byte register space. The register layout is shared between
two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0xc0–0xff
for RC_H. Only RC_H is modeled in this implementation.
The RC_H bus uses bus numbers in the 0x80–0xff range instead of the
standard root bus 0x00. To allow the PCI subsystem to discover devices,
the host bridge logic remaps the root bus number back to 0x00 whenever the
configured bus number matches the "bus-nr" property.
New MMIO callbacks are added for the H2X config space:
- aspeed_pcie_cfg_read() and aspeed_pcie_cfg_write() handle register
accesses.
- aspeed_pcie_cfg_readwrite() provides configuration read/write support.
- aspeed_pcie_cfg_translate_write() handles PCIe byte-enable semantics for
write operations.
The reset handler initializes the H2X register block with default values
as defined in the AST2600 datasheet.
Additional changes:
- Implement ASPEED PCIe root complex (TYPE_ASPEED_PCIE_RC).
- Wire up interrupt propagation via aspeed_pcie_rc_set_irq().
- Add tracepoints for config read/write and INTx handling.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: cac2f082936de3c35c7b9c04fef4dc99b7af9898
https://github.com/qemu/qemu/commit/cac2f082936de3c35c7b9c04fef4dc99b7af9898
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2600 PCIe Root Device support
Introduce a PCIe Root Device for AST2600 platform.
The AST2600 root complex exposes a PCIe root device at bus 80, devfn 0.
This root device is implemented as a child of the PCIe RC and modeled
as a host bridge PCI function (class_id = PCI_CLASS_BRIDGE_HOST).
Key changes:
- Add a new device type "aspeed.pcie-root-device".
- Instantiate the root device as part of AspeedPCIERcState.
- Initialize it during RC realize() and attach it to the root bus.
- Mark the root device as non-user-creatable.
- Add RC boolean property "has-rd" to control whether the Root Device is
created (platforms can enable/disable it as needed).
Note: Only AST2600 implements this PCIe root device. AST2700 does not
provide one.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 2af56518fa911b8370adaaabc8823bfbab303613
https://github.com/qemu/qemu/commit/2af56518fa911b8370adaaabc8823bfbab303613
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable
Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port
is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT).
Key changes:
- Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs
and AER capability offset.
- Extend AspeedPCIERcState to embed a root_port instance and a
configurable rp_addr.
- Add "rp-addr" property to the RC to place the root port at a specific
devfn on the root bus.
- Set the root port's "chassis" property to ensure a unique chassis per RC.
- Extend AspeedPCIECfgClass with rc_rp_addr defaulting to PCI_DEVFN(8,0).
Rationale:
- AST2600 places the root port at 80:08.0 (bus 0x80, dev 8, fn 0).
- AST2700 must place the root port at 00:00.0, and it supports three RCs.
Each root port must therefore be uniquely identifiable; uses the
PCIe "chassis" ID for that.
- Providing a configurable "rp-addr" lets platforms select the correct
devfn per SoC family, while the "chassis" property ensures uniqueness
across multiple RC instances on AST2700.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 89f949e515f1bcc4858993f9a47ac7d2656e361a
https://github.com/qemu/qemu/commit/89f949e515f1bcc4858993f9a47ac7d2656e361a
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M hw/pci-host/trace-events
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC
"IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI
system memory (not normal DRAM). If the MSI window were mapped into real
system RAM, an endpoint's write could be observed by other RCs and
spuriously trigger their interrupts. To avoid this, each RC now owns an
isolated IOMMU root AddressSpace that contains a small MSI window and a
DRAM alias region for normal DMA.
The MSI window captures writes and asserts the RC IRQ. MSI status bits
are tracked in new H2X RC_H registers (R_H2X_RC_H_MSI_EN{0,1} and
R_H2X_RC_H_MSI_STS{0,1}). Clearing all status bits drops the IRQ. The
default MSI address is set to 0x1e77005c and can be overridden via the
msi-addr property.
This keeps MSI traffic contained within each RC while preserving normal
DMA to system DRAM. It enables correct MSI/MSI-X interrupt delivery when
multiple RCs use the same MSI target address.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 575846c056a320b3008436fc8c11d10616677722
https://github.com/qemu/qemu/commit/575846c056a320b3008436fc8c11d10616677722
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Wire up PCIe devices in SoC model
Add PCIe controller and PHY instances to the Aspeed SoC state and device
enum. This prepares the SoC model to host PCIe Root Complexes and their
associated PHYs.
Although the AST2600 supports only a single Root Complex, the AST2700
provides three Root Complexes. For this reason, the model defines arrays
of three PCIe config/PHY objects and enumerates three PCIe device IDs so
that both SoCs can be represented consistently.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a498916ba292ada19cc47df80e0e9507c63356fc
https://github.com/qemu/qemu/commit/a498916ba292ada19cc47df80e0e9507c63356fc
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast2600.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)
Wire up the PCIe Root Complex in the AST2600 SoC model.
According to the AST2600 firmware driver, only the RC_H controller is
supported. RC_H uses PCIe PHY1 at 0x1e6ed200 and the PCIe config (H2X)
register block at 0x1e770000. The RC_H MMIO window is mapped at
0x70000000–0x80000000. RC_L is not modeled. The RC_H interrupt is
wired to IRQ 168. Only RC_H is realized and connected to the SoC
interrupt controller.
The SoC integration initializes PCIe PHY1, instantiates a single RC
instance, wires its MMIO regions, and connects its interrupt. An alias
region is added to map the RC MMIO space into the guest physical address
space.
This provides enough functionality for firmware and guest drivers to
discover and use the AST2600 RC_H Root Complex while leaving RC_L
unimplemented.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ed2df979ab229feaa81327ad4941383c024116e6
https://github.com/qemu/qemu/commit/ed2df979ab229feaa81327ad4941383c024116e6
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2700 PCIe PHY
Introduce a PCIe Host Controller PHY model for AST2700. This adds an
AST2700 specific PHY type (TYPE_ASPEED_2700_PCIE_PHY) with a 0x800 byte
register space and link-status bits compatible with the firmware’s
expectations.
AST2700 provides three PCIe RCs; PCIe0 and PCIe1 are GEN4, PCIe2 is
GEN2. The PHY exposes:
PEHR_2700_LINK_GEN2 at 0x344, bit 18 indicates GEN2 link up
PEHR_2700_LINK_GEN4 at 0x358, bit 8 indicates GEN4 link up
In real hardware these GEN2/GEN4 link bits are mutually exclusive.
QEMU does not model GEN2 vs GEN4 signaling differences, so the reset
handler sets both bits to 1. This keeps the model simple and lets
firmware see the link as up; firmware will read the appropriate
register per RC port to infer the intended mode.
The header gains TYPE_ASPEED_2700_PCIE_PHY; the new class derives from
TYPE_ASPEED_PCIE_PHY, sets nr_regs to 0x800 >> 2, and installs an
AST2700 reset routine that programs the class code (0x06040011) and the
GEN2/GEN4 status bits.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ba6fb09048198a2952d731cd063f4307b137e7ec
https://github.com/qemu/qemu/commit/ba6fb09048198a2952d731cd063f4307b137e7ec
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
M include/hw/pci-host/aspeed_pcie.h
Log Message:
-----------
hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks
Introduce PCIe config (H2X) support for the AST2700 SoC.
Unlike the AST2600, the AST2700 provides three independent Root Complexes,
each with its own H2X (AHB to PCIe bridge) register block of size 0x100.
All RCs use the same MSI address (0x000000F0). The H2X block includes
two different access paths:
1. CFGI (internal bridge): used to access the host bridge itself, always
with BDF=0. The AST2700 controller simplifies the design by exposing
only one register (H2X_CFGI_TLP) with fields for ADDR[15:0], BEN[19:16],
and WR[20]. This is not a full TLP descriptor as in the external case.
For QEMU readability and code reuse, the model converts H2X_CFGI_TLP
into a standard TLP TX descriptor with BDF forced to 0 and then calls
the existing helpers aspeed_pcie_cfg_readwrite() and
aspeed_pcie_cfg_translate_write().
2. CFGE (external EP access): used to access external endpoints. The
AST2700 design provides H2X_CFGE_TLP1 and a small FIFO at H2X_CFGE_TLPN.
For reads, TX DESC0 is stored in TLP1 and DESC1/DESC2 in TLPN FIFO
slots. For writes, TX DESC0 is stored in TLP1, DESC1/DESC2 in TLPN
FIFO[0..1], and TX write data in TLPN FIFO[2].
The implementation extends AspeedPCIECfgState with a small FIFO and index,
wires up new register definitions for AST2700, and adds a specific ops
table and class (TYPE_ASPEED_2700_PCIE_CFG). The reset handler clears the
FIFO state. Interrupt and MSI status registers are also supported.
This provides enough modeling for firmware and drivers to use any of the
three PCIe RCs on AST2700 with their own dedicated H2X config window,
while reusing existing TLP decode helpers in QEMU.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ac30597ee859ecaa4a87688fbd722bb5bfe80bd7
https://github.com/qemu/qemu/commit/ac30597ee859ecaa4a87688fbd722bb5bfe80bd7
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/pci-host/aspeed_pcie.c
Log Message:
-----------
hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to
AST2700
AST2700 does not implement a PCIe Root Device; each RC exposes a single
PCIe Root Port at devfn 0:0.0.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 65996e84089459a4b52514a928988816e5c0bae0
https://github.com/qemu/qemu/commit/65996e84089459a4b52514a928988816e5c0bae0
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast27x0.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700
Add PCIe Root Complex support to the AST2700 SoC model.
The AST2700 A1 silicon revision provides three PCIe Root Complexes:
PCIe0 with its PHY at 0x12C15000, config (H2X) block at 0x120E0000,
MMIO window at 0x60000000, and GIC IRQ 56.
PCIe1 with its PHY at 0x12C15800, config (H2X) block at 0x120F0000,
MMIO window at 0x80000000, and GIC IRQ 57.
PCIe2 with its PHY at 0x14C1C000, config (H2X) block at 0x140D0000,
MMIO window at 0xA0000000, and IRQ routed through INTC4 bit 31
mapped to GIC IRQ 196.
Each RC instantiates a PHY device, a PCIe config (H2X) bridge, and an MMIO
alias region. The per-RC MMIO alias size is 0x20000000. The AST2700 A0
silicon revision does not support PCIe Root Complexes, so pcie_num is set
to 0 in that variant.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: d43f6db6548c997263949d8908b62dbab5fbd0ff
https://github.com/qemu/qemu/commit/d43f6db6548c997263949d8908b62dbab5fbd0ff
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M tests/functional/arm/test_aspeed_ast2600.py
Log Message:
-----------
tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test
Extend the AST2600 functional tests with PCIe and network checks.
This patch introduces a new helper "do_ast2600_pcie_test()" that runs "lspci"
on the emulated system and verifies the presence of the expected PCIe devices:
- 80:00.0 Host bridge: ASPEED Technology, Inc. Device 2600
- 80:08.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
- 81:00.0 Ethernet controller: Intel Corporation 82574L Gigabit Network
Connection
To exercise the PCIe network device, the test adds:
-device e1000e,netdev=net1,bus=pcie.0
-netdev user,id=net1
and assigns an IP address to the interface, verifying it with `ip addr`.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: f821557f4f7fc8ff7ed5c1950e6a12cfe47cdac5
https://github.com/qemu/qemu/commit/f821557f4f7fc8ff7ed5c1950e6a12cfe47cdac5
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc_common.c
Log Message:
-----------
hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code
Relocate aspeed_board_init_flashes() from hw/arm/aspeed.c into
hw/arm/aspeed_soc_common.c so the helper can be reused by all
ASPEED machines. The API was already declared in
include/hw/arm/aspeed_soc.h; this change moves its
implementation out of the machine file to keep aspeed.c cleaner.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 597165ec2fb018be8aa7cefa5e3424c39fcec226
https://github.com/qemu/qemu/commit/597165ec2fb018be8aa7cefa5e3424c39fcec226
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Move write_boot_rom to common SoC code
Move the write_boot_rom helper from hw/arm/aspeed.c into
hw/arm/aspeed_soc_common.c so it can be reused by all ASPEED
machines. Export the API as aspeed_write_boot_rom() in
include/hw/arm/aspeed_soc.h and update the existing call site
to use the new helper.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: a705e9997fd571427fc72d88c1235b1e2bd0c6fb
https://github.com/qemu/qemu/commit/a705e9997fd571427fc72d88c1235b1e2bd0c6fb
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC code
Move the boot ROM install helper into common SoC code so it can be reused
by all ASPEED boards, and decouple the API from AspeedMachineState.
Specifically:
- Move aspeed_install_boot_rom() to hw/arm/aspeed_soc_common.c and
declare it in include/hw/arm/aspeed_soc.h.
- Change the helper’s signature to take AspeedSoCState * and a
MemoryRegion * provided by the caller, instead of AspeedMachineState *.
- Update aspeed_machine_init() call sites accordingly.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: ecabf8ba94961a23f473e7060f8589e93967cfd2
https://github.com/qemu/qemu/commit/ecabf8ba94961a23f473e7060f8589e93967cfd2
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed.c
M hw/arm/aspeed_soc_common.c
M include/hw/arm/aspeed_soc.h
Log Message:
-----------
hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC code
Move the vbootrom loader helper into common SoC code so it can be reused
by all ASPEED boards, and decouple the API from AspeedMachineState.
Specifically:
- Move aspeed_load_vbootrom() to hw/arm/aspeed_soc_common.c and
declare it in include/hw/arm/aspeed_soc.h.
- Change the helper’s signature to take AspeedSoCState * instead of
AspeedMachineState *.
- Update aspeed_machine_init() call sites accordingly.
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 8d3aaefdb3bb13df7c57091a4319f3afe3c351ac
https://github.com/qemu/qemu/commit/8d3aaefdb3bb13df7c57091a4319f3afe3c351ac
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
Log Message:
-----------
hw/arm/aspeed_ast27x0-fc: Drop dead return checks
1. object_property_set_link() can return false only when it fails, and it
sets an error when it fails. Since passing &error_abort causes an abort,
the function never returns false, and the return statement is effectively
dead code.
2. object_property_set_int() is considered as a routine which shouldn't fail.
So the common practice in models is to pass &error_abort and ignore the
returned value.
https://patchwork.kernel.org/project/qemu-devel/patch/[email protected]/#26540626
No functional change.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 9ec30a07483640ecb8417fce3dfa9273f7a036c9
https://github.com/qemu/qemu/commit/9ec30a07483640ecb8417fce3dfa9273f7a036c9
Author: Jamin Lin <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M hw/arm/aspeed_ast27x0-fc.c
Log Message:
-----------
hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp
Refactor ast2700fc_ca35_init(), ast2700fc_ssp_init(), and ast2700fc_tsp_init()
to take an Error **errp parameter and return a bool.
Each function now reports failure through the error object and returns false.
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link:
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>
Commit: 85a3fd1c4cb3ba7a9eb291c1e222f935e922d1f7
https://github.com/qemu/qemu/commit/85a3fd1c4cb3ba7a9eb291c1e222f935e922d1f7
Author: Richard Henderson <[email protected]>
Date: 2025-09-29 (Mon, 29 Sep 2025)
Changed paths:
M docs/system/arm/aspeed.rst
M hw/arm/Kconfig
M hw/arm/aspeed.c
M hw/arm/aspeed_ast10x0.c
M hw/arm/aspeed_ast2600.c
M hw/arm/aspeed_ast27x0-fc.c
M hw/arm/aspeed_ast27x0.c
M hw/arm/aspeed_soc_common.c
M hw/misc/aspeed_sbc.c
M hw/misc/trace-events
A hw/nvram/aspeed_otp.c
M hw/nvram/meson.build
M hw/nvram/trace-events
M hw/pci-host/Kconfig
A hw/pci-host/aspeed_pcie.c
M hw/pci-host/meson.build
M hw/pci-host/trace-events
M include/hw/arm/aspeed_soc.h
M include/hw/misc/aspeed_sbc.h
A include/hw/nvram/aspeed_otp.h
A include/hw/pci-host/aspeed_pcie.h
M include/hw/pci/pci_ids.h
M tests/functional/aarch64/test_aspeed_ast2700.py
M tests/functional/arm/test_aspeed_ast1030.py
M tests/functional/arm/test_aspeed_ast2600.py
M tests/functional/aspeed.py
Log Message:
-----------
Merge tag 'pull-aspeed-20250929' of https://github.com/legoater/qemu into
staging
aspeed queue:
* Introduce a new ASPEED OTP memory device model integrated with the
Secure Boot Controller. It includes a new block device backend
('drive' property), is enabled for AST2600 SoCs and AST1030 SoCs.
Functional tests are included
* Changed "ast2700-evb" alias to point to the "ast2700a1-evb" machine
* Introduce support for Aspeed PCIe host controller, including models
for the PCIe Root Complex, Root Port, and PHY. Enabled for the
AST2600 and AST2700 SoCs, and functional tests are included
* Refactor Boot ROM support to improve code reuse across the different
Aspeed machine. This is in preparation of vbootrom support in the
ast2700fc machine
* Improved Error Handling in the AST27x0-fc machine init functions
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# gpg: Signature made Mon 29 Sep 2025 09:51:38 AM PDT
# gpg: using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg: aka "Cédric Le Goater <[email protected]>" [full]
* tag 'pull-aspeed-20250929' of https://github.com/legoater/qemu: (32 commits)
hw/arm/aspeed_ast27x0-fc: Make sub-init functions return bool with errp
hw/arm/aspeed_ast27x0-fc: Drop dead return checks
hw/arm/aspeed: Move aspeed_load_vbootrom to common SoC code
hw/arm/aspeed: Move aspeed_install_boot_rom to common SoC code
hw/arm/aspeed: Move write_boot_rom to common SoC code
hw/arm/aspeed: Move aspeed_board_init_flashes() to common SoC code
tests/functional/arm/test_aspeed_ast2600: Add PCIe and network test
hw/arm/aspeed_ast27x0: Introduce 3 PCIe RCs for AST2700
hw/pci-host/aspeed: Disable Root Device and place Root Port at 00:00.0 to
AST2700
hw/pci-host/aspeed: Add AST2700 PCIe config with dedicated H2X blocks
hw/pci-host/aspeed: Add AST2700 PCIe PHY
hw/arm/aspeed_ast2600: Add PCIe RC support (RC_H only)
hw/arm/aspeed: Wire up PCIe devices in SoC model
hw/pci-host/aspeed: Add MSI support and per-RC IOMMU address space
hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make address configurable
hw/pci-host/aspeed: Add AST2600 PCIe Root Device support
hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge
hw/pci-host/aspeed: Add AST2600 PCIe PHY model
hw/pci/pci_ids: Add PCI vendor ID for ASPEED
tests/functional/arm: Add AST2600 boot test with generated OTP image
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/9b16edec6e9a...85a3fd1c4cb3
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