Branch: refs/heads/staging
  Home:   https://github.com/qemu/qemu
  Commit: cacd8fb08d3f992ef9cdf4c26a2d28ced409cfd4
      
https://github.com/qemu/qemu/commit/cacd8fb08d3f992ef9cdf4c26a2d28ced409cfd4
  Author: Nabih Estefan <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/aspeed_ast27x0.c

  Log Message:
  -----------
  hw/arm/ast27x0: Fix typo in LTPI address

The address for LTPI has one more 0 that it should, bug introduced in
commit 91064bea6b2d747a981cb3bd2904e56f443e6c67.

Signed-off-by: Nabih Estefan <[email protected]>
Fixes: 91064bea6b2d ("aspeed: ast27x0: Map unimplemented devices in SoC memory")
Reviewed-by: Cédric Le Goater <[email protected]>
Link: 
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>


  Commit: 510d5c61ad3eb1690b61c804d38c984527a5ea62
      
https://github.com/qemu/qemu/commit/510d5c61ad3eb1690b61c804d38c984527a5ea62
  Author: Jamin Lin <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_ast27x0.c

  Log Message:
  -----------
  hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure

It did not connect SPI IRQ to the Interrupt Controller, so even the SPI
model raised the IRQ, the interrupt was not received. The CPU therefore
did not trigger an interrupt via the controller, and the firmware never
received the interrupt.

Fixes: 356b230ed13889e09d087a96498887de695df17e ("aspeed/soc: Add AST1030 
support")
Fixes: f25c0ae1079dc0b9de02676eb3e3949a09df9f41 ("aspeed/soc: Add AST2600 
support")
Fixes: 5dd883ab0635c9f715c77cc32622e458a0724581 ("aspeed/soc: Add AST2700 
support")
Signed-off-by: Jamin Lin <[email protected]>
Reviewed-by: Cédric Le Goater <[email protected]>
Link: 
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>


  Commit: e9a8b04dbb98fba7942b23b3ac5c35f2f0b9c4a0
      
https://github.com/qemu/qemu/commit/e9a8b04dbb98fba7942b23b3ac5c35f2f0b9c4a0
  Author: Jamin Lin <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/pci-host/aspeed_pcie.c

  Log Message:
  -----------
  hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable 
MSI to support hotplug

This patch updates the ASPEED PCIe Root Port capability layout and interrupt
handling to match the hardware-defined capability structure as documented in
the PCI Express Controller (PCIE) chapter of the ASPEED SoC datasheet.

The following capability offsets and fields are now aligned with the actual
hardware implementation (validated using EVB config-space dumps via
'lspci -s <bdf> -vvv'):

- Added MSI capability at offset 0x50 and enabled 1-vector MSI support
- Added PCI Express Capability structure at offset 0x80
- Added Secondary Subsystem Vendor ID (SSVID) at offset 0xC0
- Added AER capability at offset 0x100
- Implemented aer_vector() callback and MSI init/uninit hooks
- Updated Root Port SSID to 0x1150 to reflect the platform default

Enabling MSI is required for proper PCIe Hotplug event signaling. This change
improves correctness and ensures QEMU Root Port behavior matches the behavior
of ASPEED hardware and downstream kernel expectations.

Signed-off-by: Jamin Lin <[email protected]>
Fixes: 2af56518fa91 ("hw/pci-host/aspeed: Add AST2600 PCIe Root Port and make 
address configurable")
Reviewed-by: Cédric Le Goater <[email protected]>
Reviewed-by: Nabih Estefan <[email protected]>
Tested-by: Nabih Estefan <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Link: 
https://lore.kernel.org/qemu-devel/[email protected]
Signed-off-by: Cédric Le Goater <[email protected]>


  Commit: 4a5df192932a49f4e074162bd6d09dd33b18e3e9
      
https://github.com/qemu/qemu/commit/4a5df192932a49f4e074162bd6d09dd33b18e3e9
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    A contrib/gitdm/group-map-huawei
    M gitdm.config

  Log Message:
  -----------
  contrib/gitdm: add group-map for Huawei

While we do see contributions from the top-level domain some
contributors also post via other addresses.

Reviewed-by: Jonathan Cameron <[email protected]>
Reviewed-by: Mauro Carvalho Chehab <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: 9b6ceb68550a758cc7557ec5b49ddd413ed779c4
      
https://github.com/qemu/qemu/commit/9b6ceb68550a758cc7557ec5b49ddd413ed779c4
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    A contrib/gitdm/group-map-microsoft
    M gitdm.config

  Log Message:
  -----------
  contrib/gitdm: add group-map for Microsoft

While we do see contributions from the top-level domain we want to
catch the linux.microsoft subdomain and those contributors also post
via other addresses.

Cc: Magnus Kulke <[email protected]>
Acked-by: Wei Liu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: b6690596b2d26c3a1e4f698a497059be6c644eac
      
https://github.com/qemu/qemu/commit/b6690596b2d26c3a1e4f698a497059be6c644eac
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M contrib/gitdm/group-map-academics

  Log Message:
  -----------
  contrib/gitdm: add University of Tokyo to academic group

>From Akihiko:

  I and my colleagues use QEMU for academic microarchitecture
  researches so it is indeed to appropriate to have an entry here.

Reviewed-by: Akihiko Odaki <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: 93d39daebe007932c6d877f103d3abbe6ba20e7e
      
https://github.com/qemu/qemu/commit/93d39daebe007932c6d877f103d3abbe6ba20e7e
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M contrib/gitdm/domain-map

  Log Message:
  -----------
  contrib/gitdm: add mapping for Eviden

Reviewed-by: Clement Mathieu--Drif <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: e4799403d1a55b71d57f8db0284898ac4794e2ff
      
https://github.com/qemu/qemu/commit/e4799403d1a55b71d57f8db0284898ac4794e2ff
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M contrib/gitdm/domain-map

  Log Message:
  -----------
  contrib/gitdm: add mapping for Nutanix

We have a number of hackers from Nutanix, make sure they are grouped
together.

Reviewed-by: Jon Kohler <[email protected]>
Reviewed-by: John Levon <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: f5b6ca5606f8a1ed29a127847932fa2bc237ae38
      
https://github.com/qemu/qemu/commit/f5b6ca5606f8a1ed29a127847932fa2bc237ae38
  Author: Alex Bennée <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M contrib/gitdm/group-map-individuals

  Log Message:
  -----------
  contrib/gitdm: add more individual contributors

I only add names explicitly acked as individual contributors.

Acked-by: Sean Wei <[email protected]>
Acked-by: William Kosasih <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alex Bennée <[email protected]>


  Commit: 697ccce3c50145a82e6f754cc8fc75b209f241ba
      
https://github.com/qemu/qemu/commit/697ccce3c50145a82e6f754cc8fc75b209f241ba
  Author: Bernhard Beschow <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/Kconfig

  Log Message:
  -----------
  hw/arm/Kconfig: Exclude imx8mp-evk machine from KVM-only build

Fixes make check failures on an aarch64 host when QEMU is configured
using '--enable-kvm --disable-tcg':
  qemu-system-aarch64: unknown type 'arm-gicv3'

Reported-by: Cornelia Huck <[email protected]>
Tested-by: Cornelia Huck <[email protected]>
Reviewed-by: Cornelia Huck <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Message-id: [email protected]
Suggested-by: Peter Maydell <[email protected]>
Tested-by: Cornelia Huck <[email protected]>
Reviewed-by: Cornelia Huck <[email protected]>
Signed-off-by: Bernhard Beschow <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>


  Commit: fa9d9f6b71c9412c96a8adc92402c78a01049bd1
      
https://github.com/qemu/qemu/commit/fa9d9f6b71c9412c96a8adc92402c78a01049bd1
  Author: Philippe Mathieu-Daudé <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/display/exynos4210_fimd.c

  Log Message:
  -----------
  hw/display/exynos4210_fimd: Remove duplicated definition

FIMD_VIDWADD0_END is defined twice, keep only one.

Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]
Reviewed-by: Peter Maydell <[email protected]>
Signed-off-by: Peter Maydell <[email protected]>


  Commit: 4a934d284dfac9fa19b0f47874f12d9b3519c21c
      
https://github.com/qemu/qemu/commit/4a934d284dfac9fa19b0f47874f12d9b3519c21c
  Author: Peter Maydell <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/armv7m.c

  Log Message:
  -----------
  hw/arm/armv7m: Disable reentrancy guard for v7m_sysreg_ns_ops MRs

For M-profile cores which support TrustZone, there are some memory
areas which are "NS aliases" -- a Secure access to these addresses
really performs an NS access to a different part of the device.  We
implement these using MemoryRegionOps read and write functions which
pass the access on with adjusted attributes using
memory_region_dispatch_read() and memory_region_dispatch_write().

Since the MR we are dispatching to is owned by the same device that
owns the NS-alias MR (the TYPE_ARMV7M container object), this trips
the reentrancy-guard that is applied by access_with_adjusted_size().

Mark the NS alias MemoryRegions as disable_reentrancy_guard; this is
safe because v7m_sysreg_ns_read() and v7m_sysreg_ns_write() do not
touch any of the device's state.  (Any further reentrancy attempts by
the underlying MR will still be caught.)

Without this fix, an attempt to read from an address like 0xe002e010,
which is a register in the NS systick alias, will fail and provoke

 qemu-system-arm: warning: Blocked re-entrant IO on MemoryRegion: v7m_systick 
at addr: 0x0

We didn't notice this earlier because almost all code accesses
the registers and systick via the non-alias addresses; the NS
aliases are only need for the rarer case of Secure code that needs
to manage the NS timer or system state on behalf of NS code.

Note that although the v7m_systick_ops read and write functions
also call memory_region_dispatch_{read,write}, this MR does not
need to have the reentrancy-guard disabled because the underlying
MR that it forwards to is owned by a different device (the
TYPE_SYSTICK timer device).

Reported via a stackoverflow question:
https://stackoverflow.com/questions/79808107/what-this-error-is-even-about-qemu-system-arm-warning-blocked-re-entrant-io

Cc: [email protected]
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]


  Commit: 579be921f509fb9d2deccc4233496e36b221abb3
      
https://github.com/qemu/qemu/commit/579be921f509fb9d2deccc4233496e36b221abb3
  Author: Peter Maydell <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/display/exynos4210_fimd.c

  Log Message:
  -----------
  hw/display/exynos4210_fimd: Account for zero length in 
fimd_update_memory_section()

In fimd_update_memory_section() we attempt ot find and map part of
the RAM MR which backs the framebuffer, based on guest-configurable
size and start address.

If the guest configures framebuffer settings which result in a
zero-sized framebuffer, we hit an assertion(), because
memory_region_find() will return a NULL mem_section.mr.

Explicitly check for the zero-size case and treat this as a
guest error.

Because we now have a code path which can reach error_return without
calling memory_region_find to set w->mem_section, we must NULL out
w->mem_section.mr after the unref of the old MR, so that error_return
does not incorrectly double-unref the old MR.

Cc: [email protected]
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1407
Signed-off-by: Peter Maydell <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-id: [email protected]


  Commit: 596e4b7bf5254cd61c6e1f6761eac414138e6e6e
      
https://github.com/qemu/qemu/commit/596e4b7bf5254cd61c6e1f6761eac414138e6e6e
  Author: Richard Henderson <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/aspeed_ast10x0.c
    M hw/arm/aspeed_ast2600.c
    M hw/arm/aspeed_ast27x0.c
    M hw/pci-host/aspeed_pcie.c

  Log Message:
  -----------
  Merge tag 'pull-aspeed-20251124' of https://github.com/legoater/qemu into 
staging

aspeed queue:

* Fixed typo in the AST2700 LTPI device
* Fixed missing wiring of the SPI IRQ in AST10x0, AST2600, AST2700 SoCs
* Updated ASPEED PCIe Root Port capabilities and MSI support

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEoPZlSPBIlev+awtgUaNDx8/77KEFAmkkA5wACgkQUaNDx8/7
# 7KG/xg/+LqpKxeFhofFSini+NLcD6gelGf2svIlz/q7Q5NhbgBdVC77g7L8aUho3
# gphaMmpafwyUW7OqtddB6FINDOVR8UnbU7NJJv5hedmgC+oxdpMrG2PiIPr6TsRu
# 6g/f4YvEMsehKAJm+x9APCFHmr9bTuY1iVwDJ3jfzWUBo8VPOT+duTLLTmc/RypZ
# elupzVTN7+RwVi18cYkrSQEtkmkz1U42W9ZG+PUKAdta0VfRTSReiEFGsD8pY/CB
# ndPbeEYVwIF2ezH5pXUneXgwMFM/ANYpNx2VXRuWabaRZMfChiDiHBOYt/CvfTH+
# v/o52sjbHtPJ2rKWKnZO+VBuV8Frwz9HgWAKLpoEurTolrnbA592BIxo3XaMS/eq
# 5a3HJ6wHAoU6qfiI3JSsP42nsCh5Ercf1mX8ArJlLePT/5XiQ3/MLBiESHXPptkm
# 4XBwG9zkr6zVhTm+Yj789rSlQgL+7cPZ78bMwCNhFHHXtZSpiWUP1e3LdVIX4pkP
# 1CPNyXRA+DDQEvksKkE6XkQZrnjydRbwCGrtNpuPkFmWDq9vQhUCjaKQBcutYgcD
# mbJVTeK3e7za/toWf88eNOWaJ7D+syXSQ8AfACkg5bG5zKreaQOLc2oC8UDcVJSE
# 3nwj12jDbfbmTDcFOY3diEhA8JiwylagiMZNiSx7bN9t+RO1jlQ=
# =DmJM
# -----END PGP SIGNATURE-----
# gpg: Signature made Sun 23 Nov 2025 11:05:00 PM PST
# gpg:                using RSA key A0F66548F04895EBFE6B0B6051A343C7CFFBECA1
# gpg: Good signature from "Cédric Le Goater <[email protected]>" [full]
# gpg:                 aka "Cédric Le Goater <[email protected]>" [full]

* tag 'pull-aspeed-20251124' of https://github.com/legoater/qemu:
  hw/pci-host/aspeed_pcie: Update ASPEED PCIe Root Port capabilities and enable 
MSI to support hotplug
  hw/arm/aspeed: Fix missing SPI IRQ connection causing DMA interrupt failure
  hw/arm/ast27x0: Fix typo in LTPI address

Signed-off-by: Richard Henderson <[email protected]>


  Commit: 9cef16dd2246194ce961ccbef3596be0eee59439
      
https://github.com/qemu/qemu/commit/9cef16dd2246194ce961ccbef3596be0eee59439
  Author: Richard Henderson <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M contrib/gitdm/domain-map
    M contrib/gitdm/group-map-academics
    A contrib/gitdm/group-map-huawei
    M contrib/gitdm/group-map-individuals
    A contrib/gitdm/group-map-microsoft
    M gitdm.config

  Log Message:
  -----------
  Merge tag 'pull-10.2-gitdm-241125-1' of https://gitlab.com/stsquad/qemu into 
staging

gitdm updates for 2025

With the latest updates the last year has been made possible by:

  Top changeset contributors by employer
  Linaro                    2959 (37.0%)
  Red Hat                   1919 (24.0%)
  Intel                      313 (3.9%)
  (None)                     308 (3.9%)
  ASPEED Technology Inc.     231 (2.9%)
  Loongson Technology        227 (2.8%)
  IBM                        192 (2.4%)
  Oracle                     187 (2.3%)
  Nutanix                    133 (1.7%)
  Academics (various)         99 (1.2%)

  Top lines changed by employer
  Linaro                    109812 (31.8%)
  Red Hat                   91050 (26.4%)
  ASPEED Technology Inc.    11811 (3.4%)
  Intel                     10606 (3.1%)
  IBM                       10146 (2.9%)
  (None)                    8965 (2.6%)
  Oracle                    8574 (2.5%)
  Loongson Technology       7614 (2.2%)
  Nutanix                   7404 (2.1%)
  Microsoft                 6927 (2.0%)

  Employers with the most hackers (total 433)
  Red Hat                     54 (12.5%)
  IBM                         30 (6.9%)
  Intel                       17 (3.9%)
  (None)                      13 (3.0%)
  AMD                         13 (3.0%)
  Google                      11 (2.5%)
  Rivos Inc                   10 (2.3%)
  Linaro                       9 (2.1%)
  Oracle                       8 (1.8%)
  Huawei                       8 (1.8%)

# -----BEGIN PGP SIGNATURE-----
#
# iQEzBAABCgAdFiEEZoWumedRZ7yvyN81+9DbCVqeKkQFAmkkKsAACgkQ+9DbCVqe
# KkRbcQgAhc2I0HQa9fqFnp8vAZPMEEp3FFuPf1Dhwl4SWP95uZe/giooFyUhoZjw
# fmLu3V+Tza1oX9ymgHcbGu465jgIORotIG9c2jfTNStbWQWMLT+3fsS3+/9oNgry
# TtTNrSR2RpcUvnOWbMCPm68FiekQEmm4lbzNjh5uuGb6IddFyP/gZatbdMw3KzaX
# kYKnlV6Ul5wBjzfH68paRfC1ZcM0/iPy5EbK3FhPVozpA3fV729ZR535WnFHNjc9
# Gk6+oN2o4KQnvgSBY00NNnKUMcvMnvg3LSgmd2YUWh3O5jfVBbzaebP06HgfjLI3
# WwBdlAnhAQRFZqJhiH7mCVmJhuwigQ==
# =OPEI
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 24 Nov 2025 01:52:00 AM PST
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) 
<[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* tag 'pull-10.2-gitdm-241125-1' of https://gitlab.com/stsquad/qemu:
  contrib/gitdm: add more individual contributors
  contrib/gitdm: add mapping for Nutanix
  contrib/gitdm: add mapping for Eviden
  contrib/gitdm: add University of Tokyo to academic group
  contrib/gitdm: add group-map for Microsoft
  contrib/gitdm: add group-map for Huawei

Signed-off-by: Richard Henderson <[email protected]>


  Commit: de074358e99b8eb5076d3efa267e44c292c90e3e
      
https://github.com/qemu/qemu/commit/de074358e99b8eb5076d3efa267e44c292c90e3e
  Author: Richard Henderson <[email protected]>
  Date:   2025-11-24 (Mon, 24 Nov 2025)

  Changed paths:
    M hw/arm/Kconfig
    M hw/arm/armv7m.c
    M hw/display/exynos4210_fimd.c

  Log Message:
  -----------
  Merge tag 'pull-target-arm-20251124' of https://gitlab.com/pm215/qemu into 
staging

target-arm queue:
 * hw/display/exynos4210_fimd: Account for zero length in 
fimd_update_memory_section()
 * hw/arm/armv7m: Disable reentrancy guard for v7m_sysreg_ns_ops MRs
 * hw/display/exynos4210_fimd: Remove duplicated definition
 * hw/arm/Kconfig: Exclude imx8mp-evk machine from KVM-only build

# -----BEGIN PGP SIGNATURE-----
#
# iQJNBAABCAA3FiEE4aXFk81BneKOgxXPPCUl7RQ2DN4FAmkka80ZHHBldGVyLm1h
# eWRlbGxAbGluYXJvLm9yZwAKCRA8JSXtFDYM3hVpD/48w6peqEy8HmLtmrswBdVt
# TIYAkcz3oGNDnpYqB0UsjEVvmtAQZtGLS0XaOSVlB3l8NPiGe5GFwJJmt8TYBUpB
# rl76Cbmnx9lHyJshuoHb7CdtY2Q2gWxQPaeqD+cFvWTa/HNzeMO8joS9EkNApubP
# B7SQpcZuMgv4mgBTM3ly2/9mmFkKyY+/gkvtOmTMS/wGjrhpIs8DWIgLZ5/odmI5
# +c15aNOsfsnZ7KEsawRyYpn1pV2YeoYWYbQqQGOVLLfF7y/mLSfkI35SoXHI79zu
# nU0f/8NKhFswtx+SoAuQtHmnGLpgc5gRL21hwHZxiLkLQif1HgfCT3YNM2V/03ll
# +n5lOZzvNY4TLaoc5R9a2B+DRpp7ihrDnpW+tUV5LIhpDT4eqRto6+ATqlJ0Hfkw
# konwiahSAuHMMpnmfKbDvieVQasOZZBI0bpdwj3/yzXKh91/cYhAE4RySC1qLWe+
# dHeroqdyWKxbxetQz14kwJVWHDrvZSiSVpc1uVHWYBnrP310kMXlkgGt7MA2qiw5
# Dm01Dz/Upc+FpLGUqwHhZPWf2sJLdQVRqGwEevRkJl80AFpCR10JbSqwN4Fpz2gg
# YlkHmFhJfNM7FYoD+c6y4USwxiv0mMmtkIMuR2csmY5F5oH18H6zJ0lYikz5I0eo
# MVcNV1lPilWh7lKAKlLlGQ==
# =+CbZ
# -----END PGP SIGNATURE-----
# gpg: Signature made Mon 24 Nov 2025 06:29:33 AM PST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "[email protected]"
# gpg: Good signature from "Peter Maydell <[email protected]>" [unknown]
# gpg:                 aka "Peter Maydell <[email protected]>" [unknown]
# gpg:                 aka "Peter Maydell <[email protected]>" 
[unknown]
# gpg:                 aka "Peter Maydell <[email protected]>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20251124' of https://gitlab.com/pm215/qemu:
  hw/display/exynos4210_fimd: Account for zero length in 
fimd_update_memory_section()
  hw/arm/armv7m: Disable reentrancy guard for v7m_sysreg_ns_ops MRs
  hw/display/exynos4210_fimd: Remove duplicated definition
  hw/arm/Kconfig: Exclude imx8mp-evk machine from KVM-only build

Signed-off-by: Richard Henderson <[email protected]>


Compare: https://github.com/qemu/qemu/compare/fb241d0a1fd3...de074358e99b

To unsubscribe from these emails, change your notification settings at 
https://github.com/qemu/qemu/settings/notifications

Reply via email to