Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: b619c41593e9e8cd3dfffc550e29745df1357f17
https://github.com/qemu/qemu/commit/b619c41593e9e8cd3dfffc550e29745df1357f17
Author: Thomas Huth <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M tests/functional/riscv64/test_sifive_u.py
Log Message:
-----------
tests/functional/riscv64/test_sifive_u: Remove unused import statement
skipIfMissingCommands is not used here, remove the import to silence
a pylint warning for this file.
Signed-off-by: Thomas Huth <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 044bc505b10cefb5356fe46ac6ba176146f6e6f9
https://github.com/qemu/qemu/commit/044bc505b10cefb5356fe46ac6ba176146f6e6f9
Author: Alistair Francis <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/core/loader.c
Log Message:
-----------
hw/core/loader: Fixup whitespace for get_image_size()
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by:Vishal Chourasia <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 98d3546f01296af6b61b494b6e01bf0dc68039c0
https://github.com/qemu/qemu/commit/98d3546f01296af6b61b494b6e01bf0dc68039c0
Author: Alistair Francis <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/core/loader.c
Log Message:
-----------
hw/core/loader: Free the image file descriptor on error
Coverity: CID 1642764
Fixes: f62226f7dc4 ("hw/core/loader: improve error handling in image loading
functions")
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Vishal Chourasia <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: de0a5b1fbd1f842719af9311ba2a3bcd0d2bc482
https://github.com/qemu/qemu/commit/de0a5b1fbd1f842719af9311ba2a3bcd0d2bc482
Author: Alistair Francis <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/core/loader.c
Log Message:
-----------
hw/core/loader: Free the allocated string from size_to_str()
The string needs be be freed with g_free() according to the functions
documentation.
Coverity: CID 1642762
Fixes: f62226f7dc44 ("hw/core/loader: improve error handling in image loading
functions")
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c10187b12da52d6c4ac9e37db422c89d5df3e9bb
https://github.com/qemu/qemu/commit/c10187b12da52d6c4ac9e37db422c89d5df3e9bb
Author: Daniel Henrique Barboza <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu: add riscv_dump_csr() helper
riscv_cpu_dump_state() is using the same pattern to print a CSR given
its number. Add a helper to avoid code repetition.
While we're at it fix the identation of the 'flags & CPU_DUMP_VPU'
block.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 8e35971a561bdbaa8948f6cb32023d3de88e821d
https://github.com/qemu/qemu/commit/8e35971a561bdbaa8948f6cb32023d3de88e821d
Author: Daniel Henrique Barboza <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
Log Message:
-----------
target/riscv/cpu: print all FPU CSRs in riscv_cpu_dump_state()
We're missing fflags and frm.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 354c16c69f371a1e68bc9feb501a6c2a4410944e
https://github.com/qemu/qemu/commit/354c16c69f371a1e68bc9feb501a6c2a4410944e
Author: Daniel Henrique Barboza <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: print all available CSRs in riscv_cpu_dump_state()
At this moment we're printing a small selection of CSRs. There's no
particular reason to not print all of them.
We're ignoring the note about CSR_SSTATUS being ommited because it can
be read via CSR_MSTATUS. There's a huge list of CSRs that would fall in
this category and it would be an extra burden to manage them, not
mentioning having to document "we're not listing X because it's the same
value as Y" to users.
Remove 'dump_csrs' and use the existing 'csr_ops' array to print all
available CSRs. Create two helpers in csr.c to identify FPU and VPU CSRs
and skip them - they'll be printed in the FPU/VPU blocks later.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 7e89ab5eab7c38acdaa532154bd88107c8dead34
https://github.com/qemu/qemu/commit/7e89ab5eab7c38acdaa532154bd88107c8dead34
Author: Daniel Henrique Barboza <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M docs/specs/riscv-aia.rst
Log Message:
-----------
docs/specs/riscv-aia.rst: add 'riscv-aia' accel prop info
Add a small section talking about the 'riscv-aia' KVM setting we
implement and how it affects the provisioning of the IMSIC s-mode
in-kernel controller.
While we're at it, fix the formatting of the AIA bullet list.
Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c497ef6739cfb44b4fdb410ad997e3d2ea506788
https://github.com/qemu/qemu/commit/c497ef6739cfb44b4fdb410ad997e3d2ea506788
Author: Akihiko Odaki <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv/riscv-iommu: Fix MemoryRegion owner
as points to the MemoryRegion itself. s is the device that owns the
MemoryRegion.
Signed-off-by: Akihiko Odaki <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Nutty Liu <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 740021e278bf0b875d616b454a5c453308eac98e
https://github.com/qemu/qemu/commit/740021e278bf0b875d616b454a5c453308eac98e
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/machine.c
Log Message:
-----------
target/riscv: Fix size of trivial CPUArchState fields
This commits groups together all CPUArchState fields whose behaviour can
be retained by simply changing the size of the field.
Note, senvcfg is defined to be SXLEN bits wide, but is widened to 64
bits to match henvcfg and menvcfg. Next, [m|h]edeleg are changed to
64 bits as defined privileged specification, and hvictl is fixed to 32
bits which holds all relevant values, see HVICTL_VALID_MASK. The
remaining fields touched in the commit are widened from [H|S|M]XLEN
to 64-bit.
Note, the cpu/hyper, cpu/envcfg, cpu/jvt, and cpu VMSTATE versions are
bumped, breaking migration from older versions.
References to the privileged/unprivileged RISCV specification refer to
version 20250508.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: bd008558d25278f8424d6ca45370d09bee1ef754
https://github.com/qemu/qemu/commit/bd008558d25278f8424d6ca45370d09bee1ef754
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/cpu_helper.c
M target/riscv/machine.c
M target/riscv/tcg/tcg-cpu.c
Log Message:
-----------
target/riscv: Fix size of mhartid
and update formatting in log.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: d9fa41e10156ee9c989f8556adc0fafcaf83d2da
https://github.com/qemu/qemu/commit/d9fa41e10156ee9c989f8556adc0fafcaf83d2da
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Bugfix make bit 62 read-only 0 for sireg* cfg CSR read
According to version 20250508 of the privileged specification, a read of
cyclecfg or instretcfg through sireg* should make the MINH bit
read-only 0, currently bit 30 is zeroed.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: c9efdb7b63a4d84745e3765426a0442f7966c779
https://github.com/qemu/qemu/commit/c9efdb7b63a4d84745e3765426a0442f7966c779
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Combine mhpmevent and mhpmeventh
According to version 20250508 of the privileged specification,
mhpmeventn is 64 bits in size and mhpmeventnh is only ever used
when XLEN == 32 and accesses the top 32 bits of the 64-bit
mhpmeventn registers. Combine the two arrays of target_ulong
mhpmeventh[] and mhpmevent[] to a single array of uint64_t.
This also allows for some minor code simplification where branches
handling either mhpmeventh[] or mhpmevent[] could be combined.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 6c07ca842b559cf48fb58d0c518cb49b0b6db959
https://github.com/qemu/qemu/commit/6c07ca842b559cf48fb58d0c518cb49b0b6db959
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Combine mcyclecfg and mcyclecfgh
According to version 20250508 of the privileged specification, mcyclecfg
is a 64-bit register and mcyclecfgh refers to the top 32 bits of this
register when XLEN == 32. No real advantage is gained by keeping
them separate, and combining them allows for slight simplification.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: bb951e47f9394fe70e159d7c147829148290464f
https://github.com/qemu/qemu/commit/bb951e47f9394fe70e159d7c147829148290464f
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Combine minstretcfg and minstretcfgh
According to version 20250508 of the privileged specification,
minstretcfg is a 64-bit register and minstretcfgh refers to the top
32 bits of this register when XLEN == 32. No real advantage is
gained by keeping them separate, and combining them allows for slight
simplification.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4fe8ae09062d5c15c77c340d7a235b0d67d3e2b0
https://github.com/qemu/qemu/commit/4fe8ae09062d5c15c77c340d7a235b0d67d3e2b0
Author: Anton Johansson <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.h
M target/riscv/csr.c
M target/riscv/machine.c
M target/riscv/pmu.c
Log Message:
-----------
target/riscv: Combine mhpmcounter and mhpmcounterh
According to version 20250508 of the privileged specification,
mhpmconter is a 64-bit register and mhpmcounterh refers to the top
32 bits of this register when XLEN == 32. No real advantage is
gained by keeping them separate, and combining allows for slight
simplification.
Note, the cpu/pmu VMSTATE version is bumped breaking migration from
older versions.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: cfc96df65e01b339fc8b544ad56863279c80decb
https://github.com/qemu/qemu/commit/cfc96df65e01b339fc8b544ad56863279c80decb
Author: Alistair Francis <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/csr.c
Log Message:
-----------
target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val
Now that mhpmcounter is always a 64-bit value we can remove the
upper_half argument from riscv_pmu_ctr_get_fixed_counters_val() and
always return a 64-bit value.
Signed-off-by: Alistair Francis <[email protected]>
Reviewed-by: Anton Johansson <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 7c96dbdda8faf3a8318bd4e7898aa71a1c8a07b2
https://github.com/qemu/qemu/commit/7c96dbdda8faf3a8318bd4e7898aa71a1c8a07b2
Author: Nikita Novikov <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i]
According to the RISC-V AIA v1.0, section 4.5.2 ("Source configurations"),
register target[i] shall be read-only zero when interrupt source i is inactive
in this domain. A source is inactive if it is delegated to a child domain or
its source mode is INACTIVE.
The previous implementation only checked SM == INACTIVE. This patch adds
full compliance:
- Return zero on read if D == 1 or SM == INACTIVE
- Ignore writes in both cases
Fixes: b6f1244678 ("intc/riscv_aplic: Fix target register read when source is
inactive")
Signed-off-by: Nikita Novikov <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b88df155921fda9c7cac8425ca534602505ebf22
https://github.com/qemu/qemu/commit/b88df155921fda9c7cac8425ca534602505ebf22
Author: Nikita Novikov <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/intc/riscv_aplic.c
Log Message:
-----------
hw/intc/riscv_aplic: Factor out source_active() and remove duplicate checks
Refactor the APLIC code to consolidate repeated conditions checking
whether an interrupt source is valid, delegated, or inactive.
Signed-off-by: Nikita Novikov <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 15406cc593a76f075f23e4113b2723190e6a0d1a
https://github.com/qemu/qemu/commit/15406cc593a76f075f23e4113b2723190e6a0d1a
Author: Frank Chang <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/riscv/riscv-iommu.c
Log Message:
-----------
hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
According to the RISC-V IOMMU specification:
* When ddtp.iommu_mode is set to Off, there is no DDT look-up, and an "All
inbound transactions disallowed" fault (cause = 256) is reported for any
inbound transaction.
* When ddtp.iommu_mode is set to Bare, there is no DDT look-up, and the
translated address is the same as the IOVA, unless the transaction type
is disallowed (cause = 260).
In the current implementation, the DDT cache is incorrectly looked up
even when ddtp.iommu_mode is set to Off or Bare. This may result in
unintended cache hits.
Therefore, the DDT cache must not be looked up when ddtp.iommu_mode is
set to Off or Bare. For other modes, software is required to issue cache
invalidation commands before any inbound transactions.
Signed-off-by: Frank Chang <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Jim Shu <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 4975960510c3660a8f1ff2f3b6f8c8583184b59c
https://github.com/qemu/qemu/commit/4975960510c3660a8f1ff2f3b6f8c8583184b59c
Author: lxx <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn16.decode
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_zilsd.c.inc
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
Log Message:
-----------
target/riscv: Add Zilsd and Zclsd extension support
This patch adds support for the Zilsd and Zclsd extension,
which is documented at https://github.com/riscv/riscv-zilsd/releases/tag/v1.0
Signed-off-by: LIU Xu <[email protected]>
Co-developed-by: SUN Dongya <[email protected]>
Co-developed-by: ZHAO Fujin <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 26154585c69c9fde612d78a1adeddb3ea71e24ce
https://github.com/qemu/qemu/commit/26154585c69c9fde612d78a1adeddb3ea71e24ce
Author: Roan Richmond <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzalasr.c.inc
M target/riscv/translate.c
Log Message:
-----------
Add RISCV ZALASR extension
This is based on version v0.9 of the ZALASR specification [1].
The specification is listed as in Ratified state [2].
[1]: https://github.com/riscv/riscv-zalasr/tree/v0.9
[2]:
https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154882/All+RISC-V+Specifications+Under+Active+Development
Reviewed-by: Alistair Francis <[email protected]>
Signed-off-by: Roan Richmond <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 209c2c9af6259054938ab4c0226e5a41ee92d4ec
https://github.com/qemu/qemu/commit/209c2c9af6259054938ab4c0226e5a41ee92d4ec
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
Log Message:
-----------
target/riscv: Add cpu_set_exception_base
Add a new function, so we can change reset vector from platforms
during runtime.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 38e63ea61a4b84349f98550495038b20e4db099e
https://github.com/qemu/qemu/commit/38e63ea61a4b84349f98550495038b20e4db099e
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu_vendorid.h
Log Message:
-----------
target/riscv: Add MIPS P8700 CPU
Introduce P8700 CPU by MIPS.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: dfe2b6fa76333a7fc126f15899343ccd6301b58b
https://github.com/qemu/qemu/commit/dfe2b6fa76333a7fc126f15899343ccd6301b58b
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/meson.build
A target/riscv/mips_csr.c
Log Message:
-----------
target/riscv: Add MIPS P8700 CSRs
Define MIPS CSRs used for P8700 CPU.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2d9f941085e1cfa8f825e0f7d077130fa06d3d66
https://github.com/qemu/qemu/commit/2d9f941085e1cfa8f825e0f7d077130fa06d3d66
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
A target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/meson.build
M target/riscv/translate.c
A target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add mips.ccmov instruction
Add mips.ccmov defined by Xmipscmov.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0bc1d40977491dee87d89b9a1a22d25a9a5861b7
https://github.com/qemu/qemu/commit/0bc1d40977491dee87d89b9a1a22d25a9a5861b7
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add mips.pref instruction
Add MIPS P8700 prefetch instruction defined by Xmipscbop.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 84635b939629b5eee54fe3f2815d1077a939248d
https://github.com/qemu/qemu/commit/84635b939629b5eee54fe3f2815d1077a939248d
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M target/riscv/cpu.c
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/insn_trans/trans_xmips.c.inc
M target/riscv/xmips.decode
Log Message:
-----------
target/riscv: Add Xmipslsp instructions
Add MIPS P8700 ldp, lwp, sdp, swp instructions.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 290a1f174ee004346c878fddc0728d34ae382898
https://github.com/qemu/qemu/commit/290a1f174ee004346c878fddc0728d34ae382898
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cmgcr.c
A include/hw/misc/riscv_cmgcr.h
Log Message:
-----------
hw/misc: Add RISC-V CMGCR device implementation
Add RISC-V implementation of the Coherent Manager Global Control
Register (CMGCR) device. It is based on the existing MIPS CMGCR
implementation but adapted for RISC-V systems.
The CMGCR device provides global system control for multi-core
configurations in RISC-V systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 0cf4a87966da3a3e01e45a88fa1019bc249ffda5
https://github.com/qemu/qemu/commit/0cf4a87966da3a3e01e45a88fa1019bc249ffda5
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cpc.c
A include/hw/misc/riscv_cpc.h
Log Message:
-----------
hw/misc: Add RISC-V CPC device implementation
Add RISC-V implementation of the Cluster Power Controller (CPC) device.
It is based on the existing MIPS CPC implementations but adapted for
RISC-V systems.
The CPC device manages power control for CPU clusters in RISC-V
systems.
This is needed for the MIPS BOSTON AIA board.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 12eda1a6aa939b96ed14f6ed9bc7f4ca9a91b185
https://github.com/qemu/qemu/commit/12eda1a6aa939b96ed14f6ed9bc7f4ca9a91b185
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/misc/Kconfig
A hw/riscv/cps.c
M hw/riscv/meson.build
A include/hw/riscv/cps.h
Log Message:
-----------
hw/riscv: Add support for RISCV CPS
Add support for the Coherent Processing System for RISC-V.
This enables SMP support for RISC-V boards that require
cache-coherent multiprocessor systems.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 2264f637da7d397467648bc4aabd57d0f74bbb91
https://github.com/qemu/qemu/commit/2264f637da7d397467648bc4aabd57d0f74bbb91
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M configs/devices/riscv64-softmmu/default.mak
A docs/system/riscv/mips.rst
M docs/system/target-riscv.rst
M hw/riscv/Kconfig
A hw/riscv/boston-aia.c
M hw/riscv/meson.build
Log Message:
-----------
hw/riscv: Add support for MIPS Boston-aia board mode
The board model supports up to 64 harts with MIPS CPS, MIPS GCR,
MIPS CPC, AIA plic, and AIA clint devices. The model can create
boot code, if there is no -bios parameter. We can specify -smp x,
cores=y,thread=z.
Ex: Use 4 cores and 2 threads with each core to
have 8 smp cpus as follows.
qemu-system-riscv64 -cpu mips-p8700 \
-m 2G -M boston-aia \
-smp 8,cores=4,threads=2 -kernel fw_payload.bin \
-drive file=rootfs.ext2,format=raw -serial stdio
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: 94081c10af46bc1d02fc29c5717ddcbaa382bce1
https://github.com/qemu/qemu/commit/94081c10af46bc1d02fc29c5717ddcbaa382bce1
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M hw/riscv/boston-aia.c
Log Message:
-----------
riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
The Boston AIA board needs a basic GbE NIC. There is no PCH GbE
device emulation, so use an `e1000e` instead. We place it in
**slot 0, function 1** in order not to conflict with the existing
AHCI device in slot 0 func 0.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: e71111e26bdf5e98243d6a896c9e595e205dd9bb
https://github.com/qemu/qemu/commit/e71111e26bdf5e98243d6a896c9e595e205dd9bb
Author: Djordje Todorovic <[email protected]>
Date: 2026-01-09 (Fri, 09 Jan 2026)
Changed paths:
M tests/functional/riscv64/meson.build
A tests/functional/riscv64/test_boston.py
Log Message:
-----------
test/functional: Add test for boston-aia board
Add functional test for Boston AIA board. The P8700 RISC-V based
CPU by MIPS supports it at the moment.
Signed-off-by: Chao-ying Fu <[email protected]>
Signed-off-by: Djordje Todorovic <[email protected]>
Acked-by: Alistair Francis <[email protected]>
Reviewed-by: Thomas Huth <[email protected]>
Message-ID: <[email protected]>
Signed-off-by: Alistair Francis <[email protected]>
Commit: b254e486242466dad881fc2bbfa215f1b67cd30f
https://github.com/qemu/qemu/commit/b254e486242466dad881fc2bbfa215f1b67cd30f
Author: Richard Henderson <[email protected]>
Date: 2026-01-10 (Sat, 10 Jan 2026)
Changed paths:
M configs/devices/riscv64-softmmu/default.mak
M docs/specs/riscv-aia.rst
A docs/system/riscv/mips.rst
M docs/system/target-riscv.rst
M hw/core/loader.c
M hw/intc/riscv_aplic.c
M hw/misc/Kconfig
M hw/misc/meson.build
A hw/misc/riscv_cmgcr.c
A hw/misc/riscv_cpc.c
M hw/riscv/Kconfig
A hw/riscv/boston-aia.c
A hw/riscv/cps.c
M hw/riscv/meson.build
M hw/riscv/riscv-iommu.c
A include/hw/misc/riscv_cmgcr.h
A include/hw/misc/riscv_cpc.h
A include/hw/riscv/cps.h
M target/riscv/cpu-qom.h
M target/riscv/cpu.c
M target/riscv/cpu.h
M target/riscv/cpu_cfg.h
M target/riscv/cpu_cfg_fields.h.inc
M target/riscv/cpu_helper.c
M target/riscv/cpu_vendorid.h
M target/riscv/csr.c
M target/riscv/insn16.decode
M target/riscv/insn32.decode
A target/riscv/insn_trans/trans_rvzalasr.c.inc
A target/riscv/insn_trans/trans_xmips.c.inc
A target/riscv/insn_trans/trans_zilsd.c.inc
M target/riscv/machine.c
M target/riscv/meson.build
A target/riscv/mips_csr.c
M target/riscv/pmu.c
M target/riscv/tcg/tcg-cpu.c
M target/riscv/translate.c
A target/riscv/xmips.decode
M tests/functional/riscv64/meson.build
A tests/functional/riscv64/test_boston.py
M tests/functional/riscv64/test_sifive_u.py
Log Message:
-----------
Merge tag 'pull-riscv-to-apply-20260109' of
https://github.com/alistair23/qemu into staging
First RISC-V PR for 11.
* Remove unused import statement from sifive_u test
* Free allocated memory in core/loader
* Add all available CSRs to 'info registers'
* Add 'riscv-aia' accel prop info to documentation
* Fix IOMMU MemoryRegion owner
* Make riscv cpu.h target partially independent
* Expand AIA target[i] source handling and refactor related code
* Don't look up DDT cache in Off and Bare modes
* Add Zilsd and Zclsd extension support
* Add RISCV ZALASR extension
* Add support for MIPS P8700 CPU
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# gpg: Signature made Fri 09 Jan 2026 05:06:23 PM AEDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20260109' of https://github.com/alistair23/qemu: (34
commits)
test/functional: Add test for boston-aia board
riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
hw/riscv: Add support for MIPS Boston-aia board mode
hw/riscv: Add support for RISCV CPS
hw/misc: Add RISC-V CPC device implementation
hw/misc: Add RISC-V CMGCR device implementation
target/riscv: Add Xmipslsp instructions
target/riscv: Add mips.pref instruction
target/riscv: Add mips.ccmov instruction
target/riscv: Add MIPS P8700 CSRs
target/riscv: Add MIPS P8700 CPU
target/riscv: Add cpu_set_exception_base
Add RISCV ZALASR extension
target/riscv: Add Zilsd and Zclsd extension support
hw/riscv: riscv-iommu: Don't look up DDT cache in Off and Bare modes
hw/intc/riscv_aplic: Factor out source_active() and remove duplicate checks
hw/intc/riscv_aplic: Expand inactive source handling for AIA target[i]
target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val
target/riscv: Combine mhpmcounter and mhpmcounterh
target/riscv: Combine minstretcfg and minstretcfgh
...
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/146dcea03e27...b254e4862424
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