Branch: refs/heads/staging
Home: https://github.com/qemu/qemu
Commit: a508208eda9711c8779ce4fbab28c98999e628d6
https://github.com/qemu/qemu/commit/a508208eda9711c8779ce4fbab28c98999e628d6
Author: Jeuk Kim <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/ufs/ufs.c
Log Message:
-----------
hw/ufs: Ensure DBC of PRDT uses only lower 18 bits
The UFS spec defines the PRDT data byte count as an 18-bit field. This
commit masks the value to the lower 18 bits to prevent incorrect
transfer lengths and ensure compliance.
Signed-off-by: Jeuk Kim <[email protected]>
Commit: 6833aae1cfbbc83d8458ee1bba33ca4f71f71e55
https://github.com/qemu/qemu/commit/6833aae1cfbbc83d8458ee1bba33ca4f71f71e55
Author: Ilia Levi <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/ufs/ufs.c
M hw/ufs/ufs.h
Log Message:
-----------
hw/ufs: Fix mcq completion queue wraparound
Currently, ufs_mcq_process_cq() writes to the CQ without checking whether
there is available space. This can cause CQ entries to be discarded and
overwritten. The solution is to stop writing when CQ is full and exert
backpressure on the affected SQs. This is similar to how NVMe CQs operate.
Signed-off-by: Ilia Levi <[email protected]>
Reviewed-by: Jeuk Kim <[email protected]>
Signed-off-by: Jeuk Kim <[email protected]>
Commit: 0995e513c7c46412ccb5b11a2e71b9c7145997b0
https://github.com/qemu/qemu/commit/0995e513c7c46412ccb5b11a2e71b9c7145997b0
Author: Ilia Levi <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M tests/qtest/ufs-test.c
Log Message:
-----------
tests/qtest/ufs-test: Add test for mcq completion queue wraparound
Added a test that sends 32 NOP Out commands asynchronously. Since the CQ
has 31 entries by default, this tests the scenario where CQ processing
needs to wait for space to become available.
Additionally, added two minor fixes to existing tests:
* advance CQ head after reading from CQ
* initialize command descriptor slots bitmap in ufs_init()
Signed-off-by: Ilia Levi <[email protected]>
Acked-by: Fabiano Rosas <[email protected]>
Reviewed-by: Jeuk Kim <[email protected]>
Signed-off-by: Jeuk Kim <[email protected]>
Commit: 47de28a0b7fb96531271aaeaa3e7f2cad2b91221
https://github.com/qemu/qemu/commit/47de28a0b7fb96531271aaeaa3e7f2cad2b91221
Author: Xianglai Li <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/loongarch/virt-fdt-build.c
Log Message:
-----------
hw/loongarch/virt: Modify the interrupt trigger type in fdt table
In the loongarch virt fdt file, the interrupt trigger type directly
uses magic numbers. Now, refer to the definitions in the linux kernel and
use macro definitions.
Signed-off-by: Xianglai Li <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: ff54394eed148c642f83b45753c7898acdbd5ddb
https://github.com/qemu/qemu/commit/ff54394eed148c642f83b45753c7898acdbd5ddb
Author: Xianglai Li <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/loongarch/virt-fdt-build.c
Log Message:
-----------
hw/loongarch/virt: Fix irq allocation failure with pci device from fdt
When we use the -kernel parameter to start an elf format kernel relying on
fdt, we get the following error:
pcieport 0000:00:01.0: of_irq_parse_pci: failed with rc=-22
pcieport 0000:00:01.0: enabling device (0000 -> 0003)
pcieport 0000:00:01.0: PME: Signaling with IRQ 19
pcieport 0000:00:01.0: AER: enabled with IRQ 19
pcieport 0000:00:01.1: of_irq_parse_pci: failed with rc=-22
pcieport 0000:00:01.1: enabling device (0000 -> 0003)
pcieport 0000:00:01.1: PME: Signaling with IRQ 20
pcieport 0000:00:01.1: AER: enabled with IRQ 20
pcieport 0000:00:01.2: of_irq_parse_pci: failed with rc=-22
pcieport 0000:00:01.2: enabling device (0000 -> 0003)
pcieport 0000:00:01.2: PME: Signaling with IRQ 21
pcieport 0000:00:01.2: AER: enabled with IRQ 21
pcieport 0000:00:01.3: of_irq_parse_pci: failed with rc=-22
pcieport 0000:00:01.3: enabling device (0000 -> 0003)
pcieport 0000:00:01.3: PME: Signaling with IRQ 22
pcieport 0000:00:01.3: AER: enabled with IRQ 22
pcieport 0000:00:01.4: of_irq_parse_pci: failed with rc=-22
This is because the description of interrupt-cell is missing in the pcie
irq map. And there is a lack of a description of the interrupt trigger
type. Now it is corrected and the correct interrupt-cell is added in the
pcie irq map.
Refer to the implementation in arm and add some comments.
Signed-off-by: Xianglai Li <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 70cf9b7bf7aff47f8d85ccce35b688dd91335cf0
https://github.com/qemu/qemu/commit/70cf9b7bf7aff47f8d85ccce35b688dd91335cf0
Author: Song Gao <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
target/loongach: Fix some exceptions failure in updating CSR_BADV
According to Volume 1 Manual 7.4.8 ,exception,SYS,BRK,INE,IPE,PPD
FPE,SXD,ASXD are need't update CSR_BADV, this patch correct it.
Signed-off-by: Song Gao <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: e4f0ef58d53eb20056f9f3ca9f21dbbbf25f2530
https://github.com/qemu/qemu/commit/e4f0ef58d53eb20056f9f3ca9f21dbbbf25f2530
Author: Song Gao <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
target/loongarch: Fix exception BCE missing to update CSR_BADV
Exception BCE need update CSR_BADV, and the value is env->pc.
Signed-off-by: Song Gao <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: a7be2e0a3f7d0f35bcc3b17e2b558084efc5d9fe
https://github.com/qemu/qemu/commit/a7be2e0a3f7d0f35bcc3b17e2b558084efc5d9fe
Author: Song Gao <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
target/loongarch: Fix exception ADEF/ADEM missing to update CSR_BADV
Exception ADEM/ADEF need update CSR_BADV, the value from the virtual
address.
Signed-off-by: Song Gao <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 49ee001a5b8378e9a9b3db8cbf61e7eda970ecd2
https://github.com/qemu/qemu/commit/49ee001a5b8378e9a9b3db8cbf61e7eda970ecd2
Author: Yao Zi <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/loongarch/virt.c
Log Message:
-----------
hw/loongarch/virt: Don't abort on access to unimplemented IOCSR
Since commit f2e61edb2946 ("hw/loongarch/virt: Use MemTxAttrs interface
for misc ops") which adds a call to g_assert_not_reached() in the path
of handling unimplemented IOCSRs, QEMU would abort when the guest
accesses unimplemented IOCSRs.
This is too serious since there's nothing fatal happening in QEMU
itself, and the guest could probably continue running if we give zero as
result for these reads, which also matches the behavior observed on
3A5000M real machine.
Replace the assertion with qemu_log_mask(LOG_UNIMP, ...), it's still
possible to examine unimplemented IOCSR access through "-d unimp"
command line arguments.
Fixes: f2e61edb2946 ("hw/loongarch/virt: Use MemTxAttrs interface for misc ops")
Signed-off-by: Yao Zi <[email protected]>
Signed-off-by: Bibo Mao <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Reviewed-by: Bibo Mao <[email protected]>
Commit: 23cd2d933364610e5c0dcaf18561ab277f68d849
https://github.com/qemu/qemu/commit/23cd2d933364610e5c0dcaf18561ab277f68d849
Author: Richard Henderson <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/ufs/ufs.c
M hw/ufs/ufs.h
M tests/qtest/ufs-test.c
Log Message:
-----------
Merge tag 'pull-ufs-20260115' of https://gitlab.com/jeuk20.kim/qemu into
staging
ufs: MCQ fixes and tests
- Mask PRDT data byte count to 18 bits
- Fix MCQ completion queue wraparound
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# gpg: Signature made Thu 15 Jan 2026 03:49:28 PM AEDT
# gpg: using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602
# gpg: Good signature from "Jeuk Kim <[email protected]>" [unknown]
# gpg: aka "Jeuk Kim <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5017 D831 597C 78A3 D907 EEF7 12E2 204C 0E5D B602
* tag 'pull-ufs-20260115' of https://gitlab.com/jeuk20.kim/qemu:
tests/qtest/ufs-test: Add test for mcq completion queue wraparound
hw/ufs: Fix mcq completion queue wraparound
hw/ufs: Ensure DBC of PRDT uses only lower 18 bits
Signed-off-by: Richard Henderson <[email protected]>
Commit: 7e95274034065e4cd1d6afac4627e9211677899f
https://github.com/qemu/qemu/commit/7e95274034065e4cd1d6afac4627e9211677899f
Author: Richard Henderson <[email protected]>
Date: 2026-01-15 (Thu, 15 Jan 2026)
Changed paths:
M hw/loongarch/virt-fdt-build.c
M hw/loongarch/virt.c
M target/loongarch/tcg/tcg_cpu.c
Log Message:
-----------
Merge tag 'pull-loongarch-20260115' of https://github.com/bibo-mao/qemu into
staging
loongarch queue
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# gpg: Signature made Thu 15 Jan 2026 05:37:20 PM AEDT
# gpg: using EDDSA key 0D8642A3A2659F80B0B3D1A41F7B0C1251ACE7D1
# gpg: Good signature from "bibo mao <[email protected]>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 7044 3A00 19C0 E97A 31C7 13C4 8E86 8FB7 A176 9D4C
# Subkey fingerprint: 0D86 42A3 A265 9F80 B0B3 D1A4 1F7B 0C12 51AC E7D1
* tag 'pull-loongarch-20260115' of https://github.com/bibo-mao/qemu:
hw/loongarch/virt: Don't abort on access to unimplemented IOCSR
target/loongarch: Fix exception ADEF/ADEM missing to update CSR_BADV
target/loongarch: Fix exception BCE missing to update CSR_BADV
target/loongach: Fix some exceptions failure in updating CSR_BADV
hw/loongarch/virt: Fix irq allocation failure with pci device from fdt
hw/loongarch/virt: Modify the interrupt trigger type in fdt table
Signed-off-by: Richard Henderson <[email protected]>
Compare: https://github.com/qemu/qemu/compare/4cfa1ce0365f...7e9527403406
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