On Wed, Jul 24, 2024 at 11:08 PM Philippe Mathieu-Daudé
<phi...@linaro.org> wrote:
>
> The 'any' CPU is deprecated since commit f57d5f8004b
> ("target/riscv: deprecate the 'any' CPU type"). Users
> are better off using the default CPUs or the 'max' CPU.
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> docs/about/deprecated.rst | 13 -------------
> docs/about/removed-features.rst | 8 ++++++++
> target/riscv/cpu-qom.h | 1 -
> target/riscv/cpu.c | 28 ----------------------------
> 4 files changed, 8 insertions(+), 42 deletions(-)
>
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index 88f0f037865..0ac49b15b44 100644
> --- a/docs/about/deprecated.rst
> +++ b/docs/about/deprecated.rst
> @@ -347,19 +347,6 @@ QEMU's ``vhost`` feature, which would eliminate the high
> latency costs under
> which the 9p ``proxy`` backend currently suffers. However as of to date
> nobody
> has indicated plans for such kind of reimplementation unfortunately.
>
> -RISC-V 'any' CPU type ``-cpu any`` (since 8.2)
> -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> -
> -The 'any' CPU type was introduced back in 2018 and has been around since the
> -initial RISC-V QEMU port. Its usage has always been unclear: users don't know
> -what to expect from a CPU called 'any', and in fact the CPU does not do
> anything
> -special that isn't already done by the default CPUs rv32/rv64.
> -
> -After the introduction of the 'max' CPU type, RISC-V now has a good coverage
> -of generic CPUs: rv32 and rv64 as default CPUs and 'max' as a feature
> complete
> -CPU for both 32 and 64 bit builds. Users are then discouraged to use the
> 'any'
> -CPU type starting in 8.2.
> -
> RISC-V CPU properties which start with capital 'Z' (since 8.2)
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
>
> diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst
> index fc7b28e6373..f3e9474a73e 100644
> --- a/docs/about/removed-features.rst
> +++ b/docs/about/removed-features.rst
> @@ -850,6 +850,14 @@ The RISC-V no MMU cpus have been removed. The two CPUs:
> ``rv32imacu-nommu`` and
> ``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be
> specified
> via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs.
>
> +RISC-V 'any' CPU type ``-cpu any`` (removed in 9.1)
> +'''''''''''''''''''''''''''''''''''''''''''''''''''
> +
> +The 'any' CPU type was introduced back in 2018 and was around since the
> +initial RISC-V QEMU port. Its usage was always been unclear: users don't know
> +what to expect from a CPU called 'any', and in fact the CPU does not do
> anything
> +special that isn't already done by the default CPUs rv32/rv64.
> +
> ``compat`` property of server class POWER CPUs (removed in 6.0)
> '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
>
> diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
> index 3670cfe6d9a..4464c0fd7a3 100644
> --- a/target/riscv/cpu-qom.h
> +++ b/target/riscv/cpu-qom.h
> @@ -29,7 +29,6 @@
> #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
> #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
>
> -#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
> #define TYPE_RISCV_CPU_MAX RISCV_CPU_TYPE_NAME("max")
> #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
> #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a90808a3bac..4bda754b013 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -438,27 +438,6 @@ static void set_satp_mode_default_map(RISCVCPU *cpu)
> }
> #endif
>
> -static void riscv_any_cpu_init(Object *obj)
> -{
> - RISCVCPU *cpu = RISCV_CPU(obj);
> - CPURISCVState *env = &cpu->env;
> - riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
> -
> -#ifndef CONFIG_USER_ONLY
> - set_satp_mode_max_supported(RISCV_CPU(obj),
> - riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
> - VM_1_10_SV32 : VM_1_10_SV57);
> -#endif
> -
> - env->priv_ver = PRIV_VERSION_LATEST;
> -
> - /* inherited from parent obj via riscv_cpu_init() */
> - cpu->cfg.ext_zifencei = true;
> - cpu->cfg.ext_zicsr = true;
> - cpu->cfg.mmu = true;
> - cpu->cfg.pmp = true;
> -}
> -
> static void riscv_max_cpu_init(Object *obj)
> {
> RISCVCPU *cpu = RISCV_CPU(obj);
> @@ -1161,11 +1140,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error
> **errp)
> RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
> Error *local_err = NULL;
>
> - if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) {
> - warn_report("The 'any' CPU is deprecated and will be "
> - "removed in the future.");
> - }
> -
> cpu_exec_realizefn(cs, &local_err);
> if (local_err != NULL) {
> error_propagate(errp, local_err);
> @@ -2952,7 +2926,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> .abstract = true,
> },
> #if defined(TARGET_RISCV32)
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV32,
> riscv_any_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV32,
> riscv_max_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, MXL_RV32,
> rv32_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX, MXL_RV32,
> rv32_ibex_cpu_init),
> @@ -2962,7 +2935,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I, MXL_RV32,
> rv32i_bare_cpu_init),
> DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E, MXL_RV32,
> rv32e_bare_cpu_init),
> #elif defined(TARGET_RISCV64)
> - DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, MXL_RV64,
> riscv_any_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, MXL_RV64,
> riscv_max_cpu_init),
> DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, MXL_RV64,
> rv64_base_cpu_init),
> DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,
> rv64_sifive_e_cpu_init),
> --
> 2.45.2
>
>
