On Fri, 19 Jul 2024 16:29:25 +0000
Hendrik Wuethrich <whend...@google.com> wrote:
> From: Hendrik Wüthrich <whend...@google.com>
>
> Implement rdmsr and wrmsr for the following MSRs:
> * MSR_IA32_PQR_ASSOC
> * MSR_IA32_QM_EVTSEL
> * MSR_IA32_QM_CTR
> * IA32_L3_QOS_Mask_n
> * IA32_L2_QOS_Mask_n
> * IA32_L2_QoS_Ext_BW_Thrtl_n
>
> This allows for the guest to call RDT-internal functions to
> associate an RMID with a CLOSID / set an active RMID for
> monitoring, read monitoring data, and set classes of service.
>
> Signed-off-by: Hendrik Wüthrich <whend...@google.com>
A few comments inline. Mostly code cleanup stuff.
> ---
> hw/i386/rdt.c | 8 +++
> include/hw/i386/rdt.h | 8 ++-
> target/i386/cpu.h | 14 +++++
> target/i386/tcg/sysemu/misc_helper.c | 80 ++++++++++++++++++++++++++++
> 4 files changed, 109 insertions(+), 1 deletion(-)
>
> diff --git a/hw/i386/rdt.c b/hw/i386/rdt.c
> index 77b7b4f2d4..0d0e5751fc 100644
> --- a/hw/i386/rdt.c
> +++ b/hw/i386/rdt.c
> @@ -17,6 +17,10 @@
> #define MAX_L2_MASK_COUNT 48
> #define MAX_MBA_THRTL_COUNT 31
>
> +#define CPUID_10_1_EDX_COS_MAX MAX_L3_MASK_COUNT
> +#define CPUID_10_2_EDX_COS_MAX MAX_L2_MASK_COUNT
> +#define CPUID_10_3_EDX_COS_MAX MAX_MBA_THRTL_COUNT
Worth these defines? Seems easier to just use the MAX_L3...
etc
> +
> #define TYPE_RDT "rdt"
> #define RDT_NUM_RMID_PROP "rmids"
>
> @@ -57,6 +61,10 @@ struct RDTState {
>
> struct RDTStateClass { };
>
> +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void) { return
> CPUID_10_1_EDX_COS_MAX; }
> +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void) { return
> CPUID_10_2_EDX_COS_MAX; }
> +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void) { return
> CPUID_10_3_EDX_COS_MAX; }
> +
> bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc) {
> X86CPU *cpu = X86_CPU(current_cpu);
> RDTStateInstance *rdt = cpu->rdt;
> diff --git a/include/hw/i386/rdt.h b/include/hw/i386/rdt.h
> index 8092c5f290..51d36822f0 100644
> --- a/include/hw/i386/rdt.h
> +++ b/include/hw/i386/rdt.h
> @@ -9,7 +9,12 @@ typedef struct RDTStateInstance RDTStateInstance;
> typedef struct RDTMonitor RDTMonitor;
> typedef struct RDTAllocation RDTAllocation;
>
> -#endif
> +uint32_t rdt_get_cpuid_10_1_edx_cos_max(void);
> +
> +uint32_t rdt_get_cpuid_10_2_edx_cos_max(void);
> +
> +uint32_t rdt_get_cpuid_10_3_edx_cos_max(void);
No need for blank lines between these related function
definitions.
> +
> bool rdt_associate_rmid_cos(uint64_t msr_ia32_pqr_assoc);
>
> void rdt_write_msr_l3_mask(uint32_t pos, uint32_t val);
> @@ -23,3 +28,4 @@ uint32_t rdt_read_mba_thrtl(uint32_t pos);
> uint64_t rdt_read_event_count(RDTStateInstance *rdt, uint32_t rmid, uint32_t
> event_id);
> uint32_t rdt_max_rmid(RDTStateInstance *rdt);
>
> +#endif
Fix that in earlier patch not here.
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index bd0bbb75f2..0b3aca2d02 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -574,6 +574,17 @@ typedef enum X86Seg {
> #define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490
> #define MSR_IA32_VMX_VMFUNC 0x00000491
>
> +#define MSR_IA32_QM_EVTSEL 0x0c8d
> +#define MSR_IA32_QM_CTR 0x0c8e
> +#define MSR_IA32_PQR_ASSOC 0x0c8f
> +
> +#define MSR_IA32_L3_CBM_BASE 0x0c90
> +#define MSR_IA32_L3_MASKS_END 0x0d0f
> +#define MSR_IA32_L2_CBM_BASE 0x0d10
> +#define MSR_IA32_L2_CBM_END 0x0d4f
> +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE 0xd50
> +#define MSR_IA32_L2_QOS_Ext_BW_Thrtl_END 0xd80
> +
> #define MSR_APIC_START 0x00000800
> #define MSR_APIC_END 0x000008ff
>
> @@ -1778,6 +1789,9 @@ typedef struct CPUArchState {
> uint64_t msr_ia32_feature_control;
> uint64_t msr_ia32_sgxlepubkeyhash[4];
>
> + uint64_t msr_ia32_qm_evtsel;
> + uint64_t msr_ia32_pqr_assoc;
> +
> uint64_t msr_fixed_ctr_ctrl;
> uint64_t msr_global_ctrl;
> uint64_t msr_global_status;
> diff --git a/target/i386/tcg/sysemu/misc_helper.c
> b/target/i386/tcg/sysemu/misc_helper.c
> index 094aa56a20..e48e6b0da1 100644
> --- a/target/i386/tcg/sysemu/misc_helper.c
> +++ b/target/i386/tcg/sysemu/misc_helper.c
> @@ -25,6 +25,7 @@
> #include "exec/address-spaces.h"
> #include "exec/exec-all.h"
> #include "tcg/helper-tcg.h"
> +#include "hw/i386/rdt.h"
> #include "hw/i386/apic.h"
>
> void helper_outb(CPUX86State *env, uint32_t port, uint32_t data)
> @@ -293,6 +294,44 @@ void helper_wrmsr(CPUX86State *env)
> env->msr_bndcfgs = val;
> cpu_sync_bndcs_hflags(env);
> break;
> + case MSR_IA32_QM_EVTSEL:
> + env->msr_ia32_qm_evtsel = val;
> + break;
> + case MSR_IA32_PQR_ASSOC:
> + {
> + env->msr_ia32_pqr_assoc = val;
> + bool res = rdt_associate_rmid_cos(val);
QEMU tends to use traditional C style, so declare
variables at start of scope then blank line.
However...
> + if (!res)
> + goto error;
if (rdt_associate_rmid_cos(val)) {
goto error;
}
> + break;
> + }
Drop this scoping as bool will have gone away.
> + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
blank line
> + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) {
> + goto error;
> + }
> + rdt_write_msr_l3_mask(pos, val);
> + break;
> + }
> + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
blank line.
> + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) {
> + goto error;
> + }
> + rdt_write_msr_l2_mask(pos, val);
> + break;
> + }
> + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
> MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] -
> MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
blank line
> + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) {
> + goto error;
> + }
> + rdt_write_mba_thrtl(pos, val);
> + break;
> + }
> case MSR_APIC_START ... MSR_APIC_END: {
> int ret;
> int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
> @@ -472,6 +511,44 @@ void helper_rdmsr(CPUX86State *env)
> val = (cs->nr_threads * cs->nr_cores) | (cs->nr_cores << 16);
> break;
> }
> + case MSR_IA32_QM_CTR:
> + val = rdt_read_event_count(x86_cpu->rdt,
> + (env->msr_ia32_qm_evtsel >> 32) & 0xff,
> + env->msr_ia32_qm_evtsel & 0xff);
> + break;
> + case MSR_IA32_QM_EVTSEL:
> + val = env->msr_ia32_qm_evtsel;
> + break;
> + case MSR_IA32_PQR_ASSOC:
> + val = env->msr_ia32_pqr_assoc;
> + break;
> + case MSR_IA32_L3_CBM_BASE ... MSR_IA32_L3_MASKS_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L3_CBM_BASE;
blank line.
> + if (pos >= rdt_get_cpuid_10_1_edx_cos_max()) {
> + goto error;
> + }
> + val = rdt_read_l3_mask(pos);
> + break;
> + }
> + case MSR_IA32_L2_CBM_BASE ... MSR_IA32_L2_CBM_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] - MSR_IA32_L2_CBM_BASE;
blank line.
> + if (pos >= rdt_get_cpuid_10_2_edx_cos_max()) {
> + goto error;
> + }
> + val = rdt_read_l2_mask(pos);
> + break;
> + }
> + case MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE ...
> MSR_IA32_L2_QOS_Ext_BW_Thrtl_END:
> + {
> + uint32_t pos = (uint32_t)env->regs[R_ECX] -
> MSR_IA32_L2_QOS_Ext_BW_Thrtl_BASE;
blank line.
> + if (pos >= rdt_get_cpuid_10_3_edx_cos_max()) {
> + goto error;
> + }
> + val = rdt_read_mba_thrtl(pos);
> + break;
> + }
> case MSR_APIC_START ... MSR_APIC_END: {
> int ret;
> int index = (uint32_t)env->regs[R_ECX] - MSR_APIC_START;
> @@ -499,6 +576,9 @@ void helper_rdmsr(CPUX86State *env)
> }
> env->regs[R_EAX] = (uint32_t)(val);
> env->regs[R_EDX] = (uint32_t)(val >> 32);
> +return;
return;
fix the indent
blank line after the return.
> +error:
> + raise_exception_err_ra(env, EXCP0D_GPF, 0, GETPC());
If this is only thing to do in error path it might be easier
to just do that inline instead of goto.
> }
>
> void helper_flush_page(CPUX86State *env, target_ulong addr)
