On Fri, Jul 26, 2024 at 12:42 AM Alistair Francis <alistai...@gmail.com> wrote: > > On Wed, Jul 24, 2024 at 9:31 AM Atish Patra <ati...@rivosinc.com> wrote: > > > > From: Kaiwen Xue <kaiw...@rivosinc.com> > > > > This adds the properties for sxcsrind. Definitions of new registers and > > implementations will come with future patches. > > > > Signed-off-by: Atish Patra <ati...@rivosinc.com> > > Signed-off-by: Kaiwen Xue <kaiw...@rivosinc.com> > > --- > > target/riscv/cpu.c | 2 ++ > > target/riscv/cpu_cfg.h | 2 ++ > > 2 files changed, 4 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index a90808a3bace..ebc19090b40d 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -183,12 +183,14 @@ const RISCVIsaExtData isa_edata_arr[] = { > > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > > + ISA_EXT_DATA_ENTRY(smcsrind, PRIV_VERSION_1_12_0, ext_smcsrind), > > This is actually part of the unpriv spec, so it's a bit weird that it > depends on the priv spec. But that's how it's all set up. >
Smcsrind is part of priv spec[1]. Am I missing something ? https://drive.google.com/file/d/17GeetSnT5wW3xNuAHI95-SI1gPGd5sJ_/view > But shouldn't this be PRIV_VERSION_1_13_0? > Yes. Sorry I forgot about that. smcntrpmf should also be PRIV_VERSION_1_13_0. I will send a fix patch along with the v2 for assert fix. > Alistair