On Wed, Jul 24, 2024 at 9:32 AM Atish Patra <ati...@rivosinc.com> wrote:
>
> The dependant ISA features are enabled at the end of cpu_realize
> in finalize_features. Thus, PMU init should be invoked after that
> only. Move the init invocation to riscv_tcg_cpu_finalize_features.
>
> Signed-off-by: Atish Patra <ati...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 28 ++++++++++++++--------------
> 1 file changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index b8814ab753bd..d78d5960cf30 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -898,6 +898,20 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu,
> Error **errp)
> error_propagate(errp, local_err);
> return;
> }
> +#ifndef CONFIG_USER_ONLY
> + if (cpu->cfg.pmu_mask) {
> + riscv_pmu_init(cpu, &local_err);
> + if (local_err != NULL) {
> + error_propagate(errp, local_err);
> + return;
> + }
> +
> + if (cpu->cfg.ext_sscofpmf) {
> + cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> + riscv_pmu_timer_cb, cpu);
> + }
> + }
> +#endif
> }
>
> void riscv_tcg_cpu_finalize_dynamic_decoder(RISCVCPU *cpu)
> @@ -945,7 +959,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
> **errp)
>
> #ifndef CONFIG_USER_ONLY
> CPURISCVState *env = &cpu->env;
> - Error *local_err = NULL;
>
> tcg_cflags_set(CPU(cs), CF_PCREL);
>
> @@ -953,19 +966,6 @@ static bool riscv_tcg_cpu_realize(CPUState *cs, Error
> **errp)
> riscv_timer_init(cpu);
> }
>
> - if (cpu->cfg.pmu_mask) {
> - riscv_pmu_init(cpu, &local_err);
> - if (local_err != NULL) {
> - error_propagate(errp, local_err);
> - return false;
> - }
> -
> - if (cpu->cfg.ext_sscofpmf) {
> - cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
> - riscv_pmu_timer_cb, cpu);
> - }
> - }
> -
> /* With H-Ext, VSSIP, VSTIP, VSEIP and SGEIP are hardwired to one. */
> if (riscv_has_ext(env, RVH)) {
> env->mideleg = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP | MIP_SGEIP;
>
> --
> 2.34.1
>
>
