Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org> --- target/arm/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 19191c23918..2bb87a9299f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -122,6 +122,11 @@ void arm_restore_state_to_opc(CPUState *cs, } #endif /* CONFIG_TCG */ +static bool arm_cpu_is_big_endian(CPUState *cs) +{ + return arm_cpu_data_is_big_endian(cpu_env(cs)); +} + /* * With SCTLR_ELx.NMI == 0, IRQ with Superpriority is masked identically with * IRQ without Superpriority. Moreover, if the GIC is configured so that @@ -2692,6 +2697,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) &acc->parent_phases); cc->class_by_name = arm_cpu_class_by_name; + cc->is_big_endian = arm_cpu_is_big_endian; cc->has_work = arm_cpu_has_work; cc->mmu_index = arm_cpu_mmu_index; cc->dump_state = arm_cpu_dump_state; -- 2.45.2