I guess you'd really want to simulate multiple CPUs with multiple host
threads. One of the additional problems could then be memory/cache coherency.
I'm not sure how much of a problem this would be in practice. If both host
and guest require the same (or no) explicit SMP memory barriert it's not a
problem. It the guest has stronger coherency requirements than the host we
have a problem.
Sparc32 architecure requires flushes and atomic instructions in critical code in Total Store Ordering mode. There is also higher performance mode requiring memory barriers called Partial Store Ordering, but I think Linux doesn't enable it.
> For some reason, Sparc performance is low (1/10 of native x86 nbench)
> compared to x86 (2/3). Simulating SMP on a uniprocessor would only decrease
> performance.
It think x86-on-x86 user-mode uses code-copying by default. ie. it runs a lot
of the the code unmodified. In my experience i386-softmmu is generally 10-15x
slower than native, and arm-user is 5-10x slower.
Good point. With -no-code-copy I get about 1/6 of native nbench in x86-x86, comparable to Sparc figure.
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