CVSROOT: /sources/qemu Module name: qemu Changes by: Fabrice Bellard <bellard> 06/06/14 17:32:25
Modified files: . : Makefile Makefile.target cpu-exec.c dyngen-exec.h dyngen.c dyngen.h vl.c fpu : softfloat-native.c target-mips : cpu.h Log message: Solaris/SPARC host port (Ben Taylor) CVSWeb URLs: http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile?cvsroot=qemu&r1=1.103&r2=1.104 http://cvs.savannah.gnu.org/viewcvs/qemu/Makefile.target?cvsroot=qemu&r1=1.114&r2=1.115 http://cvs.savannah.gnu.org/viewcvs/qemu/cpu-exec.c?cvsroot=qemu&r1=1.79&r2=1.80 http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen-exec.h?cvsroot=qemu&r1=1.27&r2=1.28 http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen.c?cvsroot=qemu&r1=1.43&r2=1.44 http://cvs.savannah.gnu.org/viewcvs/qemu/dyngen.h?cvsroot=qemu&r1=1.10&r2=1.11 http://cvs.savannah.gnu.org/viewcvs/qemu/vl.c?cvsroot=qemu&r1=1.188&r2=1.189 http://cvs.savannah.gnu.org/viewcvs/qemu/fpu/softfloat-native.c?cvsroot=qemu&r1=1.3&r2=1.4 http://cvs.savannah.gnu.org/viewcvs/qemu/target-mips/cpu.h?cvsroot=qemu&r1=1.9&r2=1.10 Patches: Index: Makefile =================================================================== RCS file: /sources/qemu/qemu/Makefile,v retrieving revision 1.103 retrieving revision 1.104 diff -u -b -r1.103 -r1.104 --- Makefile 14 Jun 2006 12:36:31 -0000 1.103 +++ Makefile 14 Jun 2006 17:32:25 -0000 1.104 @@ -9,6 +9,9 @@ ifdef CONFIG_DARWIN CFLAGS+= -mdynamic-no-pic endif +ifeq ($(ARCH),sparc) +CFLAGS+=-mcpu=ultrasparc +endif LDFLAGS=-g LIBS= DEFINES+=-D_GNU_SOURCE -D_FILE_OFFSET_BITS=64 -D_LARGEFILE_SOURCE Index: Makefile.target =================================================================== RCS file: /sources/qemu/qemu/Makefile.target,v retrieving revision 1.114 retrieving revision 1.115 diff -u -b -r1.114 -r1.115 --- Makefile.target 11 Jun 2006 13:32:58 -0000 1.114 +++ Makefile.target 14 Jun 2006 17:32:25 -0000 1.115 @@ -102,6 +102,11 @@ endif ifeq ($(ARCH),sparc) +ifeq ($(CONFIG_SOLARIS),yes) +CFLAGS+=-mcpu=ultrasparc -m32 -ffixed-g2 -ffixed-g3 +LDFLAGS+=-m32 +OP_CFLAGS=$(CFLAGS) -fno-delayed-branch -fno-omit-frame-pointer -ffixed-i0 +else CFLAGS+=-m32 -ffixed-g1 -ffixed-g2 -ffixed-g3 -ffixed-g6 LDFLAGS+=-m32 OP_CFLAGS=$(CFLAGS) -fno-delayed-branch -ffixed-i0 @@ -109,6 +114,7 @@ # -static is used to avoid g1/g3 usage by the dynamic linker LDFLAGS+=-Wl,-T,$(SRC_PATH)/sparc.ld -static endif +endif ifeq ($(ARCH),sparc64) CFLAGS+=-m64 -ffixed-g1 -ffixed-g2 -ffixed-g3 -ffixed-g6 Index: cpu-exec.c =================================================================== RCS file: /sources/qemu/qemu/cpu-exec.c,v retrieving revision 1.79 retrieving revision 1.80 diff -u -b -r1.79 -r1.80 --- cpu-exec.c 22 May 2006 22:03:52 -0000 1.79 +++ cpu-exec.c 14 Jun 2006 17:32:25 -0000 1.80 @@ -253,7 +253,7 @@ uint32_t *saved_regwptr; #endif #endif -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) int saved_i7, tmp_T0; #endif int ret, interrupt_request; @@ -323,7 +323,7 @@ #if defined(reg_T2) saved_T2 = T2; #endif -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) /* we also save i7 because longjmp may not restore it */ asm volatile ("mov %%i7, %0" : "=r" (saved_i7)); #endif @@ -447,7 +447,7 @@ T0 = 0; /* force lookup of first TB */ for(;;) { -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) /* g1 can be modified by some libc? functions */ tmp_T0 = T0; #endif @@ -467,7 +467,7 @@ do_interrupt(intno, 0, 0, 0, 1); /* ensure that no TB jump will be modified as the program flow was changed */ -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -486,7 +486,7 @@ env->error_code = 0; do_interrupt(env); env->interrupt_request &= ~CPU_INTERRUPT_HARD; -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -497,7 +497,7 @@ env->error_code = 0; do_interrupt(env); env->interrupt_request &= ~CPU_INTERRUPT_TIMER; -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -516,7 +516,7 @@ env->error_code = 0; do_interrupt(env); env->interrupt_request &= ~CPU_INTERRUPT_HARD; -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -534,7 +534,7 @@ env->interrupt_request &= ~CPU_INTERRUPT_HARD; do_interrupt(env->interrupt_index); env->interrupt_index = 0; -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -567,7 +567,7 @@ env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as the program flow was changed */ -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) tmp_T0 = 0; #else T0 = 0; @@ -635,7 +635,7 @@ lookup_symbol(tb->pc)); } #endif -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) T0 = tmp_T0; #endif /* see if we can patch the calling TB. When the TB @@ -671,7 +671,9 @@ "mov %%o7,%%i0" : /* no outputs */ : "r" (gen_func) - : "i0", "i1", "i2", "i3", "i4", "i5"); + : "i0", "i1", "i2", "i3", "i4", "i5", + "l0", "l1", "l2", "l3", "l4", "l5", + "l6", "l7"); #elif defined(__arm__) asm volatile ("mov pc, %0\n\t" ".global exec_loop\n\t" @@ -836,7 +838,7 @@ #else #error unsupported target CPU #endif -#ifdef __sparc__ +#if defined(__sparc__) && !defined(HOST_SOLARIS) asm volatile ("mov %0, %%i7" : : "r" (saved_i7)); #endif T0 = saved_T0; Index: dyngen-exec.h =================================================================== RCS file: /sources/qemu/qemu/dyngen-exec.h,v retrieving revision 1.27 retrieving revision 1.28 diff -u -b -r1.27 -r1.28 --- dyngen-exec.h 25 Apr 2006 22:36:06 -0000 1.27 +++ dyngen-exec.h 14 Jun 2006 17:32:25 -0000 1.28 @@ -121,6 +121,13 @@ #define AREG3 "s2" #endif #ifdef __sparc__ +#ifdef HOST_SOLARIS +#define AREG0 "g2" +#define AREG1 "g3" +#define AREG2 "g4" +#define AREG3 "g5" +#define AREG4 "g6" +#else #define AREG0 "g6" #define AREG1 "g1" #define AREG2 "g2" @@ -133,6 +140,7 @@ #define AREG9 "l5" #define AREG10 "l6" #define AREG11 "l7" +#endif #define USE_FP_CONVERT #endif #ifdef __s390__ @@ -241,10 +249,8 @@ ASM_NAME(__op_gen_label) #n) #endif #ifdef __sparc__ -#define EXIT_TB() asm volatile ("jmpl %i0 + 8, %g0\n" \ - "nop") -#define GOTO_LABEL_PARAM(n) asm volatile ( \ - "set " ASM_NAME(__op_gen_label) #n ", %g1; jmp %g1; nop") +#define EXIT_TB() asm volatile ("jmpl %i0 + 8, %g0; nop") +#define GOTO_LABEL_PARAM(n) asm volatile ("ba " ASM_NAME(__op_gen_label) #n ";nop") #endif #ifdef __arm__ #define EXIT_TB() asm volatile ("b exec_loop") Index: dyngen.c =================================================================== RCS file: /sources/qemu/qemu/dyngen.c,v retrieving revision 1.43 retrieving revision 1.44 diff -u -b -r1.43 -r1.44 --- dyngen.c 14 Jun 2006 13:41:08 -0000 1.43 +++ dyngen.c 14 Jun 2006 17:32:25 -0000 1.44 @@ -1440,6 +1440,12 @@ } #elif defined(HOST_SPARC) { +#define INSN_SAVE 0x9de3a000 +#define INSN_RET 0x81c7e008 +#define INSN_RESTORE 0x81e80000 +#define INSN_RETURN 0x81cfe008 +#define INSN_NOP 0x01000000 + uint32_t start_insn, end_insn1, end_insn2; uint8_t *p; p = (void *)(p_end - 8); @@ -1448,12 +1454,17 @@ start_insn = get32((uint32_t *)(p_start + 0x0)); end_insn1 = get32((uint32_t *)(p + 0x0)); end_insn2 = get32((uint32_t *)(p + 0x4)); - if ((start_insn & ~0x1fff) == 0x9de3a000) { + if ((start_insn & ~0x1fff) == INSN_SAVE) { p_start += 0x4; start_offset += 0x4; if ((int)(start_insn | ~0x1fff) < -128) error("Found bogus save at the start of %s", name); - if (end_insn1 != 0x81c7e008 || end_insn2 != 0x81e80000) + if (end_insn1 == INSN_RET && end_insn2 == INSN_RESTORE) + /* SPARC v7: ret; restore; */ ; + else if (end_insn1 == INSN_RETURN && end_insn2 == INSN_NOP) + /* SPARC v9: return; nop; */ ; + else + error("ret; restore; not found at end of %s", name); } else { error("No save at the beginning of %s", name); @@ -1462,7 +1473,7 @@ /* Skip a preceeding nop, if present. */ if (p > p_start) { skip_insn = get32((uint32_t *)(p - 0x4)); - if (skip_insn == 0x01000000) + if (skip_insn == INSN_NOP) p -= 4; } #endif @@ -2151,6 +2162,18 @@ reloc_offset, reloc_offset, name, addend, reloc_offset); break; + case R_SPARC_WDISP22: + fprintf(outfile, + " *(uint32_t *)(gen_code_ptr + %d) = " + "((*(uint32_t *)(gen_code_ptr + %d)) " + " & ~0x3fffff) " + " | ((((%s + %d) - (long)(gen_code_ptr + %d))>>2) " + " & 0x3fffff);\n", + rel->r_offset - start_offset, + rel->r_offset - start_offset, + name, addend, + rel->r_offset - start_offset); + break; default: error("unsupported sparc relocation (%d)", type); } Index: dyngen.h =================================================================== RCS file: /sources/qemu/qemu/dyngen.h,v retrieving revision 1.10 retrieving revision 1.11 diff -u -b -r1.10 -r1.11 --- dyngen.h 24 Apr 2006 20:32:17 -0000 1.10 +++ dyngen.h 14 Jun 2006 17:32:25 -0000 1.11 @@ -19,7 +19,13 @@ */ int __op_param1, __op_param2, __op_param3; -int __op_gen_label1, __op_gen_label2, __op_gen_label3; +#ifdef __sparc__ + void __op_gen_label1(){} + void __op_gen_label2(){} + void __op_gen_label3(){} +#else + int __op_gen_label1, __op_gen_label2, __op_gen_label3; +#endif int __op_jmp0, __op_jmp1, __op_jmp2, __op_jmp3; #ifdef __i386__ Index: vl.c =================================================================== RCS file: /sources/qemu/qemu/vl.c,v retrieving revision 1.188 retrieving revision 1.189 diff -u -b -r1.188 -r1.189 --- vl.c 14 Jun 2006 16:03:05 -0000 1.188 +++ vl.c 14 Jun 2006 17:32:25 -0000 1.189 @@ -563,6 +563,28 @@ return val; } +#elif defined(__sparc__) && defined(HOST_SOLARIS) + +uint64_t cpu_get_real_ticks (void) +{ +#if defined(_LP64) + uint64_t rval; + asm volatile("rd %%tick,%0" : "=r"(rval)); + return rval; +#else + union { + uint64_t i64; + struct { + uint32_t high; + uint32_t low; + } i32; + } rval; + asm volatile("rd %%tick,%1; srlx %1,32,%0" + : "=r"(rval.i32.high), "=r"(rval.i32.low)); + return rval.i64; +#endif +} + #else #error unsupported CPU #endif Index: fpu/softfloat-native.c =================================================================== RCS file: /sources/qemu/qemu/fpu/softfloat-native.c,v retrieving revision 1.3 retrieving revision 1.4 diff -u -b -r1.3 -r1.4 --- fpu/softfloat-native.c 23 Apr 2006 22:59:41 -0000 1.3 +++ fpu/softfloat-native.c 14 Jun 2006 17:32:25 -0000 1.4 @@ -6,7 +6,7 @@ void set_float_rounding_mode(int val STATUS_PARAM) { STATUS(float_rounding_mode) = val; -#if defined(_BSD) && !defined(__APPLE__) +#if defined(_BSD) && !defined(__APPLE__) || (defined(HOST_SOLARIS) && HOST_SOLARIS < 10) fpsetround(val); #elif defined(__arm__) /* nothing to do */ @@ -22,9 +22,14 @@ } #endif -#if defined(_BSD) -#define lrint(d) ((long)rint(d)) -#define llrint(d) ((long long)rint(d)) +#if defined(_BSD) || (defined(HOST_SOLARIS) && HOST_SOLARIS < 10) +#define lrint(d) ((int32_t)rint(d)) +#define llrint(d) ((int64_t)rint(d)) +#define lrintf(f) ((int32_t)rint(f)) +#define llrintf(f) ((int64_t)rint(f)) +#define sqrtf(f) ((float)sqrt(f)) +#define remainderf(fa, fb) ((float)remainder(fa, fb)) +#define rintf(f) ((float)rint(f)) #endif #if defined(__powerpc__) Index: target-mips/cpu.h =================================================================== RCS file: /sources/qemu/qemu/target-mips/cpu.h,v retrieving revision 1.9 retrieving revision 1.10 diff -u -b -r1.9 -r1.10 --- target-mips/cpu.h 14 Jun 2006 17:15:19 -0000 1.9 +++ target-mips/cpu.h 14 Jun 2006 17:32:25 -0000 1.10 @@ -8,6 +8,13 @@ #include "cpu-defs.h" #include "softfloat.h" +// uint_fast8_t and uint_fast16_t not in <sys/int_types.h> +// XXX: move that elsewhere +#if defined(HOST_SOLARIS) && SOLARISREV < 10 +typedef unsigned char uint_fast8_t; +typedef unsigned int uint_fast16_t; +#endif + typedef union fpr_t fpr_t; union fpr_t { float64 fd; /* ieee double precision */ _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel