Laurent DESNOGUES wrote:
On top of that try to find a specification for data
side behaviour, these beasts are not documented for
two reasons:
- they are heavily optimized and so not easily
described
- they often define the efficiency of a CPU and
so are considered as secret.
That might be the hardest part. Simulating any level of caches should
not be _that_ hard. (And a write or store buffer looks just exactly like
yet another cache).
Simulating branch prediction seems more complex to me (probably because
I'm thinking x86, not ARM).
Branch prediction has become very complex on ARM
but not as much as data side.
Sorry, I meant to refer to the pipeline, which is significantly shorter
on ARM than on the NetBurst CPUs from Intel... :-)
Thank you for your help.
Markus
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