Paul Brook a écrit :
Replacing the pregenerated blocks with hand written assembly isn't feasible.
Each target has its own set of ops, and each host would need its own assembly
implementation of those ops. Multiply 11 targets by 11 hosts and you get a
unmaintainable mess :-)
Shouldn't you have 11+11 and not 11*11, given your intermediate
representation? And of these 11+11, 11 have to be written
anyway (target). Or did I miss something?
On RISC targets like ARM most instructions don't set the condition codes, so
we don't bother doing this.
Except for ARM Thumb ISA which always sets flags. ARM is a bad
RISC example :)
I was wondering if you did some profiling to know how much time
is spent in disas_arm_insn. Of course the profiling results
would be very different for a Linux boot or a synthetic benchmark
(which makes me think that you don't support MMU, do you?).
There is a very nice trick to speed up decoding of ARM
instructions: pick up bits 20-27 and 4-7 and you (almost) get
one instruction per case entry; of course this means using a
generator to write the 4096 entries, but the result was good for
my interpreted ISS, reaching 44 M i/s on an Opteron @2.4GHz
without any compiler dependent trick (such as gcc jump to labels).
Laurent
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