> > Other targets have a hardware managed TLB. On a hardware managed TLB the > > OS treats it as if it were infinite size, and invalidation only occurs > > when a OS changes the mappings. On a software managed TLB "flushes" are > > more likely to occur during normal operation as TLB slots are reused. > > The excessive flushing for mips happens because Qemu doesn't properly > model the hardware's ASID handling.
Are you sure? IIUC changing the ASID causes a full qemu TLB flush. The code we're tweaking here is for single page flush. Actually that gives me an idea. When a TLB entry with a different ASID gets evicted we currently flush that page. This should be a no-op because we already did a full flush when the ASID changed. The other explanation is that the gest OS is manually doing a full TLB flush by manually evicting all the TLB entries. I'd hope that a sane guest OS would only do that as a last resort though. Paul _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
