"Aurelien Jarno" <[EMAIL PROTECTED]> wrote:
Then after playing with the current code, I am sure we are missing a simple interrupt controller for the MIPS CPU. It supports 6 hardware interrupts (IP2 to IP7) and we are using two of them in the current emulation: one for the i8259a and the other for the timer. In both case the current code assert and deassert a CPU_INTERRUPT_HARD.
The Galileo GT64xxx chip contains an interrupt controller too (for DMA cycle indication, built-in Timers e.t.c.). All this interrupt controllers are daisy-chained: i8259(as part of the PIIX + PCI), GT64xxx and MIPS internal. P.S. It should be good to have a well-defined modular IRQ routing architecture in the Qemu. Moreover, modern ix86 LAPIC/APIC interrupt controller even more complicated. -- -=AV=- _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
