On Friday 16 March 2007 22:06, andrzej zaborowski wrote: > This patch contains some ugly but very useful chnages: > - in cpu-exec.c, halt the arm CPU on CPU_INTERRUPT_HALT like in other > architectures.
This is ok. Though I'd prefer it to actually be common code (like CPU_INTERRUPT_DEBUG). > - wake the cpu up on CPU_INTERRUPT_EXITTB - this serves waking the > CPU up without asserting IRQ or FIQ, which is possible on PXA. Would > it be better to add a separate interrupt type instead? I think this is probably ok. Could do with a comment somewhere saying so. > - in target-arm/translate.c, don't terminate the TB after a CP15 > write. The purpose of this is to imitate the real processor's > instruction cache (to some degree). OSes should never need rely on the > cache prefetch but unfortunately Linux for pxa does when it's waking > up from sleep or deep idle, when enabling the MMU (simplifies things a > lot for Linux). This is not acceptable in its current form. IIRC on arm cores the effects take effect once all insn have worked through the pipeline (typically a few cycles), and I bet there's code that relies on this. ie: mcr cp15, ...;nop;nop;nop;nop;@expect cp15 write to have taken effect by now A more acceptable solution would be: - Only extend the TB for the specific instruction that linux abuses - Limit the number of instructions that can follow before the end of the TB. - Add a comment saying what this hack is for. Paul _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel
