Hi,
here is the patch which adds a "4KEcR1" CPU (a 4KEc, processor revision 2.2,
with MIPS32 Release 1 (!) instruction set is the heart of the AR7 SoC).
See also include/asm-mips/cpu.h in the Linux kernel sources:
./include/asm-mips/cpu.h:#define PRID_IMP_4KEC 0x8400
./include/asm-mips/cpu.h:#define PRID_IMP_4KECR2 0x9000
Stefan
PS. Did anybody run my branch test code on other MIPS CPUs?
What was the result?
Sorry, because of trouble with the Savannah CVS server, the patch is not
against CVS.
--- ../branches/head/target-mips/translate_init.c 2007-03-18
01:30:29.000000000 +0100
+++ target-mips/translate_init.c 2007-03-20 18:47:59.000000000 +0100
@@ -44,6 +44,12 @@
.CP0_Config1 = MIPS_CONFIG1,
},
{
+ .name = "4KEcR1",
+ .CP0_PRid = 0x00018448,
+ .CP0_Config0 = MIPS_CONFIG0,
+ .CP0_Config1 = MIPS_CONFIG1,
+ },
+ {
.name = "24Kf",
.CP0_PRid = 0x00019300,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR),
Thiemo Seufer schrieb:
> Thiemo Seufer wrote:
> [snip]
> I committed something which cover the rest of your patch, and throws
> now a RI exception for branch-in-branch-delay-slot.
>
> For the AR7 case, could you
> - add AR7 as a CPU type
> - handle the interesting cases for AR7 only, after verifying the
> cornercase behaviour of qemu and real hardware is consistent.
>
> The cornercases which come to mind:
> - conditional vs. unconditional branches
> - the various condition types
> - taken vs. non-taken branches
> - linked vs. non-linked branches
> - likely vs. non-likely branches
> - the side effects of j / jal in the delayslot
> - the value of PC/ra (if it changes)
>
> I don't ask for an exhaustive analysis, I just want to see the cases of
> interest covered, so we can be reasonably sure the qemu results will be
> useful for other AR7 users as well.
>
>
> Thiemo
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