The TCG emulation implements all the extensions described in the RVA22U64 profile, both mandatory and optional. The mandatory extensions will be enabled via the profile flag. We'll leave the optional extensions to be enabled by hand.
Given that this is the first profile we're implementing in TCG we'll need some ground work first: - all profiles declared in riscv_profiles[] will be exposed to users. TCG is the main accelerator we're considering when adding profile support in QEMU, so for now it's safe to assume that all profiles in riscv_profiles[] will be relevant to TCG; - we'll not support user profile settings for vendor CPUs. The flags will still be exposed but users won't be able to change them. The idea is that vendor CPUs in the future can enable profiles internally in their cpu_init() functions, showing to the external world that the CPU supports a certain profile. But users won't be able to enable/disable it; - Setting a profile to 'true' means 'enable all mandatory extensions of this profile, setting it to 'false' means disabling all its mandatory extensions. Disabling a profile is discouraged for regular use and will issue an user warning. User choices for individual extensions will take precedence, i.e. enabling a profile will not enable extensions that the user set to 'false', and vice-versa. This will make us independent of left-to-right ordering in the QEMU command line, i.e. the following QEMU command lines: -cpu rv64,zicbom=false,rva22u64=true,Zifencei=false -cpu rv64,zicbom=false,Zifencei=false,rva22u64=true -cpu rv64,rva22u64=true,zicbom=false,Zifencei=false They mean the same thing: "enable all mandatory extensions of the rva22u64 profile while keeping zicbom and Zifencei disabled". For now we'll handle multi-letter extensions only. MISA extensions need additional steps that we'll take care later. Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> --- target/riscv/tcg/tcg-cpu.c | 59 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 7a4400e2ba..3dd4783191 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -757,6 +757,63 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj) } } +static void cpu_set_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile = opaque; + RISCVCPU *cpu = RISCV_CPU(obj); + bool value; + int i, ext_offset; + + if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) == NULL) { + error_setg(errp, "Profile %s only available for generic CPUs", + profile->name); + return; + } + + if (!visit_type_bool(v, name, &value, errp)) { + return; + } + + if (!value) { + warn_report("Disabling the '%s' profile is a debug/development " + "tool, not recommended for regular use", + profile->name); + } + + profile->enabled = value; + + for (i = 0; profile->ext_offsets[i] != RISCV_PROFILE_EXT_LIST_END; i++) { + ext_offset = profile->ext_offsets[i]; + + if (cpu_cfg_ext_is_user_set(ext_offset)) { + continue; + } + + isa_ext_update_enabled(cpu, ext_offset, profile->enabled); + } +} + +static void cpu_get_profile(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVCPUProfile *profile = opaque; + bool value = profile->enabled; + + visit_type_bool(v, name, &value, errp); +} + +static void riscv_cpu_add_profiles(Object *cpu_obj) +{ + for (int i = 0; riscv_profiles[i] != NULL; i++) { + const RISCVCPUProfile *profile = riscv_profiles[i]; + + object_property_add(cpu_obj, profile->name, "bool", + cpu_get_profile, cpu_set_profile, + NULL, (void *)profile); + } +} + static bool cpu_ext_is_deprecated(const char *ext_name) { return isupper(ext_name[0]); @@ -880,6 +937,8 @@ static void riscv_cpu_add_user_properties(Object *obj) riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_deprecated_exts); + riscv_cpu_add_profiles(obj); + for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { qdev_property_add_static(DEVICE(obj), prop); } -- 2.41.0