Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/insns.decode | 2 ++
target/sparc/helper.c | 4 ---
target/sparc/translate.c | 55 ++++++++++++++++++---------------------
3 files changed, 28 insertions(+), 33 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 94a85e488a..74bf3760e9 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -173,6 +173,8 @@ SMUL 10 ..... 0.1011 ..... . .............
@r_r_ri_cc
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri_cc0
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri_cc0
+UDIV 10 ..... 0.1110 ..... . ............. @r_r_ri_cc
+SDIV 10 ..... 0.1111 ..... . ............. @r_r_ri_cc
Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5
{
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index c4358bba84..e25fdaeedd 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -102,9 +102,7 @@ static target_ulong do_udiv(CPUSPARCState *env,
target_ulong a,
}
if (cc) {
- env->cc_dst = x0;
env->cc_src2 = overflow;
- env->cc_op = CC_OP_DIV;
}
return x0;
}
@@ -143,9 +141,7 @@ static target_ulong do_sdiv(CPUSPARCState *env,
target_ulong a,
}
if (cc) {
- env->cc_dst = x0;
env->cc_src2 = overflow;
- env->cc_op = CC_OP_DIV;
}
return x0;
}
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index d0b570eb08..e8d904d565 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -697,6 +697,26 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
gen_helper_sdivx(dst, tcg_env, src1, src2);
}
+static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_udiv(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_sdiv(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_udiv_cc(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
+}
+
// 1
static void gen_op_eval_ba(TCGv dst)
{
@@ -2911,6 +2931,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1,
TCGv s2)
# define avail_64(C) false
#endif
#define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
+#define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
#define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
#define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
#define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
@@ -4206,6 +4227,10 @@ TRANS(UMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_umul,
NULL)
TRANS(SMUL, MUL, do_arith, a, CC_OP_LOGIC, gen_op_smul, NULL)
TRANS(UDIVX, 64, do_arith, a, 0, gen_op_udivx, NULL)
TRANS(SDIVX, 64, do_arith, a, 0, gen_op_sdivx, NULL)
+TRANS(UDIV, DIV, do_arith, a, CC_OP_DIV,
+ a->cc ? gen_op_udivcc : gen_op_udiv, NULL)
+TRANS(SDIV, DIV, do_arith, a, CC_OP_DIV,
+ a->cc ? gen_op_sdivcc : gen_op_sdiv, NULL)
static bool trans_OR(DisasContext *dc, arg_r_r_ri_cc *a)
{
@@ -4725,35 +4750,7 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
#endif
} else if (xop < 0x36) {
if (xop < 0x20) {
- cpu_src1 = get_src1(dc, insn);
- cpu_src2 = get_src2(dc, insn);
- switch (xop & ~0x10) {
- case 0xe: /* udiv */
- CHECK_IU_FEATURE(dc, DIV);
- if (xop & 0x10) {
- gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- dc->cc_op = CC_OP_DIV;
- } else {
- gen_helper_udiv(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- }
- break;
- case 0xf: /* sdiv */
- CHECK_IU_FEATURE(dc, DIV);
- if (xop & 0x10) {
- gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- dc->cc_op = CC_OP_DIV;
- } else {
- gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- }
- break;
- default:
- goto illegal_insn;
- }
- gen_store_gpr(dc, rd, cpu_dst);
+ goto illegal_insn;
} else {
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
--
2.34.1
