Remove gen_swap_asi.
Rename gen_swap_asi0 to gen_swap_asi.
Merge gen_swap into gen_swap_asi.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
---
target/sparc/insns.decode | 4 +++
target/sparc/translate.c | 58 +++++++++++++++++----------------------
2 files changed, 29 insertions(+), 33 deletions(-)
diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode
index 818ac33f2f..f3d02a3564 100644
--- a/target/sparc/insns.decode
+++ b/target/sparc/insns.decode
@@ -288,6 +288,10 @@ LDSTUB 11 ..... 001101 ..... . .............
@r_r_ri_na
LDSTUB 11 ..... 011101 ..... . ............. @r_r_r_asi # LDSTUBA
LDSTUB 11 ..... 011101 ..... . ............. @r_r_i_asi # LDSTUBA
+SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na
+SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA
+SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA
+
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 70d0ed3db3..2dd50a38f2 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -1884,13 +1884,6 @@ static void gen_ne_fop_QD(DisasContext *dc, int rd, int
rs,
gen_update_fprs_dirty(dc, QFPREG(rd));
}
-static void gen_swap(DisasContext *dc, TCGv dst, TCGv src,
- TCGv addr, int mmu_idx, MemOp memop)
-{
- gen_address_mask(dc, addr);
- tcg_gen_atomic_xchg_tl(dst, addr, src, mmu_idx, memop | MO_ALIGN);
-}
-
/* asi moves */
typedef enum {
GET_ASI_HELPER,
@@ -2243,14 +2236,15 @@ static void gen_st_asi(DisasContext *dc, DisasASI *da,
TCGv src, TCGv addr)
}
}
-static void gen_swap_asi0(DisasContext *dc, DisasASI *da,
- TCGv dst, TCGv src, TCGv addr)
+static void gen_swap_asi(DisasContext *dc, DisasASI *da,
+ TCGv dst, TCGv src, TCGv addr)
{
switch (da->type) {
case GET_ASI_EXCP:
break;
case GET_ASI_DIRECT:
- gen_swap(dc, dst, src, addr, da->mem_idx, da->memop);
+ tcg_gen_atomic_xchg_tl(dst, addr, src,
+ da->mem_idx, da->memop | MO_ALIGN);
break;
default:
/* ??? Should be DAE_invalid_asi. */
@@ -2259,15 +2253,6 @@ static void gen_swap_asi0(DisasContext *dc, DisasASI *da,
}
}
-static void __attribute__((unused))
-gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn)
-{
- DisasASI da = get_asi(dc, insn, MO_TEUL);
-
- gen_address_mask(dc, addr);
- gen_swap_asi0(dc, &da, dst, src, addr);
-}
-
static void gen_cas_asi0(DisasContext *dc, DisasASI *da,
TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
{
@@ -4725,6 +4710,24 @@ static bool trans_LDSTUB(DisasContext *dc,
arg_r_r_ri_asi *a)
return advance_pc(dc);
}
+static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a)
+{
+ TCGv addr, dst, src;
+ DisasASI da;
+
+ addr = gen_ldst_addr(dc, a->rs1, a->imm, a->rs2_or_imm);
+ if (addr == NULL) {
+ return false;
+ }
+ da = resolve_asi(dc, a->asi, MO_TEUL);
+
+ dst = gen_dest_gpr(dc, a->rd);
+ src = gen_load_gpr(dc, a->rd);
+ gen_swap_asi(dc, &da, dst, src, addr);
+ gen_store_gpr(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4736,7 +4739,7 @@ static bool trans_LDSTUB(DisasContext *dc, arg_r_r_ri_asi
*a)
static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
{
unsigned int opc, rs1, rs2, rd;
- TCGv cpu_src1;
+ TCGv cpu_src1 __attribute__((unused));
TCGv cpu_src2 __attribute__((unused));
TCGv_i32 cpu_src1_32, cpu_src2_32, cpu_dst_32;
TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64;
@@ -5554,6 +5557,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned
int insn)
case 0x9: /* ldsb, load signed byte */
case 0xa: /* ldsh, load signed halfword */
case 0xd: /* ldstub */
+ case 0x0f: /* swap */
case 0x10: /* lda, V9 lduwa, load word alternate */
case 0x11: /* lduba, load unsigned byte alternate */
case 0x12: /* lduha, load unsigned halfword alternate */
@@ -5561,25 +5565,13 @@ static void disas_sparc_legacy(DisasContext *dc,
unsigned int insn)
case 0x19: /* ldsba, load signed byte alternate */
case 0x1a: /* ldsha, load signed halfword alternate */
case 0x1d: /* ldstuba */
+ case 0x1f: /* swapa */
g_assert_not_reached(); /* in decodetree */
case 0x08: /* V9 ldsw */
case 0x0b: /* V9 ldx */
case 0x18: /* V9 ldswa */
case 0x1b: /* V9 ldxa */
goto illegal_insn; /* in decodetree */
- case 0x0f:
- /* swap, swap register with memory. Also atomically */
- cpu_src1 = gen_load_gpr(dc, rd);
- gen_swap(dc, cpu_val, cpu_src1, cpu_addr,
- dc->mem_idx, MO_TEUL);
- break;
-#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
- case 0x1f: /* swapa, swap reg with alt. memory. Also
- atomically */
- cpu_src1 = gen_load_gpr(dc, rd);
- gen_swap_asi(dc, cpu_val, cpu_src1, cpu_addr, insn);
- break;
-#endif
#ifdef TARGET_SPARC64
case 0x2d: /* V9 prefetch, no effect */
goto skip_move;
--
2.34.1
