On 21/10/2023 06:30, Richard Henderson wrote:
Changes for v3:
* Relax v8 simm13 checking for Tcc.
* Split gen_op_addx_int and reorganize to not clobber current cc_op.
* Do not replicate decoding for insns that can set cc_op.
Changes for v2:
* Fixes for JMPL, RETT, SAVE and RESTORE.
* Fixes for FMOV etc, which had lost gen_op_clear_ieee_excp_and_FTT.
* Allow conditional exceptions to be raised out of line
Use this for gen_check_align and conditional trap.
* Keep properties and feature bits in sync.
r~
Richard Henderson (90):
target/sparc: Clear may_lookup for npc == DYNAMIC_PC
target/sparc: Implement check_align inline
target/sparc: Avoid helper_raise_exception in helper_st_asi
target/sparc: Set TCG_GUEST_DEFAULT_MO
configs: Enable MTTCG for sparc, sparc64
target/sparc: Define features via cpu-feature.h.inc
target/sparc: Use CPU_FEATURE_BIT_* for cpu properties
target/sparc: Remove sparcv7 cpu features
target/sparc: Add decodetree infrastructure
target/sparc: Define AM_CHECK for sparc32
target/sparc: Move CALL to decodetree
target/sparc: Move BPcc and Bicc to decodetree
target/sparc: Move BPr to decodetree
target/sparc: Move FBPfcc and FBfcc to decodetree
target/sparc: Merge gen_cond with only caller
target/sparc: Merge gen_fcond with only caller
target/sparc: Merge gen_branch_[an] with only caller
target/sparc: Pass DisasCompare to advance_jump_cond
target/sparc: Move SETHI to decodetree
target/sparc: Move Tcc to decodetree
target/sparc: Move RDASR, STBAR, MEMBAR to decodetree
target/sparc: Move RDPSR, RDHPR to decodetree
target/sparc: Move RDWIM, RDPR to decodetree
target/sparc: Move RDTBR, FLUSHW to decodetree
target/sparc: Move WRASR to decodetree
target/sparc: Move WRPSR, SAVED, RESTORED to decodetree
target/sparc: Move WRWIM, WRPR to decodetree
target/sparc: Move WRTBR, WRHPR to decodetree
target/sparc: Move basic arithmetic to decodetree
target/sparc: Move ADDC to decodetree
target/sparc: Move MULX to decodetree
target/sparc: Move UMUL, SMUL to decodetree
target/sparc: Move SUBC to decodetree
target/sparc: Move UDIVX, SDIVX to decodetree
target/sparc: Move UDIV, SDIV to decodetree
target/sparc: Move TADD, TSUB, MULS to decodetree
target/sparc: Move SLL, SRL, SRA to decodetree
target/sparc: Move MOVcc, MOVR to decodetree
target/sparc: Move POPC to decodetree
target/sparc: Convert remaining v8 coproc insns to decodetree
target/sparc: Move JMPL, RETT, RETURN to decodetree
target/sparc: Move FLUSH, SAVE, RESTORE to decodetree
target/sparc: Move DONE, RETRY to decodetree
target/sparc: Split out resolve_asi
target/sparc: Drop ifdef around get_asi and friends
target/sparc: Split out ldst functions with asi pre-computed
target/sparc: Use tcg_gen_qemu_{ld,st}_i128 for GET_ASI_DTWINX
target/sparc: Move simple integer load/store to decodetree
target/sparc: Move asi integer load/store to decodetree
target/sparc: Move LDSTUB, LDSTUBA to decodetree
target/sparc: Move SWAP, SWAPA to decodetree
target/sparc: Move CASA, CASXA to decodetree
target/sparc: Move PREFETCH, PREFETCHA to decodetree
target/sparc: Split out fp ldst functions with asi precomputed
target/sparc: Move simple fp load/store to decodetree
target/sparc: Move asi fp load/store to decodetree
target/sparc: Move LDFSR, STFSR to decodetree
target/sparc: Merge LDFSR, LDXFSR implementations
target/sparc: Move EDGE* to decodetree
target/sparc: Move ARRAY* to decodetree
target/sparc: Move ADDRALIGN* to decodetree
target/sparc: Move BMASK to decodetree
target/sparc: Move FMOVS, FNEGS, FABSS, FSRC*S, FNOT*S to decodetree
target/sparc: Move FMOVD, FNEGD, FABSD, FSRC*D, FNOT*D to decodetree
target/sparc: Use tcg_gen_vec_{add,sub}*
target/sparc: Move gen_ne_fop_FFF insns to decodetree
target/sparc: Move gen_ne_fop_DDD insns to decodetree
target/sparc: Move PDIST to decodetree
target/sparc: Move gen_gsr_fop_DDD insns to decodetree
target/sparc: Move gen_fop_FF insns to decodetree
target/sparc: Move gen_fop_DD insns to decodetree
target/sparc: Move FSQRTq to decodetree
target/sparc: Move gen_fop_FFF insns to decodetree
target/sparc: Move gen_fop_DDD insns to decodetree
target/sparc: Move gen_fop_QQQ insns to decodetree
target/sparc: Move FSMULD to decodetree
target/sparc: Move FDMULQ to decodetree
target/sparc: Move gen_fop_FD insns to decodetree
target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree
target/sparc: Move FqTOs, FqTOi to decodetree
target/sparc: Move FqTOd, FqTOx to decodetree
target/sparc: Move FiTOq, FsTOq to decodetree
target/sparc: Move FdTOq, FxTOq to decodetree
target/sparc: Move FMOVq, FNEGq, FABSq to decodetree
target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree
target/sparc: Convert FCMP, FCMPE to decodetree
target/sparc: Move FPCMP* to decodetree
target/sparc: Move FPACK16, FPACKFIX to decodetree
target/sparc: Convert FZERO, FONE to decodetree
target/sparc: Remove disas_sparc_legacy
configs/targets/sparc-softmmu.mak | 1 +
configs/targets/sparc64-softmmu.mak | 1 +
linux-user/sparc/target_syscall.h | 6 +-
target/sparc/cpu.h | 76 +-
target/sparc/helper.h | 16 +-
target/sparc/cpu-feature.h.inc | 14 +
target/sparc/insns.decode | 547 +++
target/sparc/cpu.c | 41 +-
target/sparc/fop_helper.c | 17 +-
target/sparc/helper.c | 8 -
target/sparc/ldst_helper.c | 17 +-
target/sparc/translate.c | 7072 +++++++++++++--------------
target/sparc/vis_helper.c | 59 -
target/sparc/meson.build | 3 +
14 files changed, 4127 insertions(+), 3751 deletions(-)
create mode 100644 target/sparc/cpu-feature.h.inc
create mode 100644 target/sparc/insns.decode
Hi Richard,
I've given v3 a run through my entire set of boot tests, and all the 32-bit SPARC
tests now pass. Running through the 64-vit SPARC tests I've found a couple of failures:
[1] ./qemu-system-sparc64 -m 256 -hda netbsd615.qcow2 -snapshot -nographic
(NetBSD)
-> Displays error on boot
[1] Illegal instruction (core dumped) chown root:opera...
[1] Illegal instruction (core dumped) (local line; loc...
init: fatal signal: Illegal instruction
-> Bisected to:
ce60dba1aa7cbf4a4c76b7111b4102ba4734c986 is the first bad commit
commit ce60dba1aa7cbf4a4c76b7111b4102ba4734c986
Author: Richard Henderson <richard.hender...@linaro.org>
Date: Fri Oct 20 22:31:22 2023 -0700
target/sparc: Split out fp ldst functions with asi precomputed
Take the operation size from the MemOp instead of a
separate parameter.
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20231021053158.278135-55-richard.hender...@linaro.org>
target/sparc/translate.c | 136 +++++++++++++++++++++++++++--------------------
1 file changed, 78 insertions(+), 58 deletions(-)
[2] ./qemu-system-sparc64 -M niagara -L niagara/S10image/ -nographic -m 256 -drive
if=pflash,readonly=on,file=niagara/S10image/disk.s10hw2
-> Traps on startup:
qemu: fatal: Trap 0x0010 while trap level (6) >= MAXTL (6), Error state
pc: 0000000000408070 npc: 0000000000408074
%g0-3: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%g4-7: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%o0-3: 0000000000458bf8 000000000042a000 7600000000000000 0000000000000000
%o4-7: ffffffffffffffff 0000000000000000 0000000000000000 0000000000000000
%l0-3: 0000000000000000 0000009800000a00 000000000000001f 0000000000000000
%l4-7: 0000001f12080000 0000000000000000 0000000000458bf8 000000000041446c
%i0-3: 0000000000458900 0000000000458bf8 000000000042a000 000000000042a000
%i4-7: 0000001f12080000 0000000000000000 0000000000000000 0000000000000000
%f00: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f08: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f24: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f32: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f40: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f48: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
%f56: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
pstate: 00000014 ccr: 44 (icc: -Z-- xcc: -Z--) asi: 00 tl: 6 pil: 0 gl: 4
tbr: 0000000000000000 hpstate: 0000000000000804 htba: 0000000000400000
cansave: 6 canrestore: 0 otherwin: 0 wstate: 0 cleanwin: 6 cwp: 0
fsr: 0000000000000000 y: 0000000000000000 fprs: 0000000000000000
Aborted (core dumped)
-> Bisected to:
f483f1fb90c84d5f8a9012836f9e807f809db389 is the first bad commit
commit f483f1fb90c84d5f8a9012836f9e807f809db389
Author: Richard Henderson <richard.hender...@linaro.org>
Date: Fri Oct 20 22:30:56 2023 -0700
target/sparc: Move WRTBR, WRHPR to decodetree
Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Message-Id: <20231021053158.278135-29-richard.hender...@linaro.org>
target/sparc/insns.decode | 9 ++++
target/sparc/translate.c | 110 +++++++++++++++++++++++-----------------------
2 files changed, 65 insertions(+), 54 deletions(-)
ATB,
Mark.
